CN1275317C - Integrated circuit layout plan and buffer plan integrated layout method - Google Patents

Abstract

The present invention relates to a layout method for integrating an integrated circuit layout plan and a buffer plan, which belongs to the field of the aided design of integrated circuit computers. The present invention is characterized in that feasible region calculation is introduced when a buffer is inserted, the complexity of the buffer plan is simplified by the division of a blank region in the results of the layout plan, simulated annealing and a solution procedure are designed aiming at the buffer plan in the layout plan, and the buffer plan is integrated into the solution of the layout plan problem. In the present invention, the buffer plan is infused into the optimization procedure of the layout plan, and thus, the optimization of time delay performance is realized.

Description

Integrated circuit floor planning and the integrated layout method of buffer planning

Technical field

Integrated circuit floor planning and buffer plan that integrated layout method belongs to the integrated circuit CAD field, relate in particular to BBL (Building Block Layout) field.

Background technology

In the layout of integrated circuit; the hierarchy type layout-design; the module reuse technology; the extensive application of ip module; SOC (system on a chip) especially digital-to-analogue is mixed the design of SOC (system on a chip), and analog circuit device level Butut problem etc., these problems can be summed up as the floor planning and the location problem of integrated circuit macroblock; be the Butut problem of Building Block Layout:BBL pattern, it has become current research focus.Especially along with interconnection line shared proportion in Butut is increasing, traditional layout planning method has been ignored the consideration to cloth, has caused can't satisfying the time delay needs in follow-up wiring process.In order to satisfy the time delay demand, often need to insert a large amount of buffers, but buffer itself is to be made of device, need takies certain layout area, also must satisfy certain constraint simultaneously, therefore floor planning and buffer be planned that integrated problem can simply be described as:

Be provided with one and comprise B the set of the square module of size arbitrarily, the shape of module is according to the record successively from the lower-left to the upper right corner of vertex position in the plane, and module has certain direction, provides some net tables and corresponding delay constraint according to the interconnect information between the module.A layout of B module is exactly under the situation of module non-overlapping copies, and module is placed in the plane, and the minimum rectangular area that comprises this B module on the plane is called as chip.Behind the result who has provided floor planning, need determine the position that buffer inserts according to interconnect information, quantity and size make and satisfy the time delay demand as much as possible.It is exactly to seek an optimal location or near-optimization layout that floor planning is combined with buffer planning, and it is optimum that the target function value that makes chip area or other optimization aim form reaches, and makes the minimum number of buffer simultaneously, and delay performance is best.

In recent years, the buffer planning problem is subjected to paying close attention to widely, and people have proposed the method for a variety of buffer planning.Constitute because buffer is a device,, a lot of relevant work have also been arranged in the BBL stage so these method majorities utilize the clear area in the layout to insert buffer; For example the notion of the area of feasible solutions (feasible region) that proposes the earliest is used for producing buffer module; The area of feasible solutions of buffer is meant under the condition of the target time-delay of satisfying gauze, the possible maximum region that buffer can be placed.After a while, the feasible region is expanded into independent feasible region, and the crowding that connects up simultaneously is optimized.The method of network flow has only under the situation of a buffer at each gauze of hypothesis, can find optimal solution.The method of many commodity streams arrives already present buffer module in advance with buffer allocation.The dynamic programming method hypothesis also allows to insert buffer in macroblock inside, and therefore this method can make the point that inserts buffer be distributed in each position of layout.The layout planning method of cloth driving can be estimated the consumption and the buffer resources of buffer for the crowding constraint.The layout planning method that integrated buffer/passage inserts is used for the microprocessor Design based on bus.Most up to now layout method and buffer planning are all separate, buffer planning can not be considered in the floor planning process, to produce the floor planning result who more helps delay performance.From the result who obtains, also has very large gap with practical application.

Summary of the invention

Other algorithm that the objective of the invention is to propose a kind of this field more up to now is more stable, efficient, and can in the floor planning process, realize making rational planning for to buffer, and buffer planning combined with Butut result's optimization, buffer planning is as the industrial instrument of solution macroblock Butut problem in the processing integrated circuit macroblock floor planning.Under Elmore time delay model, square the growing proportionately of the time delay of long line and line length, and utilize buffer insertion technology, time delay and the line length that can control line are the linear growth relation.For satisfying delay constraint, need the number of buffers inserted with process reduce and sustainable growth.Because buffer need take silicon resource, so in design process, buffer should be planned as early as possible, especially at layout stage, to improve the delay performance of circuit as far as possible.

The invention is characterized in: the area of feasible solutions that it has been introduced when buffer inserts is calculated, and the division of the white space by in the floor planning result, simplified the complexity of buffer planning, design at the buffer in floor planning planning optimization solution procedure, the planning of buffer is integrated in the solution procedure of floor planning problem simulated annealing.It contains following steps successively:

1) computer is carried out initialization, is provided with and imports following parameter:

(1) parameter setting in the simulated annealing process comprises interior cycle-index, initial temperature and end temp, annealing factor a;

(2) the wide long R of target and the weights omega thereof of final layout chip are set;

(3) weight of total line length and the weight γ that buffer inserts are set;

(4) size of buffer in the target function and the size that buffer inserts grid are set;

(5) the relevant various performance parameters of buffer is set, comprises load capacitance, drive output resistance, buffer output resistance, buffer input capacitance, the intrinsic time delay of buffer, unit length line capacitance, unit length line resistance;

2) computer reads in module and gauze information from module description file:

(1). read in the module four angular coordinate, and wide, high according to module four angular coordinate computing module;

(2). read in lead end coordinate on the module, and be translated into the coordinate in the relative module lower left corner;

(3). number to module by reading in order, and calculate total number of modules, each module net area sum;

(4). read in gauze information, comprise the interconnection situation of lead end, the delay constraint in the gauze.

Gauze in circuit meshwork list generally is the multiterminal gauze, and promptly a gauze has a plurality of lead ends, and for the ease of time-delay calculation and the reasonable model of simplifying the buffer insertion, we split into the two ends gauze with the multiterminal gauze: promptly multiterminal gauze E has m lead end p ₁(x ₁, y ₁) ..., p _m(x _m, y _m), then we are split into m-1 two ends gauze (p ₁, p ₂), (p ₁, p ₃), (p ₁, p ₄) ..., (p ₁, p _m).We have obtained corresponding two ends gauze net table information corresponding to former wired network like this, and can carry out the planning of buffer according to two ends gauze information.

3) according to module information, the topological structure of random configuration initial layout is the position relation of intermodule, we adopt the expression of angle mould piece sequence method for expressing as module placement in the method, according to the order that reads in module, the logical topology relation of random configuration intermodule, constitute a layout, and as initial layout Q ₀

4) enter the simulated annealing optimization process, represent to calculate location problem optimum or approximate optimal solution as basic layout method for expressing with angle mould piece sequence

From initial temperature, calculate optimum or approximate optimal solution under the Current Temperatures, Current Temperatures is designated as Tnow:

[1]. calculate each gauze line length estimated value according to following formula, and total line length estimated value, the line length of single gauze is estimated with the semi-perimeter model according to the lead end position in the gauze:

If certain gauze E has m lead end p ₁(x ₁, y ₁) ..., p _m(x _m, y _m); Then: the line length WireLength (E) of this gauze estimates with following formula,

$\mathrm{WireLength}\left(E\right)=(\underset{i\∈\{1,...,m\}}{\max }\left(x_i\right)-\underset{j\∈\{1,...,m\}}{\min }\left(x_j\right))+(\underset{i\∈\{1,...,m\}}{\max }\left(y_i\right)-\underset{j\∈\{1,...,m\}}{\min }\left(y_j\right))$

Wherein, j is the lead end numbering,

Total line length estimated value is:

$\mathrm{TotalWireLength}=\underset{k=1}{\overset{L}{\mathrm{\Σ}}}\mathrm{WireLength}\left(E\right),$ L is the number of gauze

[2]. the white space in the layout that calculates, and be divided into rectangular module, the clear area rectangular module that obtains be divided into fixed size in order to put down the little rectangle of one or several buffer.

[3]. according to each two ends gauze, whether the length of judging gauze is greater than critical length l _Crit, if the length of two ends gauze is less than critical length, it is zero that then current gauze inserts number of buffers, the computing formula of critical length is as follows:

$l_{\mathrm{crit}}=\frac{R_b-R_d}{r}+\frac{C_b-C_l}{c}+2\sqrt{\frac{R_b{C}_b+T_b}{\mathrm{rc}}}---\left(1\right)$

Wherein:

R _b: buffer output resistance (Ω),

R _d: drive output resistance (Ω),

C _b: buffer input capacitance (fF),

C _l: load capacitance (fF),

R: unit length line resistance (Ω/μ m),

C: unit length line capacitance (fF/ μ m),

T _b: buffer inherent delay (ps);

[4]. calculate each two ends gauze N because do not satisfy the number of buffers of delay constraint needs insertion and the independent area of feasible solutions of each buffer:

(4.1). calculate the number of buffers k that gauze satisfies the delay constraint needs _Min:

Wherein:

K ₁＝R _bC _b+T _b (3)

K ₂＝(rC _b+cR _b)l+T _b+R _dC _b+R _bC _l-T _con

$-\frac{r}{2c}{(C_b-C_l)}^2-\frac{c}{2r}{(R_b-R_d)}^2---\left(4\right)$

${\mathrm{<figure-callout\; id="3"\; label="K"\; filenames="C20031011554500191.png"\; state="\{\{state\}\}">K</figure-callout>}}_3=\frac{1}{2}\mathrm{rc}{l}^2+(r{C}_l+c{R}_d)l+R_d{C}_l-T_{\mathrm{con}}---\left(5\right)$

Wherein:

L is a gauze length,

R _b: buffer output resistance (Ω),

R _d: drive output resistance (Ω),

C _b: buffer input capacitance (fF),

C _l: load capacitance (fF),

R: unit length line resistance (Ω/μ m),

C: unit length line capacitance (fF/ μ m),

T _b: buffer inherent delay (ps),

T ^N _ConDelay constraint for gauze N;

(4.2). calculate the independent area of feasible solutions of each buffer among the gauze N:

Length is that the independent area of feasible solutions of j buffer of the gauze N of l is:

$\mathrm{IF}{R}_j=(x_{\mathrm{opt}}^j-W_{\mathrm{ifr}}/2,x_{\mathrm{opt}}^j+W_{\mathrm{ifr}}/2)I(0,l)---\left(6\right)$

W _IfrBe the width of independent area of feasible solutions,

$W_{\mathrm{ifr}}=2\&CenterDot;\sqrt{\frac{T_{\mathrm{con}}^N-T_{\mathrm{opt}}^N(k_{\min },l)}{\mathrm{rc}(2k_{\min }-1)}}---\left(7\right)$

Wherein, k _MinBe number of buffers,

T _Con ^NBe the delay constraint of gauze N,

T _Opt ^NFor inserting k among the gauze N _MinThe optimum time delay of individual buffer,

$T_{\mathrm{opt}}^N\left(k_{\min ,l}\right)=T^N(x_{\mathrm{opt}}^1,x_{\mathrm{opt}}^2,......,x_{\mathrm{opt}}^{k_{\min }},l)$

$=\frac{\mathrm{rl}(k_{\min }{C}_b+C_l)+\mathrm{cl}(R_d+k_{\min }{R}_b)+(k_{\min }{C}_b+C_l)(k_{\min }{R}_b+R_d)}{k_{\min }+1}$

$+k_{\min }{T}_b+\frac{\mathrm{rc}{l}^2-k_{\min }r{(C_b-C_l)}^2/c-k_{\min }c{(R_b-R_d)}^2/r}{2(k_{\min }+1)}---\left(8\right)$

x _Opt ^jBeing the Manhattan distance (only comprising the horizontal and vertical lines section) of the relative gauze of buffer source end, also is the position of j buffer;

$x_{\mathrm{opt}}^j=(j-1)y_l+x_{l}j\&Element;\{\mathrm{1,2},...,k_{\min }\}---\left(9\right)$

Wherein:

$\left\{\begin{array}{c}{x}_1=\frac{1}{k_{\min }+1}(l+\frac{k_{\min }(R_b-R_d)}{r}+\frac{(C_l-C_b)}{c})\\ y_l=\frac{1}{k_{\min }+1}(l-\frac{(R_b-R_d)}{r}+\frac{(C_l-C_b)}{c})\end{array}\right.---\left(10\right)$

[5]. calculate the two ends gauze number N that satisfies the target time delay _Old

(5.1). calculate the candidate location sets of each buffer:

(5.1.1). calculate the source end of buffer place gauze and the friendship DF of determined rectangular area of drain terminal and clear area _Ol

(5.1.2). calculate DF _OlWith the friendship of the independent area of feasible solutions of buffer, work as DF _OlThe lower left corner of interior certain position is positioned at the independent area of feasible solutions of buffer, and then this position is the candidate position of respective buffer;

(5.1.3). be selected in the candidate position of above-mentioned buffer that buffer candidate position is minimum does not place the position of the position of buffer as buffer with fashion;

(5.2). check each two ends gauze, add up required buffer and fail the line screens that all insert, be designated as N _Notsat

[6]. estimate Q with following formula, obtain target function value Cost;

Cost _Q＝Area+λ×TotalWireLength+ω×Rs ²+γ×N _notsat；(11)

Wherein: $\mathrm{Area}=\underset{o\&Element;[1...n]}{\max \left\{x_i\right\}}\&times;\underset{i\&Element;[1...n]}{\max \left\{y_i\right\}}$

TotalWireLength (total line length) is each gauze estimation length sum;

λ is the weight of total line length, and ω is the weight of breadth length ratio, and γ is the weight that buffer inserts;

If R is the chip breadth length ratio of expectation, ratio is the actual breadth length ratio of chip, then:

Rs＝|R-max(ratio，1/ratio)|；

5) the current layout Qnow of output.

6) calculate the temperature of next annealed condition with following formula

Tnow=a*Tnow: wherein a is the annealing factor, 7) general value is 0.95.

If Current Temperatures greater than end temp Tnow＞Tend, then enters the solution procedure of next annealed condition;

If Current Temperatures is less than end temp Tnow＜Tend, 8) then output current layout be final layout.

Step 3) and step 4) described angle mould piece sequence and the angle mould piece sequence of being utilized in the simulated annealing process represent to be based on the Butut method for expressing of logical topology between the module, it is a kind of effective method for expressing that proposed in 2000 by the Hong Xianlong professor, the layout method that detailed angle mould piece sequence is represented does not belong to the present patent application content, and simple introduction is done in the definition of just representing at the angle mould piece that will utilize required for the present invention below.The angle mould piece represents it mainly is with (T) tlv triple string logging modle is from the Butut order in the lower left corner to the upper right corner and the topological relation between the module for S, L.Wherein the S string writes down the title of each module, and the orientation when L string logging modle is put comprises two kinds of orientation, and vertical orientations represents that this module covers other cloth modules downwards from the top, and level orientation represents that this module is from right-hand other cloth modules that covers left.The corresponding expression in the T string of the concrete number of modules that covers.Expression in simulated annealing for convenience, the T string has adopted binary sequence, represents that with the substring length of continuous " 1 " and one " 0 " total what modules are covered when front module.Along with module putting successively, the coordinate of each module all draws, and can calculate the size and the length-width ratio of chip.

The described simulated annealing process of step 4) is used to ask for the optimal result of layout, and its flow process is as follows:

When current cycle time during, be repeated below step less than interior cycle-index:

Produce new layout with one of following method from current layout Qnow, new topological structure be designated as Qnew:

Change the topological structure of layout, use following method:

(1). S goes here and there the order of any two modules in the exchange angle mould piece sequence;

(2). the direction of any one module among the L in the angle mould piece sequence is changed;

(3). change in the angle mould piece sequence T string any one.

Change the module direction when helping optimizing line length, use following method:

(4). select a module to be rotated at random, the anglec of rotation is chosen for 90 ° by random function, or 180 °, or 270 °;

(5). select a module to overturn at random, trip shaft is chosen for trunnion axis by random function, or vertical axis or module diagonal;

Calculate layout result according to the new explanation Qnew that produces, and carry out following operation:

If exp ((Cost _Qnew-Cost _Q)/Tnow)＞r; (r is the random number between 0 to 1)

Then accept new explanation, current separating is set to new explanation, i.e. Q=Qnew;

Otherwise do not accept new explanation, current layout remains Q.

Finish once circulation, current cycle time adds up 1 time;

The test explanation: the present invention has increased buffer insertion rate, has also increased the line screen that satisfies delay constraint simultaneously, has improved the circuit time delay characteristic.

Description of drawings

Fig. 1. the example that layout and clear area and Pad distribute.

Fig. 2. the simulated annealing flow chart.

Fig. 3. buffer independence area of feasible solutions and position candidate calculating chart.

Fig. 4. buffer independence area of feasible solutions is calculated schematic diagram.

The integrated buffer planning back Butut result of Fig. 5 .MCNC test case ami33.

Embodiment

The present invention can be applied to different floor planning/layouts of dividing based on rectangle and represent that (that is to say such Butut represent chip is divided into the rectangular area of number more than or equal to number of modules, each rectangular area has a module at the most simultaneously) realize down.The layout result that this part adopts the angle mould piece to represent as an example of the present invention, and adopts the model of Elmore time delay model as time-delay calculation.Carried out buffer in conjunction with the flow chart of Fig. 2 integrated with method of the present invention and inserted the floor planning of planning.Table one is the definition and the numerical value of some variablees.

Table one

r	The unit length line resistance (/m)	0.0755
			c	Unit length line capacitance (fF/m)	0.118
T b	The intrinsic time delay of buffer (ps)	36.4
			C b	Buffer input capacitance (fF)	23.4
R b	Buffer output resistance ()	180
			R d	Drive output resistance ()	180
C l	Load capacitance (fF)	23.4

Doing example with ami33 among the international benchmark test practical circuit MCNC carries out module placement in conjunction with Fig. 2 with method of the present invention it has the following steps successively:

1. initialization

(1). simulated annealing initial temperature Tstart=3000 is set, simulated annealing end temp Tend=500, interior cycle-index Repeat=1000;

(2). the target breadth length ratio (R=1.0) and the weight thereof of final layout are set;

(3). the weight of total line length in the target function is set.

(4). the size of buffer and the size that buffer inserts grid (size that buffer insertion grid is set is consistent with buffer sizes) are set

2. read in module information and gauze information

Comprise 33 square module among the test case ami33, gauze one has 123;

Each multiterminal gauze (three or three above pins are arranged) is split as follows: owing to do not comprise the source end and the drain terminal information of gauze in the test circuit, so specify a justice pin as the source end arbitrarily, other pins are as drain terminal; A gauze that comprises n pin is split into n-1 two ends gauze, in the ami33 test case, split out 363 two ends gauzes altogether.

3. 33 modules in the test case are carried out label according to reading in order, and the composition module sequence represents that its Butut is the S sequence during the angle mould piece is represented in proper order, and produces 0,1 string list and show that L string and T go here and there that it is as follows to construct initial solution thus:

S＝{block1，block2，block3，block4，...，block33)

L＝{1，0，1，0，...，1，0}

T＝{0 10 110 10 0 10 110 1110 110 10 0……}

Orientation when L string logging modle is put comprises two kinds of orientation, and 0 expression vertical orientations represents that this module covers other cloth modules downwards from the top, 1 expression vertical orientations, and level orientation represents that this module is from right-hand other cloth modules that covers left.The corresponding expression in the T string of the concrete number of modules that covers, the T string has adopted binary sequence, represents that with the substring length of continuous " 1 " and one " 0 " total what modules are covered when front module.

4. following steps are carried out according to the simulated annealing flow process among Fig. 2, and concrete outcome is seen Fig. 4 and table 3.Planning with floor planning and buffer in the simulated annealing process combines, and represents layout with angle mould piece sequence, calculates all clear areas in the layout, and they are divided into piece, and is associated with module; Method is as follows: (detailed expression does not belong to the content of present patent application to the transfer algorithm of layout, so carefully do not state here)

Represent in the transfer process of layout, to calculate the coordinate time of each module at angle mould piece sequence Butut:

Each more adjacent module if having dummy section between two modules, is associated this dummy section and the module that is capped; Module M as shown in figure one ₁From top overlay module M ₂With module M ₃, because module M ₁With module M ₃Between have dummy section, we are divided into dummy section module D with this dummy section ₁, and with itself and module M ₃Be associated, same module M4 is from right-hand overlay module M3 and M1, owing to have dummy section between module M4 and the M1, we are divided into dummy section module D2. with this dummy section

Resume module finishes, if between the module of the coboundary of chip or right margin and border, have the clear area, then with the clear area and the module that is positioned at the border accordingly be associated; As above border overlay module M1 and module M4, owing to have the clear area between coboundary and the module M4, we are divided into dummy section module D3. with it

Careful division is carried out in all clear areas, promptly the clear area carefully is divided into the little rectangle that to put next buffer of fixed size;

Each two ends gauze is finished following operation

Calculate critical length l according to following existing formula _CritIf two ends gauze length is greater than l _Crit, continue following steps, be zero otherwise current gauze inserts number of buffers;

$l_{\mathrm{crit}}=\frac{R_b-R_d}{r}+\frac{C_b-C_l}{c}+2\sqrt{\frac{R_b{C}_b+T_b}{\mathrm{rc}}}---\left(1\right)$

Wherein, R _b, C _b, T _b, R _d, C _l, r and c meaning are as shown in Table 1; Calculate l _Crit=4270.

Calculate under the condition of inserting buffer with following existing method, minimize the number of buffers that time delay needs:

The two ends gauze that a given length is l, the Elmore time delay of this gauze can be defined as follows:

$T(R_d,C_l,l)=\left(\frac{\mathrm{rc}}{2}\right)l^2+(R_{d}c+r{C}_l)l+R_d{C}_l---\left(2\right)$

Wherein each parameter meaning as shown in Table 1;

For length is l, has inserted the gauze of n buffer, reach the purpose that minimizes the gauze time delay, and the optimal location of n buffer is:

Illustrate: the position of this paper buffer and the calculating of following feasible region relate to the position problems in the gauze, all refer to the Manhattan distance (only comprising the horizontal and vertical lines section) of relative gauze source end, for example gauze length just is meant the Manhattan distance of source end to drain terminal.

The position of j buffer is x _Opt ^j

$x_{\mathrm{opt}}^l=(j-1)y_l+x_{l}j\&Element;\{\mathrm{1,2},...n\}---\left(3\right)$

Wherein:

$\left\{\begin{array}{c}{x}_l=\frac{1}{n+1}(l+\frac{n(R_b-R_d)}{r}+\frac{(C_l-C_b)}{c})\\ y_l=\frac{1}{n+1}(l-\frac{(R_b-R_d)}{r}+\frac{(C_l+C_b)}{c})\end{array}\right.---\left(4\right)$

Article one, length is the gauze (two ends gauze) of the single drain terminal of Dan Yuanduan of l, inserts the time delay of n buffer and can calculate with following formula.

$T^N(x_1,x_2,...,x_n,l)=T(R_d,C_b,x_1)+T(R_b,C_l,l-x_n)$

$+\underset{q=1}{\overset{n-1}{\mathrm{\&Sigma;}}}T(R_b,C_b,x_{q+1}-x_q)+n{T}_b---\left(5\right)$

Wherein the definition of function T is with (2), each parameter meaning as shown in Table 1, x _jIt is the position of j buffer.

Length is that the optimum time delay of the gauze N of n buffer of l insertion can be calculated according to formula (2), (3), (4) and (5), is designated as:

$T_{\mathrm{opt}}^N(n,l)=T^N(x_{\mathrm{opt}}^1,x_{\mathrm{opt}}^2,......,x_{\mathrm{opt}}^n,l)$

$=\frac{\mathrm{rl}(n{C}_b+C_l)+\mathrm{cl}(R_d+n{R}_b)+(n{C}_b+C_l)(n{R}_b+R_d)}{n+1}$

$+n{T}_b+\frac{\mathrm{rc}{l}^2-\mathrm{nr}{(C_b-C_l)}^2/c-\mathrm{nc}{(R_b-R_d)}^2/r}{2(n+1)}---\left(6\right)$

In sum, gauze N will reach the number of buffers that optimum time delay needs, and can calculate as follows:

Insert buffer in the source of two ends gauze with between leaking since 1 by the mode that increases progressively 1 buffer at every turn, cause the gauze time-delay to increase if insert k+1 buffer, this gauze reaches optimum the time-delay so needs k buffer; Be that number of buffers k satisfies following formula: $T_{\mathrm{opt}}^N(k,l)<T_{\mathrm{opt}}^N(k+1,l),$ Can solve the expression formula of k by this formula:

Each gauze is finished following calculating:

According to providing delay constraint T among following existing formula and the 1.c _ConThe number of buffers of gauze constraint needs is satisfied in calculating;

Wherein:

K ₁＝R _bC _b+T _b (9)

K ₂＝(rC _b+cR _b)l+T _b+R _dC _b+R _bC _l-T _con

$-\frac{r}{2c}{(C_b-C_l)}^2-\frac{c}{2r}{(R_b+R_d)}^2---\left(10\right)$

${\mathrm{<figure-callout\; id="3"\; label="K"\; filenames="C20031011554500191.png"\; state="\{\{state\}\}">K</figure-callout>}}_3=\frac{1}{2}\mathrm{rc}{l}^2+(r{C}_l+c{R}_d)l+R_d{C}_l-T_{\mathrm{con}}---\left(11\right)$

Wherein, the meaning of each parameter as shown in Table 1.

To each two ends gauze, calculate the buffer number k that satisfies the insertion of delay constraint needs according to formula _MinAnd (the independent area of feasible solutions of buffer b is meant and is satisfying under the delay constraint condition of gauze under the b to calculate the independent area of feasible solutions of each buffer, other buffers of supposing the affiliated gauze of this buffer all are placed in their the independent area of feasible solutions separately, can insert the maximum region of buffer b, Fig. 3 provides example, gauze source end and drain terminal are respectively the lower left corner and the upper right corner of frame of broken lines, and the independent feasible region of buffer is two 135 common factors of spending oblique line and rectangular broken line frame);

Calculate the independent area of feasible solutions of each buffer according to following existing method;

Length is that the independent area of feasible solutions of j buffer of the gauze N of l is:

$\mathrm{IF}{R}_j=(x_{\mathrm{opt}}^j-W_{\mathrm{ifr}}/2,x_{\mathrm{opt}}^j+W_{\mathrm{ifr}}/2)I(0,l)---\left(12\right)$

Wherein, x _Opt ^jThe same formula of meaning (3), W _IfrRepresent the width of independent area of feasible solutions; Promptly insert k _MinThe optimal location of individual buffer; Make following formula set up:

$\&ForAll;(x_1,x_2,...,x_i,...,x_{k_{\min }})\&Element;\mathrm{IF}{R}_1\&times;\mathrm{IF}{R}_2\&times;...\&times;\mathrm{IF}{R}_n,$

$T^N(x_1,x_2,......,x_{k_{\min }},l)\&le;T_{\mathrm{con}}^N---\left(13\right)$

X wherein _iBe the position of the relative source of buffer end, T _Con ^NBe the delay constraint relevant with gauze N; W _IfrCan be calculated as follows.

$W_{\mathrm{ifr}}=2\&CenterDot;\sqrt{\frac{T_{\mathrm{con}}^N-T_{\mathrm{opt}}^N(k_{\min },l)}{\mathrm{rc}(2k_{\min }-1)}}---\left(14\right)$

T wherein _Con ^NAnd T _Opt ^N(k _Min, l) be delay constraint and the insertion k of gauze N _MinThe optimum time delay of individual buffer, r, the meaning of c is as shown in Table 1.T _Opt ^N(k _Min, l) can be by k _MinN in the replacement formula (6) calculates.

In sum, the independent area of feasible solutions of the buffer of specific gauze can be calculated by (3), (4), (12), (14).Calculate the candidate insertion position set of each buffer;

Calculate the source end of buffer place gauze and the friendship (promptly calculating the friendship of two rectangles) of determined rectangular area of drain terminal and clear area; The result is designated as DF _Ol(as Fig. 3, the rectangle bold box is DF _O1);

Calculate DF _OlFriendship with the independent area of feasible solutions of buffer.If DF _OlIn the lower left corner of certain buffer insertion position be positioned at the independent area of feasible solutions of buffer, we think the position candidate that this buffer insertion position is a respective buffer so.(shown in Figure 3 oblique line institute cover part)

We can see that gauze source, two ends end is s (350,1575) in Fig. 3, and drain terminal is t (4725,5915);

The calculating relevant with gauze:

Gauze length is (4725-350)+(5915-1575)=8715;

Calculate critical length l _Crit=4270;

Calculate corresponding optimum time delay T according to formula (6) _Opt=517; Delay constraint is T _Con=398.7; K according to concrete implementation step formula (8) calculating _Min=2; Calculate W according to formula (14) _Ifr(width of independent area of feasible solutions):

W _ifr＝1239

Calculate according to formula (4)

x ₁＝2905

y ₁＝2905

Calculate according to formula (3) and (12) and apart from line segment to be apart from source point (350,1575):

IFR ₁＝(2285，3524)

IFR ₂＝(5190，6429)

According to as shown in Figure 4, b1, two oblique line institute area surrounded at b2 place are respectively the independent area of feasible solutions of two buffers;

Calculate as follows at initial clear area branch and plant the two ends gauze number that satisfies the target time delay, we amplify the buffer area of feasible solutions of b2 correspondence as shown in Figure 3;

Each buffer is determined the position of buffer by following heuristic:

In the candidate insertion position of this buffer, be selected to buffer position candidate least number of times and do not place the position of the insertion position of buffer as this buffer with fashion;

Check each two ends gauze, add up the line screen N that required buffer all inserts, and calculate the line screen N that buffer fails and inserts owing to the module position restriction _Notsat

Calculate the cost of current layout correspondence according to 4. (6) cost function formula, and compare, produce corresponding new explanation, and further in the simulated annealing process, carry out iteration, finish up to the simulated annealing process with former cost function.

Specific to initial solution in the annealing process be:

(1)S＝{block1，block2，block3，block4，...，block33}

L＝{1，0，1，0，...，1，0}

T＝{0 10 110 10 0 10 110 1110 110 10 0……}

Calculating line length according to formula (4) gets: TotalWirelength=5352486,

Layout area: Area=111499550

The ratio of width to height: Rs=0.504

Gauze satisfies number and is N _Notsat=82;

Cost _Q＝Area+λ×TotalWireLength+ω×Rs ²+γ×N _notsat＝165108024

Preserve Cost _Min=Cost _Q

(2) carry out layout optimization

According to random value selection scheme 1) generate new explanation:

Block14 exchanges mutually with block32

S＝{block1，block2，block3，…block13，block32，block15...，block31，block14，block33}

L＝{1，0，1，0，...，1，0}

T＝{0 10 110 10 0 10 110 1110 110 10 0……}

Calculating line length according to formula (4) gets: TotalWirelength=5431429,

Layout area: Area=111499550

The ratio of width to height: Rs=0.504

Gauze satisfies number and is N _Notsat=95;

Cost _Q＝Area+λ×TotalWireLength+ω×Rs ²+γ×N _notsat＝165364896

Do not satisfy Cost _Q＜Cost _Min, therefore do not write down this and separate.

(3) value of random number r is 0.53, because exp ((Cost _Qnew-Cost _QThe condition of accepting new explanation of)/Tnow)＞r does not satisfy, and therefore gets back to former separating, and block14 and block32 are exchanged again.

(4) loop arrangement optimizing process (2), (3) 1000 times.

(5) because do not satisfy T＜500 (end temp), produce new annealing temperature T=7600, turn to (3.2.3), step (3.2.3)-(3.2.9) is carried out in circulation, up to satisfying T＜500.Export corresponding to Cost at last _MinOptimal solution.

According to shown in parameter value, we provide experimental result (if no special instructions, the unit of length and coordinate is micron (μ m), chronomere is psec (ps)): Fig. 5 is the Butut result of ami33 in the MCNC test case, has wherein inserted 154 buffers to satisfy the constraint of time delay at white space.

Attached experimental result

Table two

Circuit	Number of modules	2-end line netting index	Area (mm 2 )	Line length (mm)	Insert number/need number	met	Violate constraint	Running time (second)
									Xerox	10	455	85.4 1	1327	214/303	370	51	59
Ami33	33	363	31.1 5	461. 2	154/214	294	39	206
									Ami49	49	545	146. 6	2920	244/568	341	151	329
Apte	0	172	48.1 4	459. 5	44/107	113	49	27
									Hp	11	226	38.8 6	392. 2	40/106	163	43	29

Wherein: the MCNC test circuit has 5 circuit, comprises Xerox, Ami33, and Ami49, Apte, five circuit of Hp, number of modules wherein and gauze number are as shown in Table 2." met " is for satisfying the line screen of delay constraint; " insertion number " is the total number that successfully inserts the clear area buffer; " need number " and be required buffer total number; " violate constraint " for violating the line screen (the optimum time delay that is gauze is greater than delay constraint) of delay constraint.

The hardware that the present invention uses is the v880 work station of a Sun Microsystems; Use Unix operating system. Buffer planning algorithm of the present invention has following advantage:

(1). the buffer planning algorithm is combined with the optimizing process of floor planning;

(2). utilize the clear area among the Butut result to distribute to carry out the insertion of buffer, realize the optimization to delay performance, be conducive to finishing smoothly of follow-up design;

(3). have industrial application value, can be used for the IC design process: the interconnect planning problem in module level floor planning/layout.

Claims (1)

1. integrated circuit floor planning and buffer are planned integrated layout method, it is characterized in that: it is that a kind of area of feasible solutions of having introduced when buffer inserts is calculated, and by carrying the division of the white space among the floor planning result, so that the planning of buffer is integrated in the method for the integrated Butut in the solution procedure of floor planning problem, it contains following steps successively:

(1). computer program is carried out initialization, make and import following parameter:

(1.1). parameter setting in the simulated annealing process comprises interior cycle-index, initial temperature and end temp;

(1.2). the wide long R of target and the weights omega thereof of final layout chip are set;

(1.3). the weight λ of total line length and the weight γ that buffer inserts are set;

(1.4). the size of buffer in the target function and the size that buffer inserts grid are set.

(1.5). the relevant various performance parameters of buffer is set, comprises load capacitance, drive output resistance, buffer output resistance, buffer input capacitance, the intrinsic time delay of buffer, unit length line capacitance, unit length line resistance;

(2). computer reads in module and gauze information from module description file:

(2.1). read in the module four angular coordinate, and wide, high according to module four angular coordinate computing module;

(2.2). read in lead end coordinate on the module, and be translated into the coordinate in the relative module lower left corner;

(2.3). number to module by reading in order, and calculate total number of modules, each module net area sum;

(2.4). read in gauze information, comprise the interconnection situation of lead end, the delay constraint in the gauze;

The multiterminal gauze E that m lead end arranged is split into m-1 two ends gauze N, carry out buffer planning according to two ends gauze information again;

(3). according to module information, the topological structure of random configuration initial layout is the position relation of intermodule, with angle mould piece sequence method for expressing as the representing of module placement, according to the order that reads in module, random configuration initial layout Q ₀Topological structure;

(4). enter the simulated annealing optimization process, calculate location problem optimum or approximate optimal solution.

From initial temperature, calculate optimum or approximate optimal solution under the Current Temperatures Tnow, it comprises following steps successively:

(4.1). calculate each gauze line length estimated value and total line length estimated value according to following formula, wherein, the line length of single gauze is estimated with the semi-perimeter model according to the lead end position in the gauze:

If: certain gauze E has m lead end p ₁(x ₁, y ₁) ..., p _m(x _m, y _m);

Then: the line length WireLength (E) of this gauze estimates with following formula,

$\mathrm{WireLength}\left(E\right)=(\underset{i\&Element;\{1,...,m\}}{\max }\left(x_i\right)-\underset{j\&Element;\{1,...,m\}}{\min }\left(x_j\right))+(\underset{i\&Element;\{1,...,m\}}{\max }\left(y_i\right)-\underset{j\&Element;\{1,...,m\}}{\min }\left(y_j\right))$

Wherein, i, j are the lead end numbering,

Total line length estimated value is:

$\mathrm{TotalWireLength}=\underset{k=1}{\overset{L}{\mathrm{\&Sigma;}}}\mathrm{WireLength}\left(E\right),$ L is the number of gauze;

(4.2) white space in the layout that calculates, and be divided into rectangular module, again the clear area rectangular module carefully be divided into fixed size in order to put down the little rectangle of one or several buffer; (4.3) judge that according to following formula whether two ends gauze N length is greater than critical length l _Crit,

$l_{\mathrm{crit}}=\frac{R_b-R_d}{r}+\frac{C_b-C_l}{c}+2\sqrt{\frac{R_b{C}_b+T_b}{\mathrm{rc}}}$

Wherein:

R _b: buffer output resistance (Ω),

R _d: drive output resistance (Ω),

C _b: buffer input capacitance (fF),

C _l: load capacitance (fF),

R: unit length line resistance (Ω/μ m),

C: unit length line capacitance (fF/ μ m),

T _b: buffer inherent delay (ps);

If: the length l≤l of two ends gauze _Crit

Then: it is zero that current gauze inserts number of buffers;

(4.4) calculate each two ends gauze because do not satisfy the number of buffers of delay constraint needs insertion and the independent area of feasible solutions of each buffer:

(4.4.1). calculate the number of buffers k that each two ends gauze satisfies the delay constraint needs _Min:

Wherein:

K ₁＝R _bC _b+T _b (9)

$K_2=(r{C}_b+c{R}_b)l+T_b+R_d{C}_b+R_b{C}_l-T_{\mathrm{con}}-\frac{r}{2c}(C_b-C_l)2-\frac{c}{2r}{(R_b-R_d)}^2---\left(10\right)$

$K_3=\frac{1}{2}{\mathrm{rcl}}^2+({\mathrm{rC}}_l+{\mathrm{cR}}_d)l+R_d{C}_l-T_{\mathrm{con}}---\left(11\right)$

Wherein:

L is a gauze length,

R _b: buffer output resistance (Ω),

R _d: drive output resistance (Ω),

C _b: buffer input capacitance (fF),

C _l: load capacitance (fF),

R: unit length line resistance (Ω/μ m),

C: unit length line capacitance (fF/ μ m),

T _b: buffer inherent delay (ps),

T _ConDelay constraint for gauze;

(4.4.2). calculate the independent area of feasible solutions of each buffer in the gauze of two ends:

Length is that the independent area of feasible solutions of j buffer of the two ends gauze N of l is:

${\mathrm{IFR}}_j=(x_{\mathrm{opi}}^j-W_{\mathrm{ifr}}/2,x_{\mathrm{opt}}^j+W_{\mathrm{ifr}}/2)I(0,l),$

W wherein _IfrBe the width of independent area of feasible solutions,

$W_{\mathrm{ifr}}=2\&CenterDot;\sqrt{\frac{T_{\mathrm{con}}^N-T_{\mathrm{opt}}^N(k_{\min },l)}{\mathrm{rc}({2k}_{\min }-1)}}$

Wherein, k _MinBe the buffer number,

T _Con ^NBe the delay constraint of two ends gauze N,

T _Opt ^NFor inserting k among the gauze N of two ends _MinThe optimum time delay of individual buffer,

$T_{\mathrm{opt}}^N(k_{\min },l)=T^N(x_{\mathrm{opt}}^1,x_{\mathrm{opt}}^2,......,x_{\mathrm{opt}}^{k_{\min }},l)$

$=\frac{\mathrm{rl}(k_{\min }{C}_b+C_l)+\mathrm{cl}(R_d+k_{\min }{R}_b)+(k_{\min }{C}_b+C_l)(k_{\min }{R}_b+R_d)}{k_{\min }+1}$

$+k_{\min }{T}_b+\frac{\frac{{\mathrm{rcl}}^2-k_{\min }r{(C_b-C_l)}^2}{c}-\frac{k_{\min }c{(R_b-R_d)}^2}{r}}{2(k_{\min }+1)}$

x _Opt ^jBeing the Manhattan distance (only comprising the horizontal and vertical lines section) of the relative gauze of buffer source end, also is the position of j buffer;

$x_{\mathrm{opt}}^j=(j-1)y_l+x_l,j\&Element;\{\mathrm{1,2},...,k_{\min }\}$

Wherein:

$\left\{\begin{array}{c}{x}_l=\frac{1}{k_{\min }+1}(l+\frac{k_{\min }(R_b-R_d)}{r}+\frac{(C_l-C_b)}{c})\\ y_l=\frac{1}{k_{\min }+1}(l-\frac{(R_b-R_d)}{r}+\frac{(C_l-C_b)}{c})\end{array}\right.$

(4.5) satisfy the two ends gauze number N of target time delay with COMPUTER CALCULATION _Old

(4.5.1). calculate the candidate location sets of each buffer:

(4.5.1.1). calculate the source end of buffer place gauze and the friendship DF of determined rectangular area of drain terminal and clear area _Ol

(4.5.1.2). calculate DF _OlWith the friendship of the independent area of feasible solutions of buffer, work as DF _OlThe lower left corner of interior certain position is positioned at the independent area of feasible solutions of buffer, and then this position is the candidate position of respective buffer;

(4.5.1.3). be selected in the candidate position of above-mentioned buffer that buffer candidate position is minimum does not place the position of the position of buffer as buffer with fashion;

(4.5.2). check each two ends gauze, add up required buffer and fail the line screens that all insert, be designated as N _Notsat

(4.6) computer is estimated Q with following formula, obtains target function value Cost;

Cost _Q＝Area+λ×TotalWireLength+ω×Rs ²+γ×N _sat；

Wherein:

$\mathrm{Area}=\underset{i\&Element;[1...n]}{\max \left\{x_i\right\}}\&times;\underset{i\&Element;[1...n]}{\max \left\{y_i\right\}}$

TotalWireLength (total line length) is each gauze estimation length sum;

λ is the weight of total line length, and ω is the weight of breadth length ratio, and γ is the weight that buffer inserts;

Rs＝|R-max(ratio，l/ratio)|；

Wherein establish the target that R is the chip breadth length ratio, ratio is the actual breadth length ratio of chip;

(5) the current layout Qnow of output;

(6) calculate the temperature of next annealed condition with following formula:

Tnow＝a*Tnow，

Wherein a is the annealing factor, and general value is 0.95;

If Current Temperatures greater than end temp Tnow＞Tend, then enters the solution procedure of next annealed condition;

If Current Temperatures is less than end temp Tnow＜Tend, then Shu Chu current layout is final layout.

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