CN1269025C - Method of applying instructions in three/four wire type nonvolatile memory - Google Patents
Method of applying instructions in three/four wire type nonvolatile memory Download PDFInfo
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- CN1269025C CN1269025C CN 03101862 CN03101862A CN1269025C CN 1269025 C CN1269025 C CN 1269025C CN 03101862 CN03101862 CN 03101862 CN 03101862 A CN03101862 A CN 03101862A CN 1269025 C CN1269025 C CN 1269025C
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Abstract
The present invention relates to a method and a structure for applying instructions on a three-wire type / four-wire type non-volatile storage. The structure is suitable for a host to store a controller and a non-volatile storage through a chip selection wire, a data transmission line and a clock line, and is especially suitable for the host and the controller to share data of the non-volatile storage. The method transmits control instructions and virtual bits closely to the controller after the control instructions, and determines whether the controlled target of the control instructions is the controller or the non-volatile storage according to the virtual bits.
Description
Technical field
The present invention relates to the instruction application process and the structure of a kind of three-wire type/four-wire type nonvolatile memory, refer in particular to a kind of method and structure of utilizing a virtual bit to decide the controlled target of steering order.
Background technology
Three-wire type and four-wire type nonvolatile memory read-write interface have come out for many years, are not difficult because its steering order is simple and the interface circuit is made, so use quite extensive in the electronics industry.The circuit structure of existing three-wire type nonvolatile memory is shown in Figure 1A, and the circuit structure of existing four-wire type nonvolatile memory has wherein comprised main frame and nonvolatile memory shown in Figure 1B.The action sequence of circuit as shown in Figure 2, main frame is by line of chip select (CS) activation nonvolatile memory, after data line (DI) was sent one group of steering order, then data line (DO) was sent the data-signal of one group of correspondence.
As mentioned above, because the design concept of the circuit structure of existing four-wire type nonvolatile memory is based on the structure of the corresponding single device of single main frame, so its line of chip select only can the activation single device, unless increase the hardware decoding scheme, otherwise if according to existing steering order, the uncontrollable multiple arrangement of single main frame.If increase the hardware decoding scheme, then not only expend hardware resource but also increase hardware cost.
Summary of the invention
The objective of the invention is to propose the instruction application process and the structure of a kind of three-wire type/four-wire type nonvolatile memory.This method is passed through line of chip select, data line and clock line access controller and nonvolatile memory by main frame.The method of access be utilize main frame to transmit one group of steering order to decide the target of operation be controller or nonvolatile memory, make main frame not need additionally to add under the situation of hardware resource, single main frame may command multiple arrangement, and main frame and each device can be shared the content of nonvolatile memory according to steering order.
To achieve these goals, the present invention proposes the instruction application process and the structure of a kind of three-wire type/four-wire type nonvolatile memory.The method of access is to utilize main frame to transmit one group of steering order, and is defined as virtual bit being right after this steering order after last, and deciding the target of control by the level of virtual bit is controller or nonvolatile memory.
In a preferred embodiment of the present invention, when virtual bit determined that the Action Target of steering order is controller, then controller cut out the reaction of nonvolatile memory for signal signal on data line and the clock line.
In another preferred embodiment of the present invention, when the Action Target of virtual bit decision steering order is nonvolatile memory, then controller is opened the reaction of nonvolatile memory for signal on data line and the clock line, and closing controller before this data transfer end for data line and clock line on the reaction of signal.
In sum, the present invention proposes the instruction application process and the structure of a kind of three-wire type/four-wire type nonvolatile memory.The method is to utilize a virtual bit that is right after after steering order to decide the controlled target of this steering order.Do not need additionally to add under the situation of hardware resource at main frame, this method can make single main frame respective operations multiple arrangement, thereby it is simultaneously compatible mutually with existing control method to make main frame and each device can share the content of nonvolatile memory according to steering order.
Can become apparent with other purpose, feature and advantage for making that the present invention is above-mentioned, further describe specific embodiments of the invention below in conjunction with accompanying drawing.
Description of drawings
Figure 1A is depicted as the circuit structure block diagram of existing three-wire type nonvolatile memory;
Figure 1B is depicted as the circuit structure block diagram of existing four-wire type nonvolatile memory;
Figure 2 shows that the prior art circuits sequential chart;
Figure 3 shows that the circuit diagram of a preferred embodiment of the present invention;
Figure 4 shows that the circuit timing diagram of a preferred embodiment of the present invention;
Figure 5 shows that the circuit timing diagram of a preferred embodiment in addition of the present invention;
Fig. 6 A is depicted as the circuit timing diagram of another preferred embodiment of the present invention;
Fig. 6 B is depicted as the circuit diagram of a preferred embodiment of the present invention;
Fig. 7 A is depicted as the circuit diagram of other preferred embodiment of the present invention;
Fig. 7 B is depicted as the circuit diagram of other preferred embodiment of the present invention;
Fig. 8 A is depicted as the circuit diagram of other preferred embodiment of the present invention;
Fig. 8 B is depicted as the circuit diagram of other preferred embodiment of the present invention;
Fig. 9 A is depicted as the circuit diagram of other preferred embodiment of the present invention; And
Fig. 9 B is depicted as the circuit diagram of other preferred embodiment of the present invention.
Wherein, description of reference numerals is as follows:
300,310,800: the structure of four-wire type control nonvolatile memory
302,312,602,702,712,802,812,902,912: main frame
304,314,604,704,714,804,814,904,914: nonvolatile memory
306,316,706,716,806,808,810,816,906,908,910,916: controller
318,718,812,818,912,918: with door
400,500,600: virtual bit
700,710,900: the structure of three-wire type control nonvolatile memory
Embodiment
Figure 3 shows that the circuit diagram of a preferred embodiment of the present invention.The structure 300 of this four-wire type control nonvolatile memory comprises main frame 302, controller 306 and nonvolatile memory 304.Main frame 302 couples controller 306, and controller 306 couples nonvolatile memory 304.
Below the explanation present embodiment is controlled the method for nonvolatile memory.Please in conjunction with reference Fig. 4, Fig. 4 is the circuit timing diagram of main frame 302 reading non-volatile storages 304.Main frame 302 is by line of chip select (CS) activation controller 306, controller 306 is by line of chip select (CS0) activation nonvolatile memory 304,3rd clock period of main frame 302 from the clock line (SK), send a string steering order (Ai～A0).If the virtual bit 400 that is right after at last A0 of this steering order is low levels, then controller 306 can not handled this steering order and keep high level signal and continue activation nonvolatile memory 304 by line of chip select (CS0).Then, nonvolatile memory 304 is handled these steering orders and is sent the data of this steering order corresponding address by data line DO.In other words, when these virtual bit 400 decision steering orders are this nonvolatile memory 304 of control, controller 306 can activation nonvolatile memories 304 for the reaction of signal on data line DI/DO and the clock line SK, and stop control 306 before this DTD for data line DI/DO and clock line SK on the reaction of transmission signals.
Below explanation please refer to Fig. 5.Sequential chart when Fig. 5 obtains data for main frame 302 slave controllers 306.When virtual bit 500 is a high level, and received steering order is under the situation of requirement controller 306 output datas, and then controller 306 is by data line DO output data; Because controller 306 makes line of chip select CS0 be in low level, do not handle this steering order so cause nonvolatile memory 304 to lose efficacy (disable).In other words, when the Action Target of virtual bit 500 decision steering orders was controller 306, controller 306 promptly cut out the signal of reaction this nonvolatile memory 304 is gone up to(for) data line DI/DO and clock line SK.
Further specify and please refer to Fig. 6 A.Sequential chart when Fig. 6 A is main frame 302 setting controllers 306 states, the principle of work of circuit is similar to Fig. 5, different is to be high level when virtual bit 600, and received steering order is requirement controller 306 input data conditions, (Dj～D0) is so that controller 306 can be set according to this control data by setting data of data line DI input for controller 306.
The do circuit diagram of a preferred embodiment of the present invention of Fig. 6 B.The structure 310 of this four-wire type control nonvolatile memory is approximate with the embodiment of Fig. 3, and different is to use with door 318 to be connected line of chip select CS and CS1, with activation nonvolatile memory 314.
Fig. 7 A is depicted as the circuit diagram of other preferred embodiment of the present invention.The constituent components and the principle of work of the structure 700 of this three-wire type control nonvolatile memory, approximate with Fig. 3 embodiment, repeat no more.Different is that data line DI and data line DO merge into a line, but the control timing of its nonvolatile memory 704 is then similar with the sequential chart of Fig. 4, Fig. 5 and Fig. 6.Main frame 702 utilizes the level of virtual bit to control controller 706 and nonvolatile memory 704 respectively.
Fig. 7 B figure is depicted as the circuit diagram of a preferred embodiment of the present invention.The structure 710 of this three-wire type control nonvolatile memory is approximate with Fig. 7 A embodiment, and different is to use with door 718 to be connected line of chip select CS and CS1, with activation nonvolatile memory 714.
Fig. 8 A is depicted as the circuit diagram of other preferred embodiment of the present invention.It is similar that each assembly function in this four-wire type control non-volatile memory architecture 800 and annexation and Fig. 3 execute example, different is present embodiment has n controller and one and 812.(CS1～CSn) is coupled to each controller, is coupled to nonvolatile memory 804 with the output terminal of door 812 by line of chip select CS0 by line of chip select with door 812.
Below the explanation present embodiment is controlled the method for nonvolatile memory, and the action sequence of its circuit and Fig. 3 embodiment are approximate, and different is that single main frame 802 must utilize steering order to control a plurality of controllers and nonvolatile memory 804.Please in conjunction with reference Fig. 5, if virtual bit 500 is high level, then these controllers can handle this steering order and output low level signal to the input end of door 812, make with the output terminal of door 812 and export a low level; Because line of chip select CS0 is a low level, so nonvolatile memory 804 is by decapacitation (disable).And when virtual bit 500 is a high level, and received steering order is when requiring these controller output datas, by data line DO output data.Please in conjunction with reference Fig. 6, its control principle and Fig. 5 are similar, and different is that these controllers are imported data according to the order of steering order by data line DI, and only has the controller of a correspondence can produce response.
Otherwise, please in conjunction with reference Fig. 4, if virtual bit is low level, then these controllers can not handle this steering order and keep high level signal to the input end of door 812, make with the output terminal of door 812 and export a high level; Because line of chip select CS0 is a high level, the data of (enable) and corresponding this steering order of output so nonvolatile memory 804 is enabled.Remaining circuit working principle and Fig. 3 embodiment are approximate, repeat no more.
Fig. 8 B is depicted as the circuit diagram of a preferred embodiment of the present invention.The structure 810 of this four-wire type control nonvolatile memory is approximate with the embodiment of Fig. 8 A, and different is uses and is connected line of chip select CS with door 818 and (CS1～CSn) is with activation nonvolatile memory 814.
Fig. 9 A is depicted as the circuit diagram of other preferred embodiment of the present invention.Each assembly function, annexation and principle of work in the structure 900 of this three-wire type control nonvolatile memory are all similar to Fig. 8 A embodiment, different is that data line DI and data line DO merge into a line, but the control principle of its nonvolatile memory 904 and Fig. 8 A embodiment are similar, no longer repeat specification.
Fig. 9 B is depicted as the circuit diagram of a preferred embodiment of the present invention.The structure 910 of this three-wire type control nonvolatile memory is approximate with the embodiment of Fig. 9 A, and different is uses and is connected line of chip select CS with door 918 and (CS1～CSn) is with activation nonvolatile memory 914.
It must be noted that the virtual bit of present embodiment and the level of each signal wire only are usefulness for example, and are not necessary restrictive condition of the present invention, those skilled in the art can be according to the required definition voluntarily of situation.
In sum, the invention provides the instruction application process and the structure of a kind of three-wire type/four-wire type nonvolatile memory.When one of design has the multifunction chip of nonvolatile memory, if utilization the present invention as the communications protocol between each structure and the main frame, then can save chip stitch (pin) number.The present invention is compatible mutually with existing three-wire type/four-wire type control method for nonvolatile memory, and the existing driver of host side only needs to revise by a small margin or newly-increased sub-program gets final product normal running.
Though the present invention with a preferred embodiment openly as above; yet it is not to be used to limit the present invention, any those skilled in the art, without departing from the spirit and scope of the present invention; can do some equivalences and change and change, so protection scope of the present invention is as the criterion with claims.
Claims (12)
1. the instruction application process of three-wire type/four-wire type nonvolatile memory, use when being applicable to by-main frame by line of chip select, data line and at least one controller of clock line access and three-wire type/four-wire type nonvolatile memory, it is characterized in that this method comprises:
A transmission-steering order and a virtual bit that is right after after this steering order arrive at least one controller; And
Determine this steering order to control this at least one controller or this nonvolatile memory according to this virtual bit.
2. the instruction application process of three-wire type as claimed in claim 1/four-wire type nonvolatile memory, it is characterized in that, when this virtual bit is high level, this steering order is used to control this at least one controller, and when this virtual bit was low level, this steering order then was to be used to control this nonvolatile memory.
3. the instruction application process of three-wire type as claimed in claim 1/four-wire type nonvolatile memory, it is characterized in that, when this virtual bit is low level, this steering order is used to control this at least one controller, and when this virtual bit was upgraded to high level, this steering order then was used to control this nonvolatile memory.
4. the instruction application process of three-wire type as claimed in claim 1/four-wire type nonvolatile memory, it is characterized in that, when determining that according to this virtual bit this steering order is controlled at least one controller, this at least one controller promptly cuts out the reaction of this nonvolatile memory for signal on data line and the clock line.
5. the instruction application process of three-wire type as claimed in claim 1/four-wire type nonvolatile memory, it is characterized in that, when determining that according to this virtual bit this steering order is controlled this nonvolatile memory, this at least one controller is promptly opened the reaction of this nonvolatile memory for signal on data line and the clock line, so that carry out data transmission between this nonvolatile memory and main frame, and before this data transfer finishes, close this controller for data line and clock line on the reaction of signal.
6. the instruction application process of three-wire type as claimed in claim 1/four-wire type nonvolatile memory, it is characterized in that, when this steering order is used to control this at least one controller, this at least one controller should after this virtual bit, add a setting data, so that can be controlled according to this setting data.
7. the instruction application process of three-wire type as claimed in claim 1/four-wire type nonvolatile memory, it is characterized in that, when this steering order was used for from this at least one controller reading of data, this at least one controller promptly returned required data after receiving this virtual bit.
8. the application of instruction circuit of three-wire type/four-wire type nonvolatile memory is characterized in that, comprising:
One main frame is conductively coupled to one first line of chip select, a data line and a clock line;
One three-wire type/four-wire type nonvolatile memory is conductively coupled to this data line and this clock line; And
At least one controller is conductively coupled to this first line of chip select, this data line and this clock line, and is conductively coupled to this three-wire type/four-wire type nonvolatile memory by one second line of chip select;
Wherein, this at least one controller is according to being received that main frame sends and being right after a virtual bit after a steering order by this data line, the controlled target of judging this main frame is this three-wire type/four-wire type nonvolatile memory or this at least one controller.
9. the application of instruction circuit of three-wire type as claimed in claim 8/four-wire type nonvolatile memory, it is characterized in that, the controlled target that this at least one controller is judged this main frame according to this virtual bit should be with this second line of chip select activation during for this three-wire type/four-wire type nonvolatile memory.
10. the application of instruction circuit of three-wire type as claimed in claim 8/four-wire type nonvolatile memory, it is characterized in that, when this at least one controller judges that according to this virtual bit the controlled target of this main frame is this at least one controller itself, should be with this second line of chip select decapacitation.
11. the application of instruction circuit of three-wire type as claimed in claim 8/four-wire type nonvolatile memory, it is characterized in that, when the number of this controller is plural number, all be conductively coupled to this main frame with corresponding this first line of chip select of each this controller, and have corresponding this second line of chip select to be conductively coupled to this three-wire type/four-wire type nonvolatile memory.
12. the application of instruction circuit of three-wire type as claimed in claim 11/four-wire type nonvolatile memory, it is characterized in that, this second line of chip select is connected to one and door, should will export this three-wire type/four-wire type nonvolatile memory to calculated result again with door.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03101862 CN1269025C (en) | 2003-01-20 | 2003-01-20 | Method of applying instructions in three/four wire type nonvolatile memory |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 03101862 CN1269025C (en) | 2003-01-20 | 2003-01-20 | Method of applying instructions in three/four wire type nonvolatile memory |
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| Publication Number | Publication Date |
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| CN1519701A CN1519701A (en) | 2004-08-11 |
| CN1269025C true CN1269025C (en) | 2006-08-09 |
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| CN 03101862 Expired - Fee Related CN1269025C (en) | 2003-01-20 | 2003-01-20 | Method of applying instructions in three/four wire type nonvolatile memory |
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| US7460989B2 (en) * | 2004-10-14 | 2008-12-02 | International Business Machines Corporation | Method and apparatus for modeling multiple concurrently dispatched instruction streams in super scalar CPU with a sequential language |
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