CN1266842C - Method for sampling and transforming analog signal below lowest electric potential in a circuit - Google Patents

Abstract

The present invention discloses a method for converting simulating signal samples lower than the potential minimum in a circuit. The present invention is characterized in that the method of the present invention comprises the following steps that PMOSFET is adopted; a bias circuit is provided, and two electric levels are manufactured; the PMOSFET can respectively exist in a switching on state and a switching off state in a corresponding time period. The circuit comprises two PMOSFET pipes m1, m2, two switches SW1, SW2, two capacitors Cs, Ci, an operational amplifier A1 and a bias circuit U1 used for generating the gate voltage of the m1 and the m2 and sending clock signals, wherein for the realization of the SW1, only the PMOSFET can be adopted, and therefore, the occurrence of clamping can be prevented.

Description

Circuit to the analog signal sampling that is lower than potential minimum in the circuit

Technical field

The invention relates to a kind of sample circuit, especially a kind of circuit of in the CMOS analog integrated circuit, realizing the also low analog level signal sampling of potential minimum in than circuit.

Background technology

Generally speaking, for common CMOS technology, the used power supply of the chip that goes out with this explained hereafter is to being that (maximum level has 2.5V, 3V, 3.3V, 5V etc. according to technology unusual for 0V (minimum level), 5V, after this this explanation is representing maximum potential with 5V for convenience without exception).Be illustrated in figure 1 as known sample-hold circuit, it is made of jointly four switch SW 1, SW2, SW3, SW4 and two capacitor C s, Ci and an operational amplifier A 1.As a rule the current potential of REF is 2.5V, because during this time can obtain the signal amplitude of identical maximum on both direction up and down.Also show in order to the clock signal that drives this circuit as Fig. 1.

For this kind circuit, clock signal PH1 be " 1 " (high level, in the time of 5V), switch SW 1, SW3 closure, and switch SW 2, SW4 are opened.Be the equal of that Vin charges for capacitor C s by SW1 this moment, and Ci is then keeping the value of last time; And when clock signal PH2 is " 1 ", switch SW 2, SW4 closure, and switch SW 1, SW3 are opened.The electric charge that capacitor C s will remain on node n2 this moment has been passed to capacitor C i by SW4, forms the action of an integration.And this circuit is to be common mode electrical level with REF level (2.5V) for the requirement of signal.

And when system design for for simplicity the time, sometimes with the common-mode point of 0V as signal level, this moment, known sample-hold circuit just seemed powerless, can not work normally.Because in cmos circuit, switch can be realized with the P transistor npn npn (PMOSFET) and the N transistor npn npn (NMOSFET) of a pair of complementation, also can be realized separately by PMOSFET or NMOSFET.

When we will be to 0V being the signal at center when sampling, difficulty part be that the level signal below the 0V is sampled.Thereby at first consider to use PMOSFET, can find generally to be 0V (level of clock signal is to switch) between the sharp 5V of 0V by thereon gate voltage is minimum, when signal less than | during Vt|, switch is can conducting, says nothing of and has sampled.Then consider NMOSFET, find since among the NMOSFET existence meeting of PN junction signal less than-| clamper takes place during Vt|.

So, in order can to improve known circuits to being that the level signal at center is sampled and changed with 0V.What at first consider is for signals sampling, and by above explanation, NMOSFET can live the signal clamper, thereby be disabled owing to the influence of its substrate to the PN junction of signal one end.

Summary of the invention

Purpose of the present invention just provides a kind of circuit that the analog signal that is lower than potential minimum in the circuit is sampled.

The present invention is directed in the known technology can not be to the signal sampling that is lower than the circuit potential minimum and the improvement that proposes.

Sample circuit of the present invention comprises: two PMOSFET pipes m1, m2, and two switch SW 1, SW2 and two capacitor C s, Ci and operational amplifier A 1, wherein:

The source electrode of PMOSFET pipe m1 connects input signal, and drain electrode is connected with the source electrode of PMOSFET pipe m2, the grounded drain of PMOSFET pipe m2;

Capacitor C s is a sampling capacitance, the drain electrode of one termination m1, another termination one node n2;

Switch SW 1 is controlled by clock PH1, and one terminates to node n2, and the other end is received reference voltage;

Switch SW 2 is controlled by clock PH2, and one terminates to node n2, and the other end is received the negative input end of operational amplifier A 1;

The positive input termination reference voltage of operational amplifier A 1, integrating capacitor Ci in parallel between its negative input end and the output;

Described circuit also comprises a biasing circuit module U1, this biasing circuit module U1 comprises signal output part G1 and G2, wherein output G1 is connected with the grid of above-mentioned PMOSFET pipe m1, output G2 is connected with the grid of above-mentioned PMOSFET pipe m2, this biasing circuit module U1 is by above-mentioned clock signal PH1 and PH2 control, and the gate voltage of generation PMOSFET pipe m1 and PMOSFET pipe m2.

Be provided with when CK is " 1 ", because the current potential that switch SW 1 closure makes G order is 2V, this moment is for m1, it is where interior no matter signal is in (1～+ 1), PMOSFET can not conducting, Cs only is the value that has kept last, and when CK reduces to " 0 " by " 1 ", switch SW 1 is opened, and the current potential at electric capacity one end n1 place is reduced to 0V by 5V, because the voltage at electric capacity two ends can not suddenly change, the current potential that makes G order is reduced to-3V by 2V, and this moment, the G point did not have on the power supply that any path can be connected to circuit, and the current potential that G is ordered can maintain long period of time, that is to say can finish for the negative voltage in the certain limit (greater than-3+|Vt|) sampling.Wherein also can only adopt PMOSFET for the realization of SW1, thus the clamper of preventing.

Consider that at first PH1 is the also situation when " 0 " of " 0 ", PH2.PMOSFET among the biasing circuit U1 is in conducting state at this moment, and the voltage at G1, G2 place equals 2V, makes m1, m2 all turn-off, and same SW1, SW2 also turn-off, and Cs and Ci were keeping the level in a last moment respectively.

PH1 becomes " 1 " by " 0 " then, and PH2 keeps " 0 ".M3 among the PMOSFET among the biasing circuit U1 turn-offs at this moment, m4 is conducting still, makes that the voltage of G2 is constant still to equal 2V, and when an end n5 of capacitor C 3 becomes " 0 " (promptly being to reduce to 0V by 5V) by " 1 ", because the voltage at electric capacity two ends can not suddenly change, make that the voltage at G1 place has dropped to-3V.M1 conducting this moment, m2 turn-offs, and circuit is in sample phase.Signal is sampled on the Cs electric capacity.Electric charge on the Cs is [Cs* (Vin-REF)] at this moment, notices that the Vin of this moment is to be the signal at center with 0V.

PH1 becomes " 0 " by " 1 " then, and PH2 still keeps " 0 ".PMOSFET among the biasing circuit U1 is in conducting state at this moment, the voltage at G1, G2 place equals 2V, makes m1, m2 all turn-off, and same SW1, SW2 also turn-off, Cs and Ci were keeping the level in a last moment respectively, and the electric charge on the Cs is [Cs* (Vin-REF)].

PH2 becomes " 1 " by " 0 " then, and PH1 keeps " 0 ".M3 conducting among the PMOSFET among the biasing circuit U1 at this moment, m4 still turn-offs, makes that the voltage of G1 is constant still to equal 2V, and when an end n6 of capacitor C 4 becomes " 0 " (promptly being to reduce to 0V by 5V) by " 1 ", because the voltage at electric capacity two ends can not suddenly change, make that the voltage at G2 place has dropped to-3V.This moment, m1 turn-offed, the m2 conducting, and circuit is in the stage of transmitting electric charge and changing common mode electrical level.After n1 is pulled to 0V, because n2 still be REF (2.5V), the electric charge on the Cs also has [Cs* (REF)], and the electric charge that then has [Vin*Cs] has been sent on the negative plate of Ci, it is same because the quantity of electric charge at electric capacity two ends will equate that the positive plate of Ci has been accepted the electric charge of [Vin*Cs].Make

$\mathrm{Vo}\left(n\right)=\mathrm{Vo}(n-1)+\frac{\mathrm{Cs}}{\mathrm{Ci}}\·\mathrm{Vin}(n-1)$

Notice that Vo is is the signal at center with REF (2.5V), and Vin is to be the signal at center with 0V, obtains just the result that we want this moment.

Work as PH2 at last and become " 0 " by " 1 ", PH1 still keeps " 0 ".PMOSFET among the biasing circuit U1 is in conducting state at this moment, and the voltage at G1, G2 place equals 2V, makes m1, m2 all turn-off, and same SW1, SW2 also turn-off.Circuit is being waited for action next time.So move in circles and just finished sampling and conversion the analog level signal also low than potential minimum in the circuit.

We just can realize being lower than the signals sampling of 0V according to above circuit, but the processing of back circuit for convenience, also need common-mode point with signal to be transformed into REF (2.5V) by 0V and come up.Come below a complete sample conversion circuit is described.

Description of drawings

Fig. 1 is the circuit diagram of known sample-hold circuit.

Fig. 2 is the implementation method schematic diagram of the sample circuit after improving.

The schematic diagram of the sample conversion circuit that Fig. 3 will illustrate for the present invention.

Embodiment

As Fig. 2, shown in Figure 3, promptly be an improved sample circuit, it can be realized for the signals sampling function that is lower than 0V.

Sample circuit of the present invention comprises: two PMOSFET pipes m1, m2, and two switch SW 1, SW2 and two capacitor C s, Ci and operational amplifier A 1, wherein:

The source electrode of PMOSFET pipe m1 connects input signal, and drain electrode is connected with the source electrode of PMOSFET pipe m2, the grounded drain of PMOSFET pipe m2;

Capacitor C s is a sampling capacitance, the drain electrode of one termination m1, another termination one node n2;

Switch SW 1 is controlled by clock PH1, and one terminates to node n2, and the other end is received reference voltage;

Switch SW 2 is controlled by clock PH2, and one terminates to node n2, and the other end is received the negative input end of operational amplifier A 1;

The positive input termination reference voltage of operational amplifier A 1, integrating capacitor Ci in parallel between its negative input end and the output;

Described sample circuit also comprises a biasing circuit module U1, this biasing circuit module U1 comprises signal output part G1 and G2, wherein output G1 is connected with the grid of above-mentioned PMOSFET pipe m1, output G2 is connected with the grid of above-mentioned PMOSFET pipe m2, this biasing circuit module U1 is by above-mentioned clock signal PH1 and PH2 control, and the gate voltage of generation PMOSFET pipe m1 and PMOSFET pipe m2.

The inside of biasing circuit module U1 comprises two identical level shift modules, and one of them level shift module comprises:

A phase inverter, its input meets above-mentioned clock signal PH1, and output connects another phase inverter, and the output of another phase inverter meets node n5;

A PMOSFET pipe m3, its source electrode is received bias voltage V1, and output G1 is received in drain electrode, and grid is received between above-mentioned two phase inverters;

An electric capacity is connected between node n5 and the output G1.

The structure and the said structure of another level shift module are identical.

When CK is " 1 ", because the current potential that switch SW 1 closure makes G order is 2V, this moment is for m1, it is where interior no matter signal is in (1～+ 1), PMOSFET can not conducting, Cs only is the value that has kept last, and when CK reduces to " 0 " by " 1 ", switch SW 1 is opened, and the current potential at electric capacity one end n1 place is reduced to 0V by 5V, because the voltage at electric capacity two ends can not suddenly change, the current potential that makes G order is reduced to-3V by 2V, and this moment, the G point did not have on the power supply that any path can be connected to circuit, and the current potential that G is ordered can maintain long period of time, that is to say can finish for the negative voltage in the certain limit (greater than-3+|Vt|) sampling.Wherein also can only adopt PMOSFET for the realization of SW1, purpose also is for fear of clamper takes place.

We just can realize being lower than the signals sampling of 0V according to above circuit, but the processing of back circuit for convenience, also need common-mode point with signal to be transformed into REF (2.5V) by 0V and come up.Come below a complete sample conversion circuit is described.

Consider that at first PH1 is the also situation when " 0 " of " 0 ", PH2.PMOSFET among the biasing circuit U1 is in conducting state at this moment, and the voltage at G1, G2 place equals 2V, makes m1, m2 all turn-off, and same SW1, SW2 also turn-off, and Cs and Ci were keeping the level in a last moment respectively.

Then PH1 becomes " 1 " by " 0 ", and PH2 keeps " 0 ".M3 among the PMOSFET among the biasing circuit U1 turn-offs at this moment, m4 is conducting still, makes that the voltage of G2 is constant still to equal 2V, and when an end n5 of capacitor C 3 becomes " 0 " (promptly being to reduce to 0V by 5V) by " 1 ", because the voltage at electric capacity two ends can not suddenly change, make that the voltage at G1 place has dropped to-3V.M1 conducting this moment, m2 turn-offs, and circuit is in sample phase.Signal is sampled on the Cs electric capacity.Electric charge on the Cs is [Cs* (Vin-REF)] at this moment, notices that the Vin of this moment is to be the signal at center with 0V.

Then PH1 is by "] " become " 0 ", PH2 still keeps " 0 ".PMOSFET among the biasing circuit U1 is in conducting state at this moment, the voltage at G1, G2 place equals 2V, makes m1, m2 all turn-off, and same SW1, SW2 also turn-off, Cs and Ci were keeping the level in a last moment respectively, and the electric charge on the Cs is [Cs* (Vin-REF)].

Then PH2 becomes " 1 " by " 0 " again, and PH1 keeps " 0 ".M3 conducting among the PMOSFET among the biasing circuit U1 at this moment, m4 still turn-offs, makes that the voltage of G1 is constant still to equal 2V, and when an end n6 of capacitor C 4 becomes " 0 " (promptly being to reduce to 0V by 5V) by " 1 ", because the voltage at electric capacity two ends can not suddenly change, make that the voltage at G2 place has dropped to-3V.This moment, m1 turn-offed, the m2 conducting, and circuit is in the stage of transmitting electric charge and changing common mode electrical level.After n1 is pulled to 0V, because n2 still be REF (2.5V), the electric charge on the Cs also has [Cs* (REF)], and the electric charge that then has [Vin*Cs] has been sent on the negative plate of Ci, it is same because the quantity of electric charge at electric capacity two ends will equate that the positive plate of Ci has been accepted the electric charge of [Vin*Cs].Make

$\mathrm{Vo}\left(n\right)=\mathrm{Vo}(n-1)+\frac{\mathrm{Cs}}{\mathrm{Ci}}\·\mathrm{Vin}(n-1)$

Notice that Vo is is the signal at center with REF (2.5V), and Vin is to be the signal at center with 0V, obtains just the result that we want this moment.

Work as PH2 at last and become " 0 " by " 1 ", PH1 still keeps " 0 ".PMOSFET among the biasing circuit U1 is in conducting state at this moment, and the voltage at G1, G2 place equals 2V, makes m1, m2 all turn-off, and same SW1, SW2 also turn-off.Circuit is being waited for action next time.So move in circles and just finished sampling and conversion the analog level signal also low than potential minimum in the circuit.

In sum, the present invention's purpose, realize that thought discloses in detail, illustrated that the present invention to the sampling of the also low analog level signal of potential minimum in than circuit and the specific implementation on the conversion method, has use value, and for not seeing on the market at present.

The above is only for one of the present invention example, when not limiting the scope that the present invention implements.The i.e. variation of being done according to the present patent application claim scope generally and modification etc. (for example only change voltage 2V and be other values 1.9V etc., and slightly modified clock signal phase etc.) all should still belong to right of the present invention and require the scope that contains.

Claims (2)

1, the circuit that the analog signal that is lower than potential minimum in the circuit is sampled, it comprises two PMOSFET pipes m1, m2, two switch SW 1, SW2 and two capacitor C s, Ci and operational amplifier A 1, wherein:

The source electrode of PMOSFET pipe m1 connects input signal, and drain electrode is connected with the source electrode of PMOSFET pipe m2, the grounded drain of PMOSFET pipe m2;

Capacitor C s is a sampling capacitance, the drain electrode of one termination m1, another termination one node n2;

Switch SW 1 is controlled by clock PH1, and one terminates to node n2, and the other end is received reference voltage;

Switch SW 2 is controlled by clock PH2, and one terminates to node n2, and the other end is received the negative input end of operational amplifier A 1;

The positive input termination reference voltage of operational amplifier A 1, integrating capacitor Ci in parallel between its negative input end and the output;

It is characterized in that: described circuit also comprises a biasing circuit module U1, this biasing circuit module U1 comprises signal output part G1 and G2, wherein output G1 is connected with the grid of above-mentioned PMOSFET pipe m1, output G2 is connected with the grid of above-mentioned PMOSFET pipe m2, this biasing circuit module U1 is by above-mentioned clock signal PH1 and PH2 control, and produce the gate voltage that PMOSFET manages m1 and PMOSFET pipe m2, make PMOSFET be in the turn-on and turn-off two states respectively in the corresponding time period.

2, the circuit that the analog signal that is lower than potential minimum in the circuit is sampled according to claim 1, it is characterized in that: the inside of described biasing circuit module U1 comprises two identical level shift modules, and this level shift module comprises:

A phase inverter, its input meets above-mentioned clock signal PH1, and output connects another phase inverter, and the output of another phase inverter meets node n5;

A PMOSFET pipe m3, its source electrode is received bias voltage V1, and output G1 is received in drain electrode, and grid is received between above-mentioned two phase inverters;

An electric capacity is connected between node n5 and the output G1.

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