CN1248470C

CN1248470C - Rolay interface device based on synchronous digital transmission system

Info

Publication number: CN1248470C
Application number: CN 01126389
Authority: CN
Inventors: 刘友义; 熊杰; 杜广
Original assignee: ZTE Corp
Current assignee: ZTE Corp
Priority date: 2001-07-28
Filing date: 2001-07-28
Publication date: 2006-03-29
Anticipated expiration: 2021-07-28
Also published as: CN1400790A

Abstract

The present invention relates to a relay interface device based on a synchronous digital transmission system, particularly to an E/M relay interface. The present invention comprises a core control circuit, a clock synchronous circuit, a synchronous access processing circuit, a time-slot crossover circuit, an audio interface circuit, a PCM coding/decoding and time-slot distribution circuit, a sending circuit for M signaling, and a receiving circuit for E signaling. The present invention can cause an original E/M analog relay interface device to be used in a synchronous digital transmission system to save the initial improvement expenses of user communication networks and to enhance the quality of voice and the reliability of signaling communication.

Description

A kind of trunk interface device based on synchronous digital transmission system

Technical field

The present invention relates to the E/M trunk interface of SDH (Synchronous Digital Hierarchy) (SDH), refer more particularly to the interface of stored-program control exchange E/M relaying in the private network and E/M carrier-current relaying.

Background technology

The E/M interface of switch is a kind of analog interface, is mainly used between the switch to interconnect as interoffice, has obtained using widely at the crossbar switch communication times.Because the E/M trunk interface compares with digital relay interface, particularly when remote the transmission, the speech delivery quality is relatively poor, and the transmitting-receiving ratio of signaling is easier to be interfered, thereby seeks a kind of device that can prolong E/M relaying transmitting range and seem necessary.Along with promoting day by day of SDH synchronous transmission net and popularizing of SPC digital switch, the optic electric interface that the analog interface between the switch---solid line/carrier-current relaying is digitized gradually replaces, and the E/M relaying is no exception.But in private wore networks such as electric power, railway, still there is a large amount of E/M trunkings continuing use at present.These private wore networks are when carrying out digital improvement, in order to prolong the useful life of these equipment, reduce first investment for trnasforming urban land expense, proposed the requirement that original E/M trunk interface equipment continuation is used in synchronous digital transmission system, but SDH synchronous digital transmission network system does not all provide this class interface at present.

Summary of the invention

Purpose of the present invention has the shortcoming that the E/M interface equipment can not insert now in order to overcome just when communication network upgrades to Digital Transmission, and solves the problem that the remote speech transmissions that exists in the prior art is of poor quality and signaling is disturbed easily.

E/M relay hardware components of the present invention comprises: core control circuit (MPU), and clock synchronization circuit inserts treatment circuit synchronously, the time slot transposition circuit, audio interface circuit, PCM encoding and decoding (CODEC) and time slot distributor circuit, the transtation mission circuit of M signaling and E signal receiving circuit; Wherein:

Core control circuit (MPU): control whole device every other circuit module running status and this device reported the webmaster maintenance terminal for information about, be used for simultaneously and the communication of webmaster maintenance terminal, explain and carry out the webmaster order;

Clock synchronization circuit: this circuit extracts the 2.048MHz clock by synchronous access treatment circuit from standard E1 interface, after frequency multiplication phase-locked loop smoothing processing and frequency division processing, produce multiple time slot transposition circuit (4) and PCM encoding and decoding and required synchronised clock and the header signal of time slot distributor circuit (6), and time slot transposition circuit and PCM encoding and decoding and time slot distributor circuit are sent into wherein from each required synchronised clock and header signal;

Insert treatment circuit synchronously: the uplink synchronous code stream from the time slot transposition circuit is carried out tap handle, divide and be inserted in the signal code stream of 2.048Mbits/S, through the insertion processing and the interface level conversion of framing processing, E signaling, promptly become the E1 output interface code stream of standard again; From the E1 interface code stream of standard, extract the line clock of 2.048MHz and the signal code stream of 2.048Mbits/S.Wherein, the line clock of 2.048MHz sends to clock synchronization circuit; 2.048Mbits/S the synchronizing signal code stream after going the frame structure circuit to remove frame structure, extract the M signaling by MPU (core control circuit); And the synchronizing signal code stream that will remove frame structure handles through multiple connection again, is transformed into the down-going synchronous data code flow of system, delivers to the time slot transposition circuit and exchanges processing;

The time slot transposition circuit: this circuit from the time gas exchange of PCM coding-decoding circuit in the uplink synchronous code stream of output E1 interface correspondence; Simultaneously the down-going synchronous code stream time gas exchange from input E1 interface correspondence is arrived the PCM coding-decoding circuit.This partial circuit realizes that other digital crossover of 64Kbits/S level handles, be convenient to the flexible allocation time slot and and other professional sharing E 1 interface band width resources;

PCM encoding and decoding and time slot distributor circuit: this circuit carries out encoding and decoding to the audio interface signals of audio interface circuit and the simulation of time slot transposition circuit to be handled, pcm encoder to conversion under the control of MPU carries out time slot configuration, is inserted in the uplink synchronous code stream of system; And from the down-going synchronous code stream of system, extract the time slot of appointment, and carry out encoding and decoding and handle, convert audio signal to;

Audio interface circuit: deliver to PCM encoding and decoding and time slot distributor circuit after audio input signal isolated coupling with impedance; And will carry out the amplification of impedance matching, isolation and signal from the simulated audio signal of PCM coding-decoding circuit, output to port;

E signal receiving circuit, M signaling transtation mission circuit: MPU be according to the M signaling of extracting from synchronous access treatment circuit, realizes transmission to the M signaling by the M wiretap in the control M signal receiving circuit; And pass through the reception condition of the loop current judgement local terminal E line signaling of detection E signaling transtation mission circuit,,, the E signaling is inserted into the SDH transfer system by synchronous access treatment circuit then the E signaling that receives.

Signaling receiving and transmission indicating circuit: in order to make that the transmitting-receiving situation to the E/M signaling comes into plain view in the maintenance process, can increase indicating circuit, indicate receiving and send signaling respectively with LED.

Adopt the device of the present invention can be, thereby saved the first improvement expenses of telex network network, and improved the quality of speech and the reliability of signaling contact so that original E/M Analog Trunk Interface equipment continues to use in the synchronous digital hierarchy transport system.

Description of drawings

Below in conjunction with accompanying drawing technical scheme of the present invention is done further detailed description:

Fig. 1 is the theory diagram of this device.

Fig. 2 is the network management configuration flow chart of this device.

Fig. 3 is the E/M signaling process flow chart of this device.

Embodiment

The theory diagram of apparatus of the present invention comprises as shown in Figure 1:

Core control circuit 1: with the MC68360 Communication processor is Master Control Center, by ethernet interface circuit and the communication of webmaster computer; With the executor of 8031 series monolithic systems, be responsible for inner each module of this device is carried out concrete control as specific tasks;

Clock synchronization circuit 2: adopt the T7688 interface circuit from standard E1 interface, to extract the 2.048MHz clock, through producing the initial clock of 32.768MHz after frequency multiplication, the phase-locked loop smoothing processing, handle the clock that the back generates 16.384MHz and 8.192MHz through frequency division again, and the header signal of 122nS and 61nS width.The header signal of described 16.384MHz clock and 61nS width is delivered in the time slot transposition circuit 4, and the header signal of 8.192MHz clock and 122nS width is delivered in PCM encoding and decoding and the time slot distributor circuit 6;

Insert treatment circuit 3 synchronously: utilize the FPGA designing technique, system 8.192Mbits/S speed uplink synchronous code stream from time slot transposition circuit 4 is carried out serial/parallel conversion, be written in the block RAM, read with the speed of 256KHz again, through parallel/serial conversion, produce the data of 2.048Mbits/S speed; 2.048Mbits/S the data of speed are inserted and interface conversion through framing, signaling, promptly become the E1 interface of standard; For downstream signal processing aspect, then pass through the processing of pulse transformer and T7688 chip, extract the line clock of 2.048MHz and the data of 2.048Mbits/S speed from the E1 interface code stream of standard, the data code flow of 2.048Mbits/S speed extracts the M signaling by MPU after going the frame structure circuit to remove frame structure; And the synchronizing signal code stream that will remove frame structure handles through multiple connection again, is transformed into the 8.192Mbits/S speed down-going synchronous data code flow of system, delivers in the time slot transposition circuit 4;

Time slot transposition circuit 4: utilize the switching network of MT90820, realize 2K*2K other time slot cross processing of 64Kbit/S level as this device;

Audio interface circuit 5: adopt audio frequency transformer and operational amplifier technology, realize the isolation of input, output audio signal,, realize that impedance matching and signal amplify in conjunction with the programmable parameter setting of PCM encoding and decoding (CODEC) and time slot distributor circuit 6;

PCM encoding and decoding (CODEC) and time slot distributor circuit 6: the AM79Q021 chip that adopts AMD is as the CODEC circuit core, both can realize codec functions, can realize the time slot allocation function again, can also the gain and the part impedance parameter of signal be provided with;

M signaling transtation mission circuit 72, E signal receiving circuit 71: by the control to the internal register of AM79Q021, the adhesive of M line has also just been controlled in the adhesive that comes control relay.By photoelectrical coupler, realize the detection of loop current, judge the signaling reception condition of E line;

Signaling receiving and transmission indicating circuit 8: utilize the unnecessary contact of relay, control sends signaling LED; Utilize circulation to detect logic, add drive circuit, control receives signaling LED.Every passage E/M interface uses 2 LED, is respectively to send and receive indication.

The software processing part of this device is described below:

Network management data is handled: comprise reporting and alarming information report of this device hardware configuration information.According to the requirement of webmaster, analog interface level, pulse duration, time slot allocation are provided with, this device is carried out warm reset, also to handle the sending and receiving of e and m signalling.

The sending and receiving of signaling are handled: because this device is a pure relaying, e and m signalling is done transparent transmission, do not add any explanation.The transmitting-receiving activity of all signalings all originates from the reception of E signaling, when the E signaling receives, MPU passes through to insert synchronously treatment circuit to the E signaling that receives, be sent to the E/M relay of opposite end, and reveal this signal again at the M of opposite end interface, not delaying time in the centre, thereby finishes the relay transmission of a signaling.When MPU when synchronous access treatment circuit is received the M signalling coding, just realize the transmission of M signaling by control to the M wiretap.For the difference of the parameter that adapts to different E/M trunk interfaces, by webmaster and software control, can be arranged on 100mS to the scope of 200mS in taking the width that confirms pulse, every 10mS is an adjustment step-length.Pulse dialing signal also is transparent transmission, by the E/M interface circuit of this device, can carry out transparent transmission to the standard compliant pulse dialing signal of index performance.

Four line audio interface gains software setting: can be by the webmaster maintenance terminal by MPU to the configuration that gains separately of each road four line analog interface level, to realize the interface level requirement of user's proposition.In conjunction with audio interface circuit, level is a step pitch with integer dB, can realize-14dBr---the transmission interface level of+1dBr, and-11dBr---any configuration of the incoming level of+4dBr.

The concrete course of work of apparatus of the present invention is as follows:

At first carry out network management configuration and handle, as shown in Figure 2: the order that core control circuit 1 is sent according to the webmaster maintenance terminal, carry out following processing:

1, when powering on or reset, the hardware components of this device is detected;

If 2 self checks successes, the then parameter command setting of sending according to the webmaster maintenance terminal determines to take in the E/M signaling process pulse duration of confirmation signaling; If fail self-test, then MPU gives the webmaster maintenance terminal fail self-test alarm report, and sends the alarm indication;

3, according to the network management configuration requirement, the analog interface level and the impedance parameter of 1 pair of PCM coding-decoding circuit of core control circuit are provided with, and withdraw from configuration process then.

After this device executes configuration process, as shown in Figure 3 by MPU control E/M signaling receiving and transmission process:

1, detects the state of E signal receiving circuit 71;

2,,, and the E signalling coding is sent to the E1 output interface by synchronous access treatment circuit the signalling coding of corresponding signaling conversion cost device when detecting at the E signal receiving circuit when showing the spare time, take or taking confirmation signaling; Otherwise carried out for the 5th step;

If 3 the 2nd the step in detected be occupied signaling, then carry out next step, otherwise carry out the 5th the step;

If 4, signal receiving circuit detects pulse dialing signal,, and send to the E1 output interface by synchronous access treatment circuit the number code signal of this conversion of signals cost device; Otherwise carried out for the 5th step;

If 5 detect the signalling coding or the number code signal of this device that synchronous access treatment circuit sends here, then carry out next step, otherwise carried out for the 7th step;

6, according to signalling coding or number code signal control M interface circuit, on the M line, produce the signal that conformance with standard requires;

7, carry out from the circulation of the 1st step.

Claims

1, a kind of trunk interface device based on synchronous digital transmission system, comprise: core control circuit (1), clock synchronization circuit (2), insert treatment circuit (3) synchronously, time slot transposition circuit (4), audio interface circuit (5), PCM encoding and decoding and time slot distributor circuit (6), M signaling transtation mission circuit (72) and E signal receiving circuit (71); It is characterized in that:

The running status of the every other circuit module of the whole device of described core control circuit (1) control also reports the webmaster maintenance terminal to this device for information about, is used for simultaneously and the communication of webmaster maintenance terminal, explains and the order of execution webmaster;

Described clock synchronization circuit (2) extracts described synchronous access treatment circuit (3) from standard E1 interface clock, produce multiple time slot transposition circuit (4) and PCM encoding and decoding and required synchronised clock and the header signal of time slot distributor circuit (6) after treatment, respectively time slot transposition circuit (4) and PCM encoding and decoding and time slot distributor circuit (6) are sent into wherein from each required synchronised clock and header signal;

Described synchronous access treatment circuit (3) is to promptly becoming the E1 output interface code stream of standard after handling from the uplink synchronous code stream of time slot transposition circuit (4); And from the E1 interface code stream of standard, extract the signal code stream of 2.048Mbits/S, extract the M signaling by core control circuit after removing frame structure, and the synchronizing signal code stream that will remove frame structure is handled through multiple connection again, be transformed into the down-going synchronous data code flow of system, deliver to time slot transposition circuit (4) and exchange processing;

Described time slot transposition circuit (4) from the time gas exchange of PCM encoding and decoding and time slot distributor circuit (6) in the uplink synchronous code stream of output E1 interface correspondence, simultaneously from the down-going synchronous code stream time gas exchange of input E1 interface correspondence to PCM encoding and decoding and time slot distributor circuit (6);

Described PCM encoding and decoding and time slot distributor circuit (6) carry out encoding and decoding to the audio interface signals of audio interface circuit and the simulation of time slot transposition circuit to be handled, pcm encoder to conversion under the control of core control circuit carries out time slot configuration, be inserted in the uplink synchronous code stream of system, and the time slot of extraction appointment from the down-going synchronous code stream of system, carry out encoding and decoding and handle, convert audio signal to;

Described audio interface circuit (5) is delivered to PCM encoding and decoding and time slot distributor circuit (6) after audio input signal is isolated coupling with impedance, and will be from the simulated audio signal of PCM encoding and decoding and time slot distributor circuit (6), carry out the amplification of impedance matching, isolation and signal, output to port;

Core control circuit (1) is according to the M signaling of extracting from synchronous access treatment circuit (3), realize transmission by the M wiretap in control M signaling transtation mission circuit (72) to the M signaling, judge the reception condition of local terminal E signaling by the loop current that detects E signal receiving circuit (71), then the E signaling that receives is inserted into the SDH transfer system by access treatment circuit (3) synchronously.

2, a kind of trunk interface device based on synchronous digital transmission system according to claim 1 is characterized in that: comprise that also signaling receiving and transmission indicating circuit (8) indicates E signaling (71) and M signaling (72).