CN1237592C - 半导体器件中晶体管的形成方法 - Google Patents

半导体器件中晶体管的形成方法 Download PDF

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CN1237592C
CN1237592C CNB02160892XA CN02160892A CN1237592C CN 1237592 C CN1237592 C CN 1237592C CN B02160892X A CNB02160892X A CN B02160892XA CN 02160892 A CN02160892 A CN 02160892A CN 1237592 C CN1237592 C CN 1237592C
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孙容宣
柳昌雨
李政烨
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SK Hynix Inc
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Abstract

一种用于形成半导体器件中的晶体管的方法，包括步骤：形成具有第一和第二导电类型的通道层，进行高温热处理以形成稳定通道层，并通过生长未掺杂硅外延层形成一具有超陡逆分布δ-掺杂的外延通道，利用氢处理已获得的结构的整个表面，通过在稳定通道层上生长未掺杂硅外延层形成一外延通道结构，在外延通道结构上形成栅极绝缘膜和栅极电极，再氧化该栅极绝缘膜以修复该栅极绝缘膜的损伤部分；以及形成源/漏区并进行一低温热处理。

Description

半导体器件中晶体管的形成方法
技术领域
本发明公开了一种形成半导体器件中的晶体管的方法以及，特别是，公开了一种用于形成金属-氧化物-半导体场效应晶体管(MOSFET)或金属-绝缘体-半导体场效应晶体管(MISFET)的改进方法，其含有一具有通道长度小于100nm的可应用于超大规模集成(ULSI)半导体器件的超浅超陡逆分布(ultra-shallow super-steep-retrograde)外延通道。
背景技术
当电场被施加于源/漏区且电压施加在栅极上时，MOSFET或MISFET半导体器件中栅极电极和栅极绝缘膜下的表面区域被作为电流通道。这个区域被称为通道。
MOSFET或MISFET半导体器件的特性由该通道区域的杂质浓度所决定。特别地，诸如晶体管的阈值电压和漏电流的器件的特性依赖于该杂质浓度，因此该通道区域必须被精确地掺杂。
惯用的通道掺杂方法包括阱离子注入、通道离子注入、阈值电压离子注入，以及其他一些相关技术。
根据前述的方法，可形成沿深度方向具有常数通道区域浓度的单分布通道(flat channel)，具有特定通道深度的掩埋通道(buried channel)，和沿深度方向具有递增通道浓度的逆分布通道(retrograde channel)。
用于高性能微处理器的具有一小于0.2μm的通道长度的通道结构为按使用In，As和Sb的重离子注入而形成的逆分布通道。此处，表面杂质浓度Cs很低，为的是改善表面的迁移率。这样就有可能制造一种具有良好的电流驱动特性的高性能MOSFET。
由于通道长度缩小，通道深度Wd必须减少。相应地，具有小于50nm通道深度的逆分布通道却无法仅仅通过离子注入来形成。
外延通道已被用以尝试解决上述的问题。然而，由于在外沿通道的形成和接下来的热处理的过程中，通道中的杂质的损失和扩散不容易被控制，惯用的外延通道晶体管无法提供一个完善的Ion/Ioff特性。
最理想的通道掺杂方法是实现δ-掺杂外延通道。然而，无论是采用掺杂的外延层和未掺杂的外延层，由于后工序中的杂质扩散，具有通道深度小于30nm的δ-掺杂外延通道的实施例还未被报道有可能被实现。
一种以超低能量离子注入来掺杂通道，然后立刻在其上进行激光热处理以防止δ-掺杂层中的扩散的方法已经被尝试，“用于制造70nm nFET先于外延通道生长的激光热退火SSR阱(LASPE)”，IEDM 2000，Lee Jungho，Lee Jungyeop等人。在选择性外延生长(SEG)期间以激光热处理控制杂质的损失与扩散已被报道。
然而，控制外延层的杂质的损失与扩散的激光热处理在该激光功率下产生了硅衬底上的局部熔化，导致了衬底表面的粗糙度的加剧和晶体缺陷的产生，并无法应用于可行的半导体器件生产方法中。
发明内容
据此，公布一种通过在热处理中控制杂质的损失和在SEG中控制杂质扩散以提供较高的半导体器件集成密度的半导体器件中的晶体管的形成方法。
为了实现前述的本发明的目的，一种用于形成半导体器件中的晶体管的方法被公开，其步骤包括：(a)利用一器件绝缘膜图案在半导体衬底上定义一第一和一第二区域；(b)利用第一曝光掩模，在该第一区域内离子注入第一导电类型的杂质以形成一第一通道层；(c)利用第二曝光掩模，在该第二区域内离子注入第二导电类型的杂质以形成一第二通道层；(d)进行高温热处理以将该第一和第二通道层转变为第一和第二稳定通道层；(e)在步骤(d)获得的结构上进行氢处理工序；(f)在该第一和第二稳定通道层上生长未掺杂硅外延层，由此产生具有超陡逆分布结构的一第一和一第二δ-掺杂外延通道；(g)在该第一和第二δ-掺杂外延通道上形成一栅极绝缘膜和一栅极电极；(h)再氧化(re-oxidizing)该栅极绝缘膜以修复该栅极绝缘膜的被损伤的部分；以及(i)形成一源/漏区并进行低温热处理。
向该第一区域离子注入的工艺按使用As离子且离子注入能量范围为3至30KeV进行，或使用P离子且离子注入能量范围为1至15KeV进行；该第一通道层被形成为在该半导体衬底表面下的深度范围为10至50nm；向该第二区域离子注入的工艺按使用B离子且离子注入能量范围为100eV至1.5KeV进行；该第二通道层被形成为在该半导体衬底表面下的深度范围为10至50nm；该高温热处理为温度范围为900至1000℃的快速热处理；该进行高温热处理的步骤为一在温度范围为1000至1100℃下进行的尖峰快速热处理(spike rapid thermal process)；该未掺杂硅外延层具有厚度范围为5至30nm；该形成一栅极绝缘膜的步骤为在蒸汽环境中温度范围为650至750℃下生长一低温热氧化膜；形成一栅极绝缘膜的步骤包括形成一低温热氧化膜并利用等离子处理氮化该低温热氧化膜以形成一低温氧化氮化膜；该栅极绝缘层为一低温高介电常数膜；形成一栅极绝缘膜的步骤包括在温度范围为300至600℃下沉积一低温高介电常数膜，并且在温度范围为400至700℃的炉内进行一热退火工艺；形成一栅极绝缘膜的步骤包括在温度范围为300至650℃下沉积一低温高介电常数膜，并且在温度范围为600至800℃下进行一快速热退火工艺；形成一栅极绝缘膜的步骤包括在蒸汽环境中温度范围为650至700℃下生长一低温热氧化膜；在温度范围为300至650℃下在该低温热氧化膜上沉积一高介电常数材料；以及在温度范围为400至700℃的炉内进行一热退火工艺；形成一栅极绝缘膜的步骤包括在蒸汽环境中温度范围为650至750℃下生长一低温热氧化膜；在温度范围为300至650℃下在该低温热氧化膜上沉积一高介电常数材料；以及在温度范围为600至800℃下进行一快速热退火工艺；再氧化栅极绝缘膜的步骤为温度范围为750至950℃下进行的快速热氧化工艺；再氧化栅极绝缘膜的步骤为温度范围为600至1100℃下进行的快速尖峰热氧化工艺；步骤(h)通过在温度范围为650至800℃的氧化炉内进行热氧化工艺而进行；步骤(i)中的低温热处理为在温度范围为600至1000℃下进行的快速热退火工艺；步骤(i)中的低温热处理为在温度范围为600至1100℃下进行的快速尖峰热退火工艺；步骤(i)中的低温热处理在温度范围为300至750℃的炉内进行。
通过采用低离子注入能量的离子注入来掺杂通道以及在低于硅熔点的温度下进行高温快速热处理，来控制在先于SEG的后序氢预焙工艺中的杂质损失和SEG中的杂质扩散，一具有通道深度范围为10至30nm的超浅超陡逆分布外延通道被形成。
附图说明
参考用以说明而非限制本发明的附图，可以使所公布的方法得到更好的理解，其中：
图1至3为用以解释依据本发明的形成半导体器件中的晶体管的方法的截面图和示出由试验获得的数据图；
图4A至4F为示出依据第一实施例的形成半导体器件中的晶体管的方法的连续步骤的截面图；
图5为示出依据第二实施例的形成半导体器件中的晶体管的方法的截面图。
具体实施方式
优选的用以形成半导体器件中的晶体管的方法将被参照附图详细说明。
图1A为具有超浅超陡逆分布(SSR)硅外延(Si-Epi)通道的晶体管的截面图。参见图1A，该晶体管包括一半导体衬底11，一置于半导体衬底上的由一栅极绝缘膜19和一栅极电极21组成的堆叠结构，一置于该堆叠结构侧壁上的绝缘膜隔离层25，置于半导体衬底11上的位于堆叠结构两侧的源/漏区13和源/漏扩展区23，一置于源/漏扩展区23之下的穿透停止层(punch stop)27，一夹在源/漏扩展区23之间的通道层15，以及一置于栅极绝缘膜19下且位于通道层15上的外延通道层17。此处，具有小于100nm的通道长度的MOSFET或MISFET所要求的通道深度Wd必须等于或小于30nm，如Asen Asenov和Subhash Saini所著“具有外延和δ-掺杂通道的亚-0.1μm MOSFET中随机杂质引入的阈值电压波动的抑制”(IEEE电子器件学报，Vol 46，No 8，1999)。
图1B示出了理想δ掺杂形貌的由晶体缺陷产生的快速瞬时增强扩散(rapid transient enhanced diffusion)(TED)和下面热处理工艺引起的热扩散导致的展宽。如图1B所示，用来控制TED和热扩散的方法对SSR通道的形成是必要的。此处，Cs代表表面浓度，Cp代表峰值浓度，以及Gox代表一栅极氧化膜。
图2A示出了根据本发明的具有10nm通道深度的超浅SSR外延通道的掺杂形貌。如图2A所示，由于通道离子注入后的快速热处理中温度的升高，SEG后杂质的损失和再分配减小。值得注意的是，由于未进行高温通道热处理时杂质的严重的损失，期望的逆分布掺杂形貌未能获得。
图2A和2B分别示出了在通道离子注入能量在1KeV和5KeV下，离子注入1013离子/厘米2的B离子后，且在外延生长后直接在其上进行通道RTA的RTA条件下，SSR通道掺杂形貌的变化。
如图2A和2B所示，通道离子注入的能量越低，掺杂层的分布范围就越窄。此处，具有较窄分布区域的δ掺杂降低了器件的结电容和结漏电流，结果形成了低功高效半导体器件。
图3为二次离子质谱实验数据。如图3所示，即使是在根据本发明的通道深度为30nm的超浅外延通道，由于诸如低温栅极氧化和栅极构图工艺后的选择性栅极再氧化和为源/漏热处理等后工艺而受到杂质扩散的影响时，SSR的掺杂形貌依然被保持。值得注意的是，100nm MOSFET所需要的SSRδ-掺杂外延通道可根据如图3所示的本发明的方法形成。
图4A至4F为示出依据第一实施例的形成半导体器件中的晶体管的方法的连续步骤的截面图，其中CMISFET被作为例子而示出。
参考图4A，一在半导体衬底61上限定有源区的器件隔离膜63被形成。该器件隔离膜优选为沟槽型。
其后，一第一感光膜图案65被形成半导体衬底61上。该第一感光膜图案65通过使用一被称为n-阱曝光掩模的曝光掩模对CMISFET的pMISFET区域曝光的曝光和显影工艺形成。
一n-阱67利用第一感光膜图案65作为掩模将n型杂质离子注入至半导体衬底61内形成，然后在其上进行n-阱场停止离子注入。
一n型通道层69通过利用第一感光膜图案65作为掩模在能量范围为1至15KeV或3至30Ke的条件下注入p型通道的n型离子，诸如P或As，至n阱67处的衬底61内，而被形成，其具深度为在半导体衬底下10至50nm的范围。
参考图4B，第一感光膜图案65被去除，再在半导体衬底61上形成一第二感光膜图案71。该第二感光膜图案通过使用一被称为p-阱(p-well)曝光掩模的曝光掩模对CMISFET的nMISFET区域曝光的曝光和显影工艺形成。
一p-阱73利用第二感光膜图案71作为掩模将p型杂质离子注入至半导体衬底61内形成，然后在其上进行p-阱场停止(p-well field-stop)离子注入。
一p型通道层75通过利用第一感光膜图案65作为掩模在能量范围为100eV至1.5KeV的条件下注入n型通道的p型离子，诸如B，至p阱73处的衬底61内，而被形成，其具有在半导体衬底下10至50nm的范围内的很薄的深度。
参考图4C，第二感光膜图案71随后被去除。高温快速热处理工艺(RTA)或高温尖峰快速热处理工艺(SRTA)被进行，以去除为形成n型和p型通道层69和75而进行的离子注入所导致的半导体衬底61中的损伤，从而在pMISFET和nMISFET区域分别形成稳定n型通道层77和稳定p型通道层79。
此处，RTA和SRTA去除了晶体缺陷并使注入离子与晶体中邻近的硅原子稳定地结合，以使接下来的SEG和其后的热处理中，对杂质的扩散的控制最大化。
此处，RTA优选在900至1000℃的温度范围内进行，而SRTA优选在温度为1000至1100℃的高温下进行。
参考图4D，进行使用氢的表面处理以去除在形成稳定n型通道层77和稳定p型通道层79的那部分半导体衬底上部的自然氧化膜(未示出)。其后，每个厚度在5至30nm范围内的未掺杂硅外延(Si-Epi)层以SEG的方式被分别生长在稳定n型通道层77和稳定p型通道层79上，以使杂质的损失和再分布最小化。这样就完成了具有由一低浓度n型外延层81和n型通道层77以及一低浓度p型外延层83和p型通道层79分别组成的SSRδ-掺杂层的外延通道的形成。
该n型和p型外延层81和83优选具有厚度在5至30nm的范围，并且被其下的通道层自动掺杂为较低的浓度。
如图4E所示，栅极绝缘膜85和87被分别形成在半导体衬底上pMISFET和nMISFET中。
此处，该栅极绝缘膜85优选通过以下方式中的一种来形成，以使n型和p型通道层77和79中的杂质的扩散最小化，从而保持SSRδ-掺杂层的掺杂形貌：
(a)该栅极绝缘层可以通过在温度在650至750℃范围的蒸汽环境中生长一低温热氧化膜而被形成；
(b)该栅极绝缘层可为利用等离子处理氮化该低温热氧化膜而形成的低温氮化氧化膜；
(c)该栅极绝缘层可为一具有高介电常数的介电膜，其可按在300至650℃温度范围的低温沉积，然后将其在400至700℃温度范围的炉内进行热退火的方法形成，也可按在300至650℃温度范围的低温沉积，然后将其在600至800℃温度范围的炉内进行快速热退火的方法形成；以及
(d)该栅极绝缘层可为一由一如(a)的低温热氧化膜和一如(c)的低温介电膜在炉内进行热处理形成的堆叠结构。另外，该栅极绝缘层可为一由一如(a)的低温热氧化膜和一如(c)的低温介电膜进行快速热处理形成的堆叠结构。
参考图4F，栅极电极89和91通过在栅极绝缘膜85和87上构图而被形成，并随后进行栅极绝缘膜89和91的再氧化.
栅极绝缘膜的该再氧化优选采用如下方式中的一种：
(a)温度范围在750至950℃的快速热氧化(RTO)；
(b)温度范围在600至1100℃的快速尖峰热氧化；以及
(c)在温度范围在650至800℃的氧化炉中的热氧化。
其后，p型和n型源/漏扩展(SDE)区93和95被通过分别使用各自的曝光掩模在pMISFET和nMISFET区域内离子注入p型和n型杂质而形成。
绝缘膜缓冲层97和99随后被形成在栅极电极89和91的侧壁上。源/漏区101和103为具有高浓度的p型和n型杂质区，它随后通过使用各自的曝光掩模在pMISFET和nMISFET区域内离子注入高浓度的p型和n型杂质而被形成，紧接着进行后序热退火工艺来完成CMISFET的形成。
此处CMISFET的通道层77和79被作为穿透停止掺杂层(punch stopdoping layer)以防止短通道效应。
该后序热退火工艺可为快速热退火工艺，快速尖峰热退火工艺，或炉内的热退火工艺。
当该后序热退火工艺为快速热退火工艺时，RTA工艺的优选在温度为600至1000℃的范围内进行。当该后序热退火工艺为快速尖峰热退火工艺时，快速尖峰热退火工艺优选在温度为600至1100℃的范围内进行。当该后序热退火工艺为炉内的热退火工艺时，热退火工艺优选在温度为300至750℃的范围内进行。
图5为示出依据本发明第二实施例的形成半导体器件中的晶体管的方法的截面图，其中CMOSFET被示出。
如图5所示，CMOSFET还包括通过分别在如图4F的p型和n型SDE区域93和95下方的部分内倾斜(tilt)注入与阱导电类型相同的n型和p型杂质相同的口袋杂质(halo impurity)而形成的口袋区域105和107。
此处，该口袋区域用于控制晶体管的短通道效应以及改善器件的电学特性。
区前面讨论的，在此公开的用以形成半导体器件中的晶体管的方法具有如下优点：
(a)在外延通道结构形成中，通道杂质的损失与再分布被通过修复由离子注入通道区内导致的晶格损伤而得到控制，因此使形成超浅SSR通道结构成为可能。也即，具有通道长度小于100nm的器件内的由非均匀杂质分布导致的、可的引发Vt变化的随机杂质，以及由长度小于100nm的栅极导致的短通道效应被控制，并以此改善了通道长度小于100nm的器件的输出。
(b)通道区域表面的掺杂浓度被降低为通道层最高浓度的1/10，由此改善了表面的迁移率和电流驱动特性。
(c)依据本发明的超浅SSR通道结构可被应用于制造低电压低功率低阈值电压的器件。
由于所公布的技术可以被用若干不脱离本技术的精神及其主要特点的形式所表达，因此也应该被理解的是，前面描述的实施例除非被另外规定，并不被任何前面说明中的细节所限制，而是应被认为明确地属于所附权利要求所界定的精神和范围之内，并因此要求将所有落于该权利要求的界限或等同的界限之内的改动与调整包含于所附权利要求之中。

Claims (21)

1.一种用于形成半导体器件中的晶体管的方法，该方法包括步骤：
(a)利用一器件绝缘膜图案在半导体衬底上定义一第一和一第二区域；
(b)利用第一曝光掩模，在该第一区域内离子注入第一导电类型的杂质以形成一第一通道层；
(c)利用第二曝光掩模，在该第二区域内离子注入第二导电类型的杂质以形成一第二通道层；
(d)进行高温热处理以将该第一和第二通道层转变为第一和第二稳定通道层；
(e)在步骤(d)获得的结构上进行氢处理工艺；
(f)在该第一和第二稳定通道层上生长未掺杂硅外延层，由此产生具有超陡逆分布结构的一第一和一第二δ-掺杂外延通道；
(g)在该第一和第二δ-掺杂外延通道上形成一栅极绝缘膜和一栅极电极；
(h)再氧化该栅极绝缘膜以修复该栅极绝缘膜的被损伤的部分；以及
(i)形成一源/漏区并进行低温热处理。
2.根据权利要求1所述的方法，其中向该第一区域离子注入的工艺按使用As离子且离子注入能量范围为3至30KeV进行，或按使用P离子且离子注入能量范围为1至15KeV进行。
3.根据权利要求1所述的方法，其中该第一通道层被形成为在该半导体衬底表面下的深度范围为10至50nm。
4.根据权利要求1所述的方法，其中向该第二区域离子注入的工艺为按使用B离子且离子注入能量范围为100eV至1.5KeV进行。
5.根据权利要求1所述的方法，其中该第二通道层被形成为在该半导体衬底表面下的深度范围为10至50nm。
6.根据权利要求1所述的方法，其中该高温热处理为温度范围为900至1000℃的快速热处理。
7.根据权利要求1所述的方法，其中该进行高温热处理的步骤为一在温度范围为1000至1100℃下进行的尖峰高温热处理。
8.根据权利要求1所述的方法，其中该未掺杂硅外延层具有厚度范围为5至30nm。
9.根据权利要求1所述的方法，其中该形成一栅极绝缘膜的步骤为在蒸汽环境中温度范围为650至750℃下生长一低温热氧化膜。
10.根据权利要求1所述的方法，其中形成一栅极绝缘膜的步骤包括形成一低温热氧化膜，并利用等离子处理氮化该低温热氧化膜以形成一低温氧化氮化膜。
11.根据权利要求1所述的方法，其中该栅极绝缘层为一低温高介电常数膜。
12.根据权利要求11所述的方法，其中形成一栅极绝缘膜的步骤包括在温度范围为300至600℃下沉积一低温高介电常数膜，并且在温度范围为400至700℃的炉内进行一热退火工艺。
13.根据权利要求11所述的方法，其中形成一栅极绝缘膜的步骤包括在温度范围为300至650℃下沉积一低温高介电常数膜，并且在温度范围为600至800℃下进行一快速热退火工艺。
14.根据权利要求1所述的方法，其中形成一栅极绝缘膜的步骤包括：
在蒸汽环境中温度范围为650至700℃下生长一低温热氧化膜；
在温度范围为300至650℃下在该低温热氧化膜上沉积一高介电常数材料；以及
在温度范围为400至700℃的炉内进行一热退火工艺。
15.根据权利要求1所述的方法，其中形成一栅极绝缘膜的步骤包括：
在蒸汽环境中温度范围为650至750℃下生长一低温热氧化膜；
在温度范围为300至650℃下在该低温热氧化膜上沉积一高介电常数材料；以及
在温度范围为600至800℃下进行一快速热退火工艺。
16.根据权利要求1所述的方法，其中再氧化栅极绝缘膜的步骤是通过温度范围为750至950℃下的快速热氧化工艺进行的。
17.根据权利要求1所述的方法，其中再氧化栅极绝缘膜的步骤是通过在温度范围为600至1100℃下的快速尖峰热氧化工艺进行的。
18.根据权利要求1所述的方法，其中步骤(h)通过在温度范围为650至800℃的氧化炉内进行热氧化工艺而进行。
19.根据权利要求1所述的方法，其中步骤(i)中的低温热处理为在温度范围为600至1000℃下进行的快速热退火工艺。
20.根据权利要求1所述的方法，其中步骤(i)中的低温热处理为在温度范围为600至1100℃下进行的快速尖峰热退火工艺。
21.根据权利要求1所述的方法，其中步骤(i)中的低温热处理在温度范围为300至750℃的炉内进行。
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