CN1233091C - Recursive matched filter and matched filtering method - Google Patents

Abstract

The present invention relates to a recursive matched filter and a matched filtering method. The elements of an input ordinal number are maintained by a storage circuit. The elements maintained by the storage circuit are multiplied with corresponding joint factors by a multiplication circuit. The output of the multiplication circuit is added by a summarization circuit. The output of the summarization circuit is displaced by a displacement unit. A subtraction unit, an adder and an additional storage circuit are used, the first element and the final element of the maintained input ordinal number and the previous input ordinal number are summarized to obtain the sum of the existing input ordinal numbers, the sum of the input ordinal numbers and the summarized output are subtracted by the other subtraction unit, and one filter output is generated.

Description

Recursive matched filter and matched filtering method

Technical field

The invention relates to the matched filtering technique of exhibition frequency or Code Division Multiple Access communication system, refer to a kind of matched filter and matched filtering method especially with the computation performance of pulling over.

Background technology

Press, in present Mobile Communications are used, direct sequence Code Division Multiple Access (Direct-Sequence Code Division Multiple Access, DS/CDMA) technology can effectively be utilized frequency range owing to having, avoid interference and be applicable to the characteristic of different traffic forms (Traffic Pattern), therefore be subjected to gradually paying attention to widely, and when carrying out communication with the DS/CDMA technology, the data that transmitted stream (Data Stream) need with a unique spreading codes (Spreading Code) in addition modulation to distinguish other data stream, owing to this spreading codes is to operate with a speed that is higher than the data rate several times, therefore, the energy of information can be expanded to bigger frequency range, and the frequency range that can reach communication is simultaneously by effect that a plurality of user shared.

The modulation that aforementioned frequency spectrum launches is to be reached by the mode of direct sequence, the information symbol that also is about to transmit is to simulate (Pseodo-random at random, PN) sign indicating number modulation to a carrier wave, because the PN sign indicating number compared to the information symbol, has bigger frequency range, so the exhibition of behind modulation, can obtaining signal frequently, and generally speaking, the selection of PN sign indicating number is good with a long code, therefore, just needs complicated hardware circuit and quite long sign indicating number acquisition (Code Acquistion) time at receiving terminal.And the CDMA communication needs the exhibition frequency waveform of transmission end and receiving terminal to reach synchronously to set up binding, its synchronous processing is the process that comprises that sign indicating number acquisition and sign indicating number are followed the trail of (Code Tracking), wherein, the process of sign indicating number acquisition is that ordinal number by sign indicating number is to determine preliminary phase place, and the exhibition that summary will transmit and receive frequency waveform gives synchronously, so that keep the synchronous of sign indicating number with the process of being followed the trail of by sign indicating number.

And mainly be divided into coupling correlator (MatchedCorrelator) and matched filter two kinds of schemes such as (Matched Filter) in order to the circuit execution mode of reaching the sign indicating number acquisition, wherein, the use of coupling correlator is the PN sign indicating number of the signal that received and its use is multiplied each other and to add up it at receiving terminal, and the square value after adding up output promptly be compare with a critical value or based on probability in proper order than test (Sequential Probability Ratio Test, SPRT) judgement is to produce the decision that whether has obtained the sign indicating number acquisition, if the output of the square value after adding up does not surpass the output judgement that this critical value or SPRT produce sync fail, then receiving terminal need be adjusted the phase place of its PN sign indicating number, repeat said process till reaching synchronously, and because the length of this PN sign indicating number is extremely long, therefore, the coupling correlator significantly can be because of the very big uncertainty of the phase place of sign indicating number, and needs extremely long search time.

Matched filter then has the framework of similar finite response digital filter (Finite ImpulseResponse Filter), whether nationality produces the decision of sign indicating number acquisition in the mode of using filtering, with reference to known matched filter framework shown in Figure 4, it mainly is by storage circuit 41, mlultiplying circuit 42 and summation unit 43 constitute, wherein, storage circuit 41 has the delay buffer 411 of most serial connections, each postpones the delay that buffer 411 provides certain sheet elementary time (Tc), these postpone buffers 411 can be in order to keeping the sampled signal x (n) that sampling frequency was received with 1/Tc, even and if these contents that postpone buffers 411 with multiplication unit 421 and the joint efficiency (c that sets according to the synchronous PN sign indicating number of institute's desire by mlultiplying circuit 42 ₀, c ₁... c _N-1) (Tapc Coefficient) multiply each other, wherein, these joint efficiencies can be corresponding to certain segment of a PN sign indicating number or whole PN sign indicating numbers, and through after taking advantage of the process of calculation, this summation unit 43 just takes advantage of all the results added of calculation to produce following filtering output

y(n)：

$y\left(n\right)=\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}{c}_{N-1-m}\·x(n-m),---\left(1\right)$

And because the element of PN sign indicating number only may be-1 or 1, only be the symbol that is to handle the content that storage circuit 42 kept so take advantage of the process of calculation.For the phase place of acquisition code accurately, this PN sign indicating number must have enough length and whole PN sign indicating number all need in order to the Signal Matching that is received, so in the application of reality, for obtaining the sequential of PN sign indicating number reliably, the length of this PN sign indicating number is usually greater than 200, therefore, the number of required joint efficiency is quite big, apparently, when the length of PN sign indicating number is long more, to have many more add operations to need to carry out, and this a large amount of add operation has caused a large amount of consumption of electric energy of filter and the problem that filtering speed can't promote, and the utmost point is waited to be improved.

In known patent documentation, U.S. USP5663983 number " the difference matched filter of Zhan Pin system " patent case is may have the characteristic of identical value based on two adjacent elements of PN sign indicating number, and be able to the output that less add operation produces matched filter, though can improve aforesaid problem by this, but desire to be subject to the condition that the PN sign indicating number need have identical adjacent element, so still have necessity of further improving.

Inventor whence is because of in this, this is in the spirit of positive invention, the utmost point is thought a kind of " can be used for opening up frequently or the recursive matched filter and the matched filtering method of Code Division Multiple Access communication system " that can address the above problem, and several times research experiment is eventually to finishing this novel progressive invention.

Summary of the invention

Purpose of the present invention is providing a kind of recursive matched filter and filtering method, and it can only carry out matched filter processing with few add operation, and is not subject to the form of PN sign indicating number.

For reaching aforesaid purpose, a kind of recursive matched filter of the present invention mainly comprises:

One filtering operation circuit is in order to keeping the element of an input ordinal number, and the joint efficiency of filter is carried out Filtering Processing to produce an output with corresponding element; It is characterized in that the filtering operation circuit further comprises:

One storage circuit is connected in series by N+1 delay element to form, and keeps it with the element that will import ordinal number respectively, and wherein, N is the natural number greater than 1;

One mlultiplying circuit is that the element that the top n delay element with this storage circuit is kept multiplies each other with corresponding joint efficiency;

One summation circuit is that the output with this mlultiplying circuit gives addition, and

One shift unit is that shifting processing is carried out in the output of this summation circuit;

One first subtrator is that first element and the last element of input ordinal number that this filtering operation circuit is kept subtracts each other;

One adder has first and second input, and this first input end is the output that receives this first subtrator;

One additional storage circuit is made of at least one delay element, and its input receives the output of this adder, and its output is connected to second input of this adder; And

One second subtrator is that the output of this adder and the output of this filtering operation circuit are subtracted each other, to produce filtering output.

Wherein also comprise a sign bit cell management unit, to adjust the sign symbol of this filtering output.

A kind of recursive matched filter of the present invention is characterized in that, mainly comprises:

One filtering operation circuit is in order to keeping the element of an input ordinal number, and the joint efficiency of filtering operation circuit is carried out Filtering Processing to produce an output with corresponding element;

The filtering operation circuit further comprises:

One storage circuit is that oil a delay element and N delay element group are connected in series and form, and each delay element group has the delay element of a plurality of serial connections, and will import the element maintenance of ordinal number respectively, wherein, N is the natural number greater than 1;

One mlultiplying circuit, be with the output of the delay element of this storage circuit and before the output and the corresponding engagement multiplication of N-1 delay element group;

-summation circuit is that the output with this mlultiplying circuit gives addition; And

One shift unit is that shifting processing is carried out in the output of this summation circuit;

One sign bit cell management unit is the joint efficiency in order to the calculation of filtered computing circuit;

One first subtrator is that first element and the last element of input ordinal number that this filtering operation circuit is kept subtracts each other;

One adder has first and second input, and this first input end is the output that receives this first subtrator;

One additional storage circuit is made of at least one delay element, and its input receives the output of this adder, and its output is connected to second input of this adder; And

One second subtrator is that the output of this adder and the output of this filtering operation circuit are subtracted each other, to produce filtering output.

Wherein this filtering operation circuit comprises:

One storage circuit is connected in series by N+1 delay element to form, and keeps it with the element that will import ordinal number respectively, and wherein, N is the natural number greater than 1;

One mlultiplying circuit is that the element that the top n delay element with this storage circuit is kept multiplies each other with corresponding joint efficiency;

One summation circuit is that the output with this mlultiplying circuit gives addition, and

One shift unit is that shifting processing is carried out in the output of this summation circuit.

Wherein this additional storage circuit is made of a delay element, and the delay element of this additional storage circuit provides identical time of delay with a delay element of this storage circuit.

Wherein this mlultiplying circuit has N multiplication unit respectively element and the corresponding engagement coefficient that should the top n delay element be kept carried out multiplying.

Wherein this summation circuit is the output addition with this N multiplication unit.

Wherein this shift unit is that output with this summation circuit is to the bit that shifts left.

Each the delay element group that wherein should add storage circuit and storage circuit has the delay element of similar number.

Wherein this storage circuit all provides identical time of delay with each delay element of additional storage circuit.

Wherein this mlultiplying circuit have N multiplication unit with respectively to the output of delay element that should storage circuit and before the output of N-1 delay element group carry out multiplying.

Wherein this summation circuit is the output addition with this N multiplication unit.

Wherein this shift unit is that output with this summation circuit is to the bit that shifts left.

A kind of recursive matched filtering method of the present invention is characterized in that, mainly comprises following step:

A plurality of elements of one input ordinal number are kept it;

The joint efficiency of filtering is multiplied each other with corresponding element;

This input ordinal number is added up and multiply by a set point mutually with the product of joint efficiency, add up output to produce one;

Ask for present input ordinal number sum by first and the last element of the input ordinal number that is kept and previous input ordinal number sum; And

Should import the output of ordinal number sum and this totalling and subtract each other, to produce filtering output.

Wherein in will importing ordinal number and step that the product of joint efficiency adds up mutually, this set point is 2.

Wherein in will importing the step that ordinal number and joint efficiency multiply each other, be all elements and the corresponding engagement multiplication beyond the last element of the input ordinal number that to be kept.

Wherein also comprise a step to adjust the sign symbol of this filtering output.

Because modern design of the present invention can provide on the industry and utilize, and truly have the enhancement effect, so apply for a patent in accordance with the law.

Description of drawings

For making your juror can further understand structure of the present invention, feature and purpose thereof, the attached now detailed description with graphic and preferred embodiment as after, wherein:

Fig. 1 is for transmitting and receive the schematic diagram of spread spectrum signal in the communication system in action.

Fig. 2 is the Organization Chart for a preferred embodiment of recursive matched filter of the present invention.

Fig. 3 is the Organization Chart for another preferred embodiment of recursive matched filter of the present invention.

Fig. 4 is the Organization Chart for known matched filter.

Embodiment

Relevant recursive matched filter of the present invention and matched filtering method, please be earlier with reference to shown in Figure 1, it is that to be presented in the Mobile Communications system with a base station 11 be that transmission ends transmits spread spectrum signal, the digital modulation tech modulation of this spread spectrum signal process is to communication channel, that is the signal that is transmitted can be written as:

$\begin{array}{c}s\left(t\right)=\underset{t=-\∞}{\overset{\∞}{\mathrm{\Σ}}}c(t-\mathrm{\λN}{T}_c)[\cos (2\mathrm{\π}{f}_{c}t+\mathrm{\θ})+j\sin (2f_{c}t+\mathrm{\θ})]\\ =\underset{t=-\∞}{\overset{\∞}{\mathrm{\Σ}}}c(t-\mathrm{\λN}{T}_c)\·e^{j(2{\mathrm{\πf}}_{c}t+\mathrm{\θ})}\end{array}$

Wherein, f _cBe carrier frequency (Carried Frequency) that θ is frequency shift (FS),

And $c\left(t\right)=\underset{n=0}{\overset{N-1}{\mathrm{\Σ}}}{c}_n\·p(t-\mathrm{nTc})$ Be exhibition frequency waveform, in N element (c of this exhibition frequency waveform ₀, c ₁... c _N-1) value be+1 or-1, and constitute the PN sign indicating number, each element wherein is the time of keeping a Tc, p (t) transmits the impulse response of the filter of waveform for control.

And behind the spread spectrum signal of antenna 12 receptions from this base station 11 of receiving terminal, just by after the power amplification of high-frequency receiver 13 with this spread spectrum signal, via a bifurcated device (Splitter) 14 minutes to two blenders (Mixer) 151 and 152, wherein, first blender 151 is output and a carrier wave cos (the 2 π f with bifurcated device 14 _cT) multiply each other second blender 152 output and another carrier wave sin (2 π f with bifurcated device 14 _cT) multiply each other, the output of this first blender 151 through the Filtering Processing of one first low pass filter 161 with filtering high-frequency signal composition, and produce one mutually in fundamental frequency signal continuous time (In-phase Continuous-time Base-band) R _i(t), the output of this second blender 152 then through the Filtering Processing of one second low pass filter 162 with filtering high-frequency signal composition, and produce quadrature phase fundamental frequency signal continuous time (Quadrature-phase Continuous-time Base-band) R _Q(t).

A preferred embodiment of the present invention is to use one first A/D converter 171 with the sampling frequency of 1/Tc signal Ri (t) to be taken a sample, and the conversion of signals of taking a sample is the digital signal R of correspondence _i(n), similarly, the present invention also use one second A/D converter 172 with the sampling frequency of 1/Tc to signal R _Q(t) take a sample, and the conversion of signals of taking a sample is the digital signal R of correspondence _Q(n), this output sampling R _i(n) and R _Q(n) then deliver to I--branch matched filter 191 and Q--branch matched filter 192 respectively to carry out the processing of sign indicating number acquisition, and because I--branch matched filter 191 and Q--branch matched filter 192 are to use identical PN sign indicating number, therefore, this two filter 191 and 192 also is to have identical formation, so following narration is the example explanation with a matched filter only, and represents this output sampling R with an input ordinal number x (n) _i(n) and R _Q(n).

And when giving a PN sign indicating number, this PN data code value is that+1 number and element value may be identical or different for-1 number, be that the number of+1 element is more as default, and the output ordinal number basis (1) of then known matched filter can be rewritten as:

$\begin{array}{c}y\left(n\right)=\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}x(n-m)-2\·\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}\frac{(1-c_{N-1-m)}}{2}\·x(n-m)\\ =z\left(n\right)-2\·\underset{m=0}{\overset{N-1}{\mathrm{\Σ}}}{e}_m\·x(n-m)\end{array}---\left(2\right)$

By above-mentioned expression as can be known, because z (n)=z (n-1)+x (n)-x (n-N), therefore, can be by calculating its result with pulling over, and output ordinal number z (n) is only obtained with 2 add operations, again because above joint efficiency over half $e_m(e_m=\frac{1-c_{N-1-\mathrm{<figure-callout\; id="2"\; label="m"\; filenames="C0010739500201.png,C0010739500221.png"\; state="\{\{state\}\}">m</figure-callout>}}}{2}\&Element;\{\mathrm{0,1}\left\}\right)$ Value be 0,

Therefore, second on the right side of expression (2) at most only needs half add operation of known matched filter, is promptly significantly increased the speed of matched filtering in view of the above.

And for example the number of-1 element of PN sign indicating number can be rewritten as the output ordinal number of known matched filter more for a long time according to (1):

$\begin{array}{c}y\left(n\right)=-\{\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}x(n-m)-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}\frac{(1+c_{N-1-m})}{2}\&CenterDot;x(n-m)\}\\ =-\{z\left(n\right)-2\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-m)\}\end{array}---\left(3\right)$

Similarly, by above-mentioned expression as can be known, also because z (n)=z (n-1)+x (n)-x (n-N), therefore, can be by calculating its result with pulling over, and output ordinal number z (n) is only obtained with 2 add operations, and because above joint efficiency over half $e_m(e_m=\frac{1+c_{N-1-\mathrm{<figure-callout\; id="2"\; label="m"\; filenames="C0010739500201.png,C0010739500221.png"\; state="\{\{state\}\}">m</figure-callout>}}}{2}\&Element;\{\mathrm{0,1}\left\}\right)$ Value be 0,

Therefore, second on the right side of expression (3) at most only needs half add operation of known matched filter, is promptly significantly increased the speed of matched filtering in view of the above.

With reference to shown in Figure 2, be to be the preferred embodiment in order to the recursive matched filter of realizing the aforementioned computing of pulling over of the present invention, it has a filtering operation circuit 20 so that input ordinal number x (n) is carried out Filtering Processing, this filtering operation circuit 20 is made of storage circuit 21, mlultiplying circuit 22, summation unit 23 and shift unit 24, and this storage circuit 21 is the delay element D by a plurality of indivedual delay Tc times ₀-D _NBe connected in series and form (N for greater than 1 natural number), with when after importing ordinal number x (n) and entering filter, delay element D ₀-D _NThe value that keeps and export is respectively x (n)-x (n-N), and delay element D ₀-D _N-1Output then respectively with joint efficiency e ₀-e _N-1Correspondence is connected to a plurality of multiplication unit M of this mlultiplying circuit 22 ₀-M _N-1, with respectively with a delay element D ₀-D _N-1The output joint efficiency e corresponding with one ₀-e _N-1Multiply each other, and these multiplication units M ₀-M _N-1Output then be connected to summation unit 23, give addition and obtain with the result who this is taken advantage of calculation $(\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-m))$ Operation values,

The output of this summation unit 23 then is connected to this shift unit 24, with the processing of the bit that moves to left, and will so that produce $(\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-m))$ Multiply by 2 effect.

Delay element D again ₀-D _NOutput and the output that is connected to one first subtrator 25 to carry out the computing of x (n)-x (n-N), the output that the output of this first subtrator 25 then is connected to an adder 27 is the input that is connected to an additional storage circuit 28, should additional storage circuit 28 be the delay elements that postpone the Tc time for, and the output that should add storage circuit 28 is another inputs that are connected to this adder 27, therefore, number is when progressing into filter in regular turn as input ordinal number x (n), and this first subtracter 25 and adder 27 just can be by the delay element D of this storage circuit 21 ₀-D _NOutput and previous input ordinal number sum and ask for present input ordinal number sum, can realize the computing of pulling over of z (n)=z (n-1)+x (n)-x (n-N) by this.

The output of the output of this adder 27 and this shift unit 24 is to be connected to one second subtrator 26, produces to carry out subtraction $z\left(n\right)-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-m)$ Operation result,

The output of this second subtrator 26 then by a sign bit cell management unit 29 with foundation PN sign indicating number+1 or the number of-1 element adjust its sign symbol, produce in view of the above $(z\left(n\right)-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-m))$ Or $(-\{z\left(n\right)-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-m))$

Filtering output, and be able under the whether identical situation of the adjacent element that is not subject to the PN sign indicating number, carry out the processing of matched filtering with few add operation.

Another preferred embodiment of the present invention is to capture for carry out sign indicating number with higher frequency, and the sampling frequency that also is about to A/D converter shown in Figure 1 171 and 172 rises to M/Tc, and under this higher sampling frequency, known matched filter output can be written as:

$y\left(n\right)=\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{c}_{N-1-m}\&CenterDot;x(n-\mathrm{mM})$

And when the PN sign indicating number+number of 1 element is more, the output ordinal number of then known matched filter can be rewritten as:

$\begin{array}{c}y\left(n\right)=\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}x(n-\mathrm{mM})-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}\frac{(1-c_{N-1-m)}}{2}\&CenterDot;x(n-\mathrm{mM})\\ =z\left(n\right)-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-\mathrm{mM})\end{array}---\left(4\right)$

By above-mentioned expression as can be known, because z (n)=z (n-M)+x (n)-x (n-NM), therefore, can be by calculating its result with pulling over, and output ordinal number z (n) is only obtained with 2 add operations, again because above joint efficiency over half $e_m(e_m=\frac{1-c_{N-1-\mathrm{<figure-callout\; id="2"\; label="m"\; filenames="C0010739500201.png,C0010739500221.png"\; state="\{\{state\}\}">m</figure-callout>}}}{2}\&Element;\{\mathrm{0,1}\left\}\right)$ Value be 0,

Therefore, second on the right side of expression (4) at most only needs half add operation of known matched filter, in view of the above and is significantly increased the speed of matched filtering.

And for example-1 element of PN sign indicating number more for a long time, the output ordinal number of known matched filter can be rewritten as:

$\begin{array}{c}y\left(n\right)=\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}x(n-\mathrm{mM})-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}\frac{(1-c_{N-1-m)}}{2}\&CenterDot;x(n-\mathrm{mM})\\ =-\{z\left(n\right)-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-\mathrm{mM})\}\end{array}---\left(5\right)$

Similarly, by above-mentioned expression as can be known, because z (n)=z (n-M)+x (n)-x (n-NM), therefore, can be by calculating its result with pulling over, and output ordinal number z (n) is only obtained with 2 add operations, and because above joint efficiency over half $e_m(e_m=\frac{1+c_{N-1-\mathrm{<figure-callout\; id="2"\; label="m"\; filenames="C0010739500201.png,C0010739500221.png"\; state="\{\{state\}\}">m</figure-callout>}}}{2}\&Element;\{\mathrm{0,1}\left\}\right)$ Value be 0,

Therefore, second on the right side of expression (5) at most only needs half add operation of known matched filter, in view of the above and is significantly increased the speed of matched filtering.

Fig. 3 is the Organization Chart that has than the recursive matched filter of high sampling frequency of the present invention, it has a filtering operation circuit 30 so that input ordinal number x (n) is carried out Filtering Processing, this filter computing circuit 30 is made of storage circuit 31, mlultiplying circuit 32, summation unit 33 and shift unit 34, and this storage circuit 31 is the delay element D by a plurality of indivedual delay Tc/M times ₀-D _NMBe connected in series and form (N, M for greater than 1 natural number), wherein, delay element D ₀-D _NMBe to be one group of delay element group S that divides into the N level with M ₀-S _N, with after entering filter in input ordinal number x (n), delay element D ₀And delay element group S ₀-S _NThe value that keeps and export is respectively x (n), x (n-M) ... x (n-(N-1) M-1), x (n-NM), and delay element D ₀And delay element group S ₀-S _N-1Output then with respectively with joint efficiency e ₀-e _N-1Correspondence is connected to a plurality of multiplication unit M of this mlultiplying circuit 32 ₀-M _M-1, with respectively with element D ₀And element S ₀-S _N-1Output and corresponding engagement coefficient e ₀-e _N-1Multiply each other, and these multiplication units M ₀-M _N-1Output then be connected to this summation unit 33, give addition and obtain with the result who this is taken advantage of calculation $\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-\mathrm{mM})$ Operation result,

The output of this summation unit 33 then is connected to this shift unit 34, with the processing of the bit that moves to left, and will so that produce $\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-\mathrm{mM})$ Multiply by 2 effect.

Delay element D again ₀And element group S _NOutput and the input that is connected to one first subtrator 35 to carry out the computing of x (n)-x (n-NM), the output of this first subtrator 35 then is connected to an input of an adder 37, the output of this adder 37 is the inputs that are connected to an additional storage circuit 38, should additional storage circuit 38 be that delay element by M delay Tc/M time is connected in series and forms, and the output that should add storage circuit 38 then is connected to this adder 37 another inputs, therefore, when the input ordinal number progressed into filter in regular turn, this first subtracter 35 and adder 37 just can be by the delay element D of this storage circuit 31 ₀And delay element group S _NOutput and previous input ordinal number sum and ask for present input ordinal number sum, can realize the computing of pulling over of z (n)=z (n-M)+x (n)-x (n-NM) by this.

The output of the output of this adder 37 and this shift unit 34 then is connected to one second subtrator 36, produces to carry out subtraction $z\left(n\right)-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-\mathrm{mM})$ Operation result,

The output of this second subtrator 36 then by a sign bit cell management unit 39 with foundation PN sign indicating number+1 or the number of-1 element adjust its sign symbol, and export $z\left(n\right)-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-\mathrm{mM})$ Or $-\{z\left(n\right)-2\&CenterDot;\underset{m=0}{\overset{N-1}{\mathrm{\&Sigma;}}}{e}_m\&CenterDot;x(n-\mathrm{mM})\}$

Filtering output, therefore, also be able under higher sampling frequency, carry out the processing of matched filtering with few add operation, and whether be not subject to the adjacent element of PN sign indicating number identical.

With regard to the application in future, in the third generation W-CDMA wireless telecommunication system of being formulated by 3GPP (3rd Generation PartnershipProject), bright fixed all base stations all can descend to pass (Downlink) fixing synchronizing signal at present, in order between mobile phone and base station synchronously, and this synchronizing signal is by a Cp=[a, a, a ,-a ,-a, a,-a ,-a, a, a, a ,-a, a,-a, a, a] sign indicating number of form is formed, and above-mentioned a is made of 16 unit, its unit can be expressed as a=[1 1111 1-1-1 1-1 1 ... 11 ... 1-11], number expression of "-" wherein is anti-phase.No matter mobile phone is the state in start, or mobile phone moves the service (being Handoff) that needs new base station, and mobile phone all needs to carry out matched filtering with received signal at any time.So receiver at mobile phone, can use known matched filter to carry out the sign indicating number acquisition of synchronizing signal, to obtain the clock pulse of this base station, this known matched filter needs the computing of 255 addition and subtractions to finish the output of a filtering, and, then only need 122 method computings in addition as using according to recursive matched filter of the present invention, can finish the output of a filtering, therefore, can save considerable computing.

To sum up institute is old, and no matter the present invention is all showing it totally different in the feature of known techniques with regard to purpose, means and effect, is the quantum jump that matched filter designs, and earnestly asks your juror to perceive, and grants quasi patent early, so that Jiahui society, the true feeling moral just.Only it should be noted that above-mentioned many embodiment give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not is limited to the foregoing description.

Claims (17)

1. recursive matched filter mainly comprises:

One filtering operation circuit is in order to keeping the element of an input ordinal number, and the joint efficiency of filter is carried out Filtering Processing to produce an output with corresponding element; It is characterized in that the filtering operation circuit further comprises:

One storage circuit is connected in series by N+1 delay element to form, and keeps it with the element that will import ordinal number respectively, and wherein, N is the natural number greater than 1;

One mlultiplying circuit is that the element that the top n delay element with this storage circuit is kept multiplies each other with corresponding joint efficiency;

One summation circuit is that the output with this mlultiplying circuit gives addition, and

One shift unit is that shifting processing is carried out in the output of this summation circuit;

One first subtrator is that first element and the last element of input ordinal number that this filtering operation circuit is kept subtracts each other;

One adder has first and second input, and this first input end is the output that receives this first subtrator;

One additional storage circuit is made of at least one delay element, and its input receives the output of this adder, and its output is connected to second input of this adder; And

One second subtrator is that the output of this adder and the output of this filtering operation circuit are subtracted each other, to produce filtering output.

2. recursive matched filter according to claim 1 is characterized in that, wherein also comprises a sign bit cell management unit, to adjust the sign symbol of this filtering output.

3. a recursive matched filter is characterized in that, mainly comprises:

One filtering operation circuit is in order to keeping the element of an input ordinal number, and the joint efficiency of filtering operation circuit is carried out Filtering Processing to produce an output with corresponding element;

The filtering operation circuit further comprises:

One storage circuit is that oil a delay element and N delay element group are connected in series and form, and each delay element group has the delay element of a plurality of serial connections, and will import the element maintenance of ordinal number respectively, wherein, N is the natural number greater than 1;

One mlultiplying circuit, be with the output of the delay element of this storage circuit and before the output and the corresponding engagement multiplication of N-1 delay element group;

One summation circuit is that the output with this mlultiplying circuit gives addition; And

One shift unit is that shifting processing is carried out in the output of this summation circuit;

One sign bit cell management unit is the joint efficiency in order to the calculation of filtered computing circuit;

One first subtrator is that first element and the last element of input ordinal number that this filtering operation circuit is kept subtracts each other;

One adder has first and second input, and this first input end is the output that receives this first subtrator;

One additional storage circuit is made of at least one delay element, and its input receives the output of this adder, and its output is connected to second input of this adder; And

One second subtrator is that the output of this adder and the output of this filtering operation circuit are subtracted each other, to produce filtering output.

4. recursive matched filter according to claim 3 is characterized in that, wherein this filtering operation circuit comprises:

One storage circuit is connected in series by N+1 delay element to form, and keeps it with the element that will import ordinal number respectively, and wherein, N is the natural number greater than 1;

One mlultiplying circuit is that the element that the top n delay element with this storage circuit is kept multiplies each other with corresponding joint efficiency;

One summation circuit is that the output with this mlultiplying circuit gives addition, and

One shift unit is that shifting processing is carried out in the output of this summation circuit.

5. recursive matched filter according to claim 4, it is characterized in that, wherein this additional storage circuit is made of a delay element, and the delay element of this additional storage circuit provides identical time of delay with a delay element of this storage circuit.

6. recursive matched filter according to claim 4 is characterized in that, wherein this mlultiplying circuit has N multiplication unit respectively element and the corresponding engagement coefficient that should the top n delay element be kept carried out multiplying.

7. recursive matched filter according to claim 6 is characterized in that, wherein this summation circuit is the output addition with this N multiplication unit.

8. recursive matched filter according to claim 4 is characterized in that, wherein this shift unit is that output with this summation circuit is to the bit that shifts left.

9. recursive matched filter according to claim 3 is characterized in that, each the delay element group that wherein should add storage circuit and storage circuit has the delay element of similar number.

10. recursive matched filter according to claim 9 is characterized in that, wherein this storage circuit all provides identical time of delay with each delay element of additional storage circuit.

11. recursive matched filter according to claim 3 is characterized in that, wherein this mlultiplying circuit have N multiplication unit with respectively to the output of delay element that should storage circuit and before the output of N-1 delay element group carry out multiplying.

12. recursive matched filter according to claim 11 is characterized in that, wherein this summation circuit is the output addition with this N multiplication unit.

13. recursive matched filter according to claim 3 is characterized in that, wherein this shift unit is that output with this summation circuit is to the bit that shifts left.

14. a recursive matched filtering method is characterized in that, mainly comprises following step:

A plurality of elements of one input ordinal number are kept it;

The joint efficiency of filtering is multiplied each other with corresponding element;

This input ordinal number is added up and multiply by a set point mutually with the product of joint efficiency, add up output to produce one;

Ask for present input ordinal number sum by first and the last element of the input ordinal number that is kept and previous input ordinal number sum; And

Should import the output of ordinal number sum and this totalling and subtract each other, to produce filtering output.

15. recursive matched filtering method according to claim 14 is characterized in that, wherein in will importing ordinal number and step that the product of joint efficiency adds up mutually, this set point is 2.

16. recursive matched filtering method according to claim 14, it is characterized in that, wherein in will importing the step that ordinal number and joint efficiency multiply each other, be all elements and the corresponding engagement multiplication beyond the last element of the input ordinal number that to be kept.

17. recursive matched filtering method according to claim 14 is characterized in that, wherein also comprises a step to adjust the sign symbol of this filtering output.

Images