CN1231445A - Grouped data communication between multiple controllers - Google Patents
Grouped data communication between multiple controllers Download PDFInfo
- Publication number
- CN1231445A CN1231445A CN98111658A CN98111658A CN1231445A CN 1231445 A CN1231445 A CN 1231445A CN 98111658 A CN98111658 A CN 98111658A CN 98111658 A CN98111658 A CN 98111658A CN 1231445 A CN1231445 A CN 1231445A
- Authority
- CN
- China
- Prior art keywords
- bus
- controller
- reception
- integrated data
- master controller
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Images
Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L47/00—Traffic control in data switching networks
- H04L47/10—Flow control; Congestion control
- H04L47/13—Flow control; Congestion control in a LAN segment, e.g. ring or bus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/10—Packet switching elements characterised by the switching fabric construction
- H04L49/102—Packet switching elements characterised by the switching fabric construction using shared medium, e.g. bus or ring
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L49/00—Packet switching elements
- H04L49/55—Prevention, detection or correction of errors
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L12/00—Data switching networks
- H04L12/54—Store-and-forward switching systems
- H04L12/56—Packet switching systems
- H04L12/5601—Transfer mode dependent, e.g. ATM
- H04L2012/5603—Access techniques
- H04L2012/5609—Topology
- H04L2012/5613—Bus (including DQDB)
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Small-Scale Networks (AREA)
Abstract
A packet data communication system including a plurality of controllers for sending and receiving the packet data. The packet data communication system includes a first and a second master controllers; a plurality of slave controllers; a sending bus connected between the master controllers and the slave controllers, which provides a transmission path for the packet data transmitted from a master controller to a slave controller; and a receiving bus connected between the master controllers and the slave controllers and separate from the sending bus, which provides a receiving path for the packet data transmitted from a master controller to a slave controller. Here, when only one master controller is available, the available master controller can process the send and receive operation for the packet data alone, and when the two master controllers are available, the two groups share the send and receive operation for the packet data.
Description
The present invention relates to a kind of packet data communication system, and particularly, relate to and including one and be used to send/block data communication between a plurality of plates of the controller of receiving block data.
Usually, resemble department of computer science's such packet data communication system of RAS (remote access server) system of unifying and comprise a plurality of plates that include a controller.Each self-controller in the plate is connected with each other by the data bus that transmits integrated data.For data bus, use VME (Versa Module Eurocard) bus usually, PCI (external unit is interconnected) bus, closely pci bus and 2 grades of buses of UTOPIA (universal test and the operating physical layer interface that are used for asynchronous transfer mode).
At VME, in PCI and the tight pci bus structure, send and receive the common use of operation bus, it is difficult therefore transmitting mass data in the limited time.Particularly, when plate adopted pci bus and tight pci bus, the slot quantity on the plate was restricted to 4 and 8 respectively.In this case, independently PCI is to the PCI bridging chip unless use, and the slot quantity on the expansion board is difficult.Further, adopting the VME bus, in the packet communication system of pci bus and tight pci bus, each plate all is set to a master controller or a slave controller, and therefore requiring independently, control operation is provided with plate to master controller or slave controller.
Use UTOPIA2 level bus to address this problem.That is, in UTOPIA2 level bus, bus is respectively applied for and sends and receive operation, therefore can transmit mass data with very high speed.In addition, it does not require and is used for plate is provided with independently control operation to master controller or slave controller, because these plates have been arranged to master controller and slave controller.
Yet, in the packet communication system that adopts this UTOPIA2 level bus, only a plate is provided with to master controller.Therefore, in the time can not obtaining this plate, total system all can not be operated.Further, adopt the packet communication system of UTOPIA2 level bus not carry out parity-check operations, this will reduce the transmission of packet data reliability.
Therefore an object of the present invention is to provide a packet data communication system that improves reliability, it has a plurality of plates that are used to send with the controller of receiving block data that include.
Another object of the present invention provides one and has a plurality of packet data communication systems that are used to send with the plate of receiving block data, even it also can normal running in the time can not obtaining a plate.
Another object of the present invention provides one and has a plurality of packet data communication systems that are used to send with the plate of receiving block data, and it can transmit mass data with very high speed.
For realizing top purpose, a packet data communication system is provided here, it comprises a plurality of controllers that are used to send with receiving block data.This packet data communication system comprises first and second master controllers; A plurality of slave controllers; Be connected the transmission bus between master controller and the slave controller, it provides transmission path for the integrated data that is sent to a slave controller from a master controller; And be connected between master controller and the slave controller, with the reception bus that the transmission bus is separated, it provides RX path for a master controller from a slave controller receiving block data.Here, but when having only a master controller time spent, available master controller carries out the transmission of integrated data alone and receives operation, but and when two master controllers time spent all, two master controllers are shared the transmission of integrated data and received operation.
Each first and second master controller comprises one first packet bus controller, and this packet bus controller comprises: one sends bus processor, and it is used for handling the right to use of the transmission bus between first and second master controllers; A transmission storer that is used for the integrated data of temporary transient storage transmission; A transmit control device, it is used for will sending integrated data by the transmission bus and sends first slave controller to; One receives bus processor, and it is used for handling the right to use of the transmission bus between first and second master controllers; A reception controller, it is used to receive the integrated data that sends to the reception bus from second slave controller; With a temporary transient reception memorizer of storing the integrated data that receives.
Transmit control device in the first packet bus controller sends one and sends bus request signal to sending bus controller, grant the right to use that it sends bus if send bus controller, then from send storer, read the transmission integrated data, and the transmission integrated data that will read sends to the transmission bus.This transmit control device comprises that one is used for transmit control device is connected to the transmission storer link that sends storer; One is used for transmit control device is connected to the transmission bus link that sends bus; One is connected the even-odd generator that sends between storer link and the transmission bus link, is used to produce a parity; With a transmit control device link, it is used to control the connection between transmit control device and the transmission bus controller, if and to send the right to use of bus, then the bus link will send transmission integrated data in the storer link and the parity values of even-odd generator generation sends to the transmission bus by sending.
Reception controller in the first packet bus controller sends one and receives bus request signal to receiving bus controller, grant the right to use that it receives bus if receive bus controller, then receive the receiving block data on the bus, and the integrated data that receives is stored in the reception memorizer.This reception controller comprises that one is used for and will receives the reception memorizer link that controller is connected to reception memorizer; One is used for being connected to the reception bus link that receives bus with receiving controller; A parity checker that is connected between reception memorizer link and the reception bus link is used for carrying out the parity error verification by the receiving block data that receives the reception of bus link; With a reception controller link, be used to control the connection that receives between controller and the reception bus controller, if and the right to use of acquisition reception bus, then the transmission integrated data that will receive on the bus by parity checker and reception memorizer link is stored in the reception memorizer.According to the parity error check to receiving block data, parity checker requires to receive the bus link and resends integrated data; Wherein under the request that resends of parity checker, described reception bus link requires second slave controller to resend integrated data.
Each slave controller comprises one second packet bus controller, and this second packet bus controller comprises the transmission storer that is used for temporary transient storage transmission integrated data; One is connected to the transmit control device that receives bus, is used to respond the control signal of sending from one first and second master controller, will send integrated data and send to the reception bus; One is connected to the reception controller that sends bus, is used to respond the control signal of sending from one first and second master controller, receives by sending the integrated data that bus sends from one first and second master controller; With a reception memorizer, be used for temporary transient storage by receiving the integrated data that controller receives.
Transmit control device in the second packet bus controller comprises that one is used for transmit control device is connected to the transmission storer link that sends storer and read the transmission integrated data from the transmission storer; An even-odd generator is used to send the transmission integrated data generation parity that the storer link reads; With a reception bus link, be used to control the connection between transmit control device and the reception bus, and the control signal sent from one first and second master controller of response, make to send the storer link and can read the transmission integrated data, and the parity that will send integrated data and even-odd generator generation sends to the reception bus.
Reception controller in the second packet bus controller comprises that is connected to a transmission bus link that sends bus, is used to receive from one first and second master controller be sent to the integrated data that sends bus; One is used for and will receives the reception memorizer link that controller is connected to reception memorizer; And be connected the parity checker that sends between bus link and the reception memorizer link, be used for also the integrated data of verification parity is outputed to the link of reception memorizer by the integrated data verification parity that sends the reception of bus link.According to the parity error check to receiving block data, parity checker requires to send the bus link and resends integrated data; Wherein under the request that resends of parity checker, described transmission bus link requires one first and second master controller to resend integrated data.
The following detailed of carrying out in conjunction with the drawings, above and other objects of the present invention, characteristic and advantage will be more obvious, wherein:
Fig. 1 is the block scheme of expression packet data communication system according to an embodiment of the invention;
Fig. 2 is the block scheme of the packet bus controller in the master controller of presentation graphs 1;
Fig. 3 is the block scheme of the packet bus controller in the slave controller of presentation graphs 1;
Fig. 4 is the block scheme of the transmit control device (203) in the packet bus controller of presentation graphs 2;
Fig. 5 is the block scheme of the reception controller (206) in the packet bus controller of presentation graphs 2;
Fig. 6 is the block scheme of the transmit control device (303) in the packet bus controller of presentation graphs 3;
Fig. 7 is the block scheme of the reception controller (306) in the packet bus controller of presentation graphs 3;
Fig. 8 is the process flow diagram that expression is used for integrated data is sent to from master controller the process of slave controller;
Fig. 9 is the timing diagram that does not have integrated data data communication system under the situation of parity error in the integrated data process of transmitting;
Figure 10 is the timing diagram that integrated data data communication system under the situation of parity error is arranged in the integrated data process of transmitting;
Figure 11 is the timing diagram that does not have integrated data data communication system under the situation of parity error in the integrated data receiving course; With
Figure 12 is the timing diagram that integrated data data communication system under the situation of parity error is arranged in the integrated data process of transmitting.
A preferred embodiment of the present invention is described below with reference to accompanying drawings.These unnecessary details in the following description, will not be described in detail well-known function or structure, because will hinder the present invention.
The symbol that uses in packet data communication system according to the present invention defines in table 1.Table 1
| Symbol | Implication |
| Tx | Send |
| Rx | Receive |
| -Addr | The address |
| -Data | Data |
| -Enb * | Enable |
| -SOP | The grouping beginning |
| -EOP | Grouping finishes |
| -Prty | Parity |
| -Pvalid * | Grouping effectively |
| -PrtyOK | Parity is correct |
| -Pay | It is available to divide into groups |
| -Full | Full |
| -deject | Empty |
| Busreq * | Bus request |
| Busgnt * | Bus is granted |
| Busbusy * | Bus is busy |
| S- | Self |
| O- | Other |
In table 1, after wear asterisk (
*) the symbolic representation low level effective, it triggers when signal is in low level, ineffective with the representative high level of asterisk, it triggers when signal is in high level.
Fig. 1 is the block scheme of expression packet data communication system according to an embodiment of the invention.With reference to Fig. 1, packet communication system comprises two master controllers (MC1) 101 of dual structure and (MC2) 102, n slave controller (SC1-SCn) 103-105, a transmission bus 10 that is used between controller 101-105, providing the integrated data transmit path, and be used between controller 101-105, providing the reception bus 20 of integrated data RX path.Here, when two master controllers 101 and 102 send to integrated data among the slave controller 103-105 any, send bus 10 transmit path is provided.When any receiving block data from slave controller 102-105 of two master controllers 101 and 102, receive bus 20 RX path is provided.
In the present embodiment, send bus 10 and transmit 16 bits transmission integrated data TxData, a signal TxSOP who is used to show the beginning that sends integrated data, a parity signal TxPrty who is used to send integrated data, the ongoing signal TxEnb of transmission that is used to show integrated data
*(m+1) bit signal TxAddr that is used to show the slave controller of the purpose that transmits as integrated data, a n bit signal TxFull who is used to show that current slave controller whether can receiving block data, with the signal TxPVaild and the TxPrtyOK that show the parity checking result, wherein according to the title of the integrated data that receives, the parity of the integrated data that the slave controller inspection receives also sends parity checking consequential signal TxPVaild and TxPrtyOK to master controller.
Receive bus 20 and transmit 16 bit receiving block data RxData, signal RxSOP who is used to show the beginning of receiving block data, one are used to signal RxEOP, the parity signal RxPrty that is used for receiving block data, the ongoing signal RxDVaild of reception that is used to show integrated data of showing that receiving block data finishes
*, one be used to trigger the signal RxEnb that slave controller 103-105 transmits integrated data
*, (m+1) bit signal RxAddr that is used to show the slave controller that will transmit integrated data, one be used to show whether current slave controller has n bit signal RxPav that integrated data will transmit and signal RxPVaild and the RxPrtyOK that shows the parity checking result, wherein according to the title of the integrated data that receives, the parity of the integrated data that the master controller inspection receives also sends parity checking consequential signal TxPVaild and TxPrtyOK to slave controller.
In addition, between master controller 101 and master controller 102, also transmit a plurality of signals.These signals comprise a signal Obdeject, and it shows that the plate of the master controller that is used for other group is separated from packet communication system; A signal OTxBusreq
*, it shows that the master controller of other group requires to use (request path just) to send bus 10; A signal ORxBusreq
*, it shows that the master controller of other group requires to use reception bus 20; A signal OTxBusgnt
*, it shows that the master controller of other group obtains to send the right to use of bus 10 (just, granting path); A signal ORxBusgnt
*, it shows that the master controller of other group obtains to receive the right to use of bus 20, a signal OTxBusbusy
*, it shows that current use of master controller of other group sends bus 10; With a signal ORxBusbusy
*, it shows that current use of other group master controller receives bus 20.
Fig. 2 has represented the packet bus controller of preparation in the master controller 101 and 102 of Fig. 1.With reference to figure 2, the data that transmit control device 203 controls send on the bus 10 send.One sends bus processor 204 and handles the right to use that sends bus 10 between two master controllers 101 and 102.Transmission storer 202 temporary transient storages will send to the integrated data of slave controller.A reception controller 206 is controlled the data transmission that receives on the buses 20.One receives bus processor 207 and handles the right to use that receives bus 20 between two master controllers 101 and 102.The integrated data that reception memorizer 205 temporary transient storages receive from slave controller.
Fig. 3 has represented the packet bus controller prepared in the slave controller 103-105 of Fig. 1.Handle by master controller by sending control signal and the data that bus 10 transmits with reference to 3, one reception controllers of figure 306.Reception memorizer 305 temporary transient storages are by receiving the integrated data that controller 306 receives.A transmit control device 303 sends the data to master controller as to from the response of master controller by the control signal of reception bus 20 receptions by receiving bus 20.Transmission storer 302 temporary transient storages will send to the integrated data of master controller.
Fig. 4 has represented the transmit control device 203 in the packet bus controller of Fig. 2.With reference to figure 4, control and the transmission processor link 401 that is connected that sends bus processor 204, transmit a bus request signal STxBusreq, be used for using transmission bus 10 to sending bus processor 204 requests, select a purpose from storer, granting signal STxBusgnt according to the bus that receives, obtain to send under the usufructuary situation of bus 10, integrated data is sent to this purpose from storer from sending bus processor 204, and ask a transmission storer link 402 and a transmission bus link 404 to transmit integrated data.Control sends the transmission storer link 402 of the connection of storer 202, under the control that sends processor link 401 from sending storer 202 reading in packet data.The 16 bit groupings data generation parity that even-odd generator 403 reads for sending storer link 402.Be connected to the transmission bus link 404 that sends bus 10, integrated data and parity are sent to transmission bus 10 from even-odd generator 403.
Fig. 5 has represented the reception controller 206 in the packet bus controller of Fig. 2.With reference to figure 5, the receiving processor link 501 that control is connected with reception bus processor 207, transmit a bus request signal SRxBusreq, be used for using reception bus 20 to receiving bus processor 207 requests, select a resource from storer, granting signal SRxBusgnt according to the bus that receives, obtain to receive under the usufructuary situation of bus 20, integrated data is sent to this resource from storer from receiving bus processor 207, and ask a transmission bus link 504 to come receiving block data.Control and the reception bus link 504 that is connected that receives bus 20, the slave controller that request is selected transmit integrated data and receive the integrated data that transmits by receiving bus 20 under the control of receiving processor link 501.Further, when parity checker 503 detected a parity error, the slave controller that receives the 504 request selections of bus link resend integrated data.Be connected the parity checker 503 that receives between bus link 504 and the reception memorizer link 502, will report to for the parity checking result of the integrated data that receives and receive bus link 504., when parity checker 503 does not detect parity error, control reception memorizer link 502 store packet data that are connected with reception memorizer 205.
Fig. 6 has represented the transmit control device 303 in the packet bus controller of Fig. 3.Be connected to the reception bus link 601 that receives bus 20 with reference to 6, one in figure, as to by receiving the response of the control signal that bus 20 receives from master controller, be sent to and receive bus 20 temporarily being stored in the integrated data that sends in the storer 302.Control and the transmission storer link 602 that is connected that sends storer 302, under the control that receives bus link 601 from sending storer 302 reading in packet data.One is connected the even-odd generator 603 that receives between bus link 601 and the transmission storer link 602, and the integrated data that reads for transmission storer link 602 produces parity and it is outputed to reception bus link 601 together with integrated data.
Fig. 7 has represented the reception controller 306 in the packet bus controller of Fig. 3.Be connected to the transmission bus link 701 that sends bus 10 with reference to 7, one in figure, as to by sending the response of the control signal that bus 10 receives from master controller, receiving block data.Further, when parity checker 703 detects a parity error, send bus link 701 request master controllers and resend integrated data by sending bus 10.Be connected the parity checker 703 that sends between bus link 701 and the reception memorizer link 702, the parity of the integrated data that verification reception memorizer link 702 receives, and the parity checking result outputed to send bus link 701.The control and the reception memorizer link 702 that is connected of reception memorizer 305 when parity checker 703 does not detect parity error, are stored in integrated data in the reception memorizer 30.
As mentioned above, send and receiving block data by independently sending bus 10 and receiving bus 20 respectively according to packet data communication system of the present invention.Because bus 10 and 20 is independently of one another, transmit operation is not disturbed mutually with receiving operation, and vice versa, therefore can improve transmission of packet data speed.The master controller 101 in the dual structure and 102 is at their all time spent (just, when the plate that comprises master controller not when system separates) shared inputs but (just, to the transmission of integrated data and receive operation).Yet, but when having only a master controller time spent (just, when the plate that comprises another group controller by when system separates), available master controller is handled whole transmissions of integrated data and is received operation.
Now, with reference to accompanying drawing, will transmission and the reception according to integrated data of the present invention be described.
Transmit operation
In order to send integrated data, the transmit control device 203 in the master controller outputs to bus request signal STxBusreq and sends bus processor 204.Send bus processor 204 though each master controller all has, but when two plates time spent all, two send and have only one can operate and another can not be operated in the bus processors.According to the process flow diagram of Fig. 8, send the master controller that bus processor 204 selects will send integrated data next time.
With reference to figure 8,, send bus processor 204 and detect another group master controller whether available (step S801) according to signal OBdeject.If another group master controller is unavailable, to grant signal Sbusgnt be " 0 " by triggering bus to send bus processor 204, makes the transmit control device 203 of self master controller can control transmission bus 10 (step S807).Yet, if the master controller of another group can be used, detect and whether send bus processor self as sending bus processor 204, this means that original state self master controller in system is set to master controller (step S802).Whether if send bus controller self not as sending bus processor 204, it is available then to detect another group master controller.Yet, will detect which the current integrated data (step S803) that transmitting in two master controllers as sending bus processor 204 if send bus processor self.After this, detect whether receive the bus request signal (step S804 and S805) that sends from the current master controller that does not transmit integrated data.In step S803, the value S of a register in master controller is set to 1, and (just, in the time of S=1), master controller transmits integrated data.If receive bus request signal from the current master controller that does not transmit integrated data, the right to use that then sends bus is granted this master controller (step S806 and S807) that will transmit next integrated data.If not receiving bus request signal, whether then detect from the master controller of current transmission integrated data and receive bus request signal (step S804 and S805) from the current master controller that does not transmit integrated data.Here, when receiving bus request signal, the right to use of bus is granted this master controller (step S806 and S807).After the right to use of granting bus, detect whether receive the bus busy signal Busbusy of level for " 1 " from granting the usufructuary master controller of bus
*(step S808 and S809).When receiving the bus busy signal Busbusy of level for " 1 "
*The time, bus is granted signal Busgnt
*Be set to " 1 " (step S810 and S811).After this, repeating this process (step S810 and S811) selects to be granted the usufructuary master controller of bus next time.
With the usufructuary master controller of top method acquisition bus, at first select to transmit the purpose slave controller of integrated data.In selecting the purpose slave controller, master controller uses the value of a register that obtains by the signal PacketArrive that receives from the upper strata, shows whether the integrated data that will send to corresponding slave controller is arranged, and uses signal TxFull
*Value show whether reception memorizer in the corresponding slave controller has the space of store packet data.When the result with operation of two values was " 1 ", integrated data was sent to corresponding slave controller.End value at a plurality of slave controllers is under the situation of " 1 ", selects to transmit the purpose slave controller of integrated data on the round-robin basis.
In case selected to transmit the purpose slave controller of integrated data with top method, then obtain the slave controller that the usufructuary master controller of bus sends integrated data to according to the timing diagram of Fig. 9 and Figure 10 selection, when describing the timing diagram of Fig. 9 and Figure 10, suppose that integrated data is sent to the title that the 5th slave controller SC5 (" 4 ") and integrated data have 2 bytes (or 4 bits).
Fig. 9 has represented normally to be sent to from master controller in integrated data the timing diagram of packet data communication system under the situation of slave controller, and Figure 10 has represented the timing diagram of packet data communication system under the situation that again integrated data is sent to slave controller because parity error takes place from master controller.
At first, transmit control device 203 in the packet bus controller of master controller, after the transmission bus processor has been selected to transmit the purpose slave controller of integrated data, on signal TxAddr, make this slave controller perform the preparation of receiving block data in the address of time clock time 2 input purpose slave controllers.At this moment, after through a time clock, transmit control device trigger pip TxEnb
*Be " 0 " that the first integrated data title data RO is input to TxData, and trigger pip TxSOP is " 1 ", trigger pip TxEOP is not " 0 ", and is parity values of TxData input on TxPrty, thereby begins to send integrated data.
After sending packet header (in the time clock time 5), master controller is waited for from what slave controller sent and is used for showing the signal that whether resends packet header.Slave controller pilot signal TxAddr comes to prepare receiving block data according to himself the address that receives, and as signal TxEnb
*Receiving block data when being triggered " 0 ".Then, slave controller after the reception of finishing integrated data fully, the parity of verification title.Here, if do not detect parity error, slave controller trigger pip TxPValid then
*For " 0 " and signal TxPrtyOK for " 1 " and then send a signal to master controller, as shown in Figure 9.On the contrary, yet, if detect parity error, slave controller trigger pip TxPValid
*For " 0 " and not trigger pip TxPrtyOK be " 0 " and then send a signal to master controller, as shown in figure 10.Wait for parity checking result's master controller, resend title according to the parity error signal that receives, as shown in figure 10.
If the parity error to packet header takes place repeatedly, master controller stops integrated data being sent to slave controller, and (just with this situation, parity error takes place) report to the transmission bus processor, therefore prevent to send this integrated data to slave controller and even with this situation report to the upper strata.
If parity error does not take place as shown in Figure 9, master controller trigger pip TxEnb* is " 0 ", and remaining integrated data is sent to slave controller by sending bus 10.After the last data of grouping sent, master controller trigger pip TxEOP notified the transmission of slave controller integrated data for " 1 " and finishes, and is the transmit operation of integrated data next time, will be the bus busy signal Busbusy of " 1 "
*Output to the transmission bus processor.
Receive operation
According to process shown in Figure 8, even receiving in the operation by the integrated data that receives bus 20, send bus processor 204 select next time with the master controller of receiving block data and with the result report to master controller make receive controller 206 can be from the slave controller receiving block data.
The usufructuary master controller that to receive bus 20 receives the signal RxPav that whether shows from corresponding slave controller receiving block data, and analyzes the signal RxPav that receives and select to send the slave controller of integrated data next time.Here, as in transmit operation, on the round-robin basis, select to send the slave controller of integrated data.That is, at first send the slave controller show the signal RxPav that integrated data will send, sent the signal RxPav that the next slave controller of the slave controller of integrated data sends, be selected as the slave controller that this sends integrated data by detecting from last time.After having selected to send the slave controller of integrated data, master controller is according to the timing diagram receiving block data of Figure 11 and 12.When describing the timing diagram of Figure 11 and 12, the slave controller of supposing to send integrated data is the 3rd slave controller (" 2 ") in the 3rd plate.Figure 11 has represented the timing diagram of packet data communication system under the situation that parity error does not take place, and Figure 12 has represented the timing diagram of packet data communication system under the situation that parity error takes place.
At first, reception controller 206 in the master controller, address according to the slave controller that will send integrated data that receives from reception bus processor 207, trigger pip RxEnb is " 0 ", and sends it to slave controller according to signal RxAddr for the slave controller Input Address that will send integrated data of selection and by receiving bus 20.According to judging that the address of input on signal RxAddr is the address of self, slave controller is trigger pip RxDValid at this moment
*Be " 0 ", first packet header of input on the RxData, trigger pip RxSOP be " 1 ", trigger pip RxEOP is not " 0 " and be that RxData imports a parity values on signal RxPrty, thereby begins to send integrated data.
After the transmission of finishing packet header, slave controller is waited for from the parity checking result of the packet header of master controller transmission.As signal RxDValid
*Master controller receiving block data when triggering to " 0 ".After receiving packet header, the parity of the packet header that the master controller verification receives, and use signal RxPValid
*With RxPrtOK the parity checking result is sent to slave controller.Here, in when, parity error not taking place when, master controller trigger pip RxPValid
*For " 0 " and signal RxprtyOK send to slave controller for " 1 " and with them.Yet, when parity error takes place when, master controller trigger pip RxPValid
*For " 0 " and not trigger pip RxprtyOK be " 0 ".According to the demonstration parity checking result's who receives signal PxPValid and PxPrtOK, when detecting parity error, slave controller resends packet header as shown in figure 12.On the contrary, however when not detecting parity error, slave controller sends remaining integrated data as shown in figure 11.When sending the final data of integrated data, slave controller be sent as " 1 " thus the transmission of signal RxEOP notice master controller integrated data finish.Master controller then will be the signal RxBusbusy of " 1 " after finishing receiving block data
*Send to and receive bus processor 207, thereby select the master controller of next receiving block data.
As mentioned above, will send bus according to packet data communication system of the present invention and separate independently, and therefore can transmit lot of data with very high speed with the reception bus.Further, use the master controller with dual structure, even when a master controller is unavailable, this packet data communication system also can normal running.In addition, system carries out parity checking to integrated data, thereby has increased the transmission of packet data reliability.
Though by providing and described the present invention, those skilled in the art will appreciate that and under the prerequisite of the spirit and scope that do not break away from the appended claims, can make various variations in form and details with reference to a preferred embodiment at this.
Claims (20)
1. comprise a plurality of packet data communication systems that are used to send with the controller of receiving block data, comprising:
First and second master controllers;
A plurality of slave controllers;
Be connected the transmission bus between master controller and the slave controller, it provides transmission path for the integrated data that is sent to a slave controller from a master controller; With
Be connected between master controller and the slave controller, with the reception bus that the transmission bus is separated, it provides RX path for a master controller from a slave controller receiving block data;
But wherein ought have only a master controller time spent, available master controller carries out the transmission of integrated data alone and receives operation, but and when two master controllers time spent all, two master controllers are shared the transmission of integrated data and received operation.
2. according to the packet data communication system of claim 1, wherein each first and second master controller comprises a packet bus controller, and it comprises:
One sends bus processor, and it is used for handling the right to use of the transmission bus between first and second master controllers;
A transmission storer that is used for the integrated data of temporary transient storage transmission;
A transmit control device, it is used for selecting bus will send integrated data to send first slave controller to by sending out;
One receives bus processor, and it is used for handling the right to use of the reception bus between first and second master controllers;
A reception controller, it is used to receive the integrated data that sends to the reception bus from second slave controller; With
The reception memorizer of the integrated data of a temporary transient storage reception.
3. according to the packet data communication system of claim 2, wherein said transmit control device sends one and sends bus request signal to sending bus processor, grant the right to use that it sends bus if send bus processor, then from send storer, read the transmission integrated data, and the transmission integrated data that will read sends to the transmission bus.
4. according to the packet data communication system of claim 3, wherein said transmit control device comprises:
One is used for transmit control device is connected to the transmission storer link that sends storer;
One is used for transmit control device is connected to the transmission bus link that sends bus;
One is connected the even-odd generator that sends between storer link and the transmission bus link, is used to produce a parity; With
A transmit control device link, it is used to control the connection between transmit control device and the transmission bus controller, if and to send the right to use of bus, then the bus link will send transmission integrated data in the storer link and the parity of even-odd generator generation sends to the transmission bus by sending.
5. according to the packet data communication system of claim 2, wherein
Described reception controller sends one and receives bus request signal to receiving bus controller, grant the right to use that it receives bus if receive bus controller, then receive the receiving block data on the bus, and the integrated data that receives is stored in the reception memorizer.
6. according to the packet data communication system of claim 5, wherein said reception controller comprises:
One is used for and will receives the reception memorizer link that controller is connected to reception memorizer;
One is used for being connected to the reception bus link that receives bus with receiving controller;
A parity checker that is connected between reception memorizer link and the reception bus link is used for carrying out the parity error verification by the receiving block data that receives the reception of bus link; With
A receiving processor link, be used to control the connection that receives between controller and the reception bus processor, if and the right to use of acquisition reception bus, then the transmission integrated data that will receive on the bus by parity checker and reception memorizer link is stored in the reception memorizer.
7. according to the packet data communication system of claim 6, wherein basis is to the parity error check of receiving block data, and parity checker requires to receive the bus link and resends integrated data; Wherein under the request that resends of parity checker, described reception bus link requires second slave controller to resend integrated data.
8. according to the packet data communication system of claim 1, wherein each slave controller comprises a packet bus controller, and it comprises:
Be used for the transmission storer that temporary transient storage sends integrated data;
One is connected to the transmit control device that receives bus, is used to respond the control signal of sending from one first and second master controller, will send integrated data and send to the reception bus;
One is connected to the reception controller that sends bus, is used to respond the control signal of sending from one first and second master controller, receives by sending the integrated data that bus sends from one first and second master controller; With
A reception memorizer is used for temporary transient storage by receiving the integrated data that controller receives.
9. packet data communication system according to Claim 8, wherein said transmit control device comprises:
One is used for transmit control device is connected to the transmission storer link that sends storer and read the transmission integrated data from the transmission storer;
An even-odd generator is used to send the transmission integrated data generation parity that the storer link reads; With
One receives the bus link, be used to control the connection between transmit control device and the reception bus, and the control signal sent from one first and second master controller of response, make to send the storer link and can read the transmission integrated data, and the parity that will send integrated data and even-odd generator generation is dealt into the reception bus.
10. packet data communication system according to Claim 8, wherein said reception controller comprises:
One is connected to the transmission bus link that sends bus, is used to receive from one first and second master controller send to the integrated data that sends bus;
One is used for and will receives the reception memorizer link that controller is connected to reception memorizer; With
Be connected the parity checker that sends between bus link and the reception memorizer link, be used for also the integrated data of verification parity being outputed to the reception memorizer link by the integrated data verification parity that sends the reception of bus link.
11. according to the packet data communication system of claim 10, wherein basis is to the parity error check of receiving block data, parity checker requires to send the bus link and resends integrated data; Wherein under the request that resends of parity checker, described transmission bus link requires one first and second master controller to resend integrated data.
12. one kind is used for integrated data is sent to a plurality of methods from one of the control device from one first and second master controller in packet data communication system, wherein master controller and slave controller interconnect by transmission bus independent of each other and reception bus in packet data communication system, and the cloth that this method comprises is suddenly:
(a) judge whether first and second master controllers are available;
(b) but in first and second master controllers, have only a time spent, grant the right to use that available master controller sends bus;
(c) but when first and second master controllers time spent all, a controller that whether detects from current first and second master controllers that do not send integrated data receives the transmission bus request signal, if and received the transmission bus request signal from the current master controller that does not send integrated data, the right to use that then will send bus would be granted the current described master controller that does not transmit integrated data.
(d) if do not receive the transmission bus request signal from the current master controller that does not send integrated data, whether then detect from the current master controller that is sending integrated data and receive the transmission bus request signal, if and from the current master controller that is sending integrated data, received the transmission bus request signal, the right to use that then will send bus would be granted from it and is received the master controller that sends bus request signal.
(e) in sending the usufructuary master controller of bus, the slave controller that selection will receiving block data; And
(f) obtaining to send in the usufructuary master controller of bus, integrated data is being sent to the slave controller of selection by the transmission bus.
13., wherein detect first and second master controllers and whether be contained on the corresponding plate, thereby select first and second master controllers whether available in described step (a) according to the method for claim 12.
14. method according to claim 12, wherein at described step (e), by grant to send the usufructuary master controller of bus select will receiving block data slave controller, and from the slave controller of selecting, select a slave controller with the storer that is used for receiving block data, as the slave controller of receiving block data.
15. method according to claim 14, wherein at described step (e), when having a plurality of slave controller with the storer that is used for receiving block data, the usufructuary master controller of being granted the transmission bus on the round-robin basis, select will receiving block data slave controller.
16. according to the method for claim 12, the step that wherein said step (f) comprises is:
In grant being sent the usufructuary master controller of bus, the slave controller that produces a packet header and parity values and the packet header and the parity values of generation sent to selection;
In the slave controller of described selection, receive packet header and parity values, be packet header verification parity error, and the parity checking result is sent to master controller;
When parity error takes place, packet header is resend slave controller from master controller; And
When parity error not taking place, integrated data is sent to slave controller from master controller.
17. one kind in packet data communication system, in one first and second master controller, be used for from the method for a receiving block data of a plurality of slave controllers, wherein master controller and slave controller interconnect by transmission bus independent of each other and reception bus in packet data communication system, and what this method comprised is arranged as:
(a) judge whether first and second master controllers are available;
(b) but in first and second master controllers, have only a time spent, grant the right to use that available master controller receives bus;
(c) but when first and second master controllers time spent all, a controller that whether detects from current first and second master controllers that do not have a receiving block data receives the reception bus request signal, if and do not have the master controller of receiving block data to receive the reception bus request signal from current, the right to use that then will receive bus would be granted the current described master controller that does not have receiving block data.
(d) if from the current master controller that does not have a receiving block data, do not receive the reception bus request signal, whether then detect from the current reception bus request signal that just the master controller of receiving block data, receiving, if and from the current reception bus request signal that just receiving the master controller of receiving block data, the right to use that then will receive bus is granted the master controller that receives the reception bus request signal from it.
(e) in obtaining the usufructuary master controller of reception bus, select a slave controller of having stored integrated data as the slave controller that will send integrated data; And
(f) obtaining to receive in the usufructuary master controller of bus, from the slave controller of selecting, pass through to receive the bus receiving block data.
18., wherein detect first and second master controllers and whether be contained on the corresponding plate, thereby select first and second master controllers whether available in described step (a) according to the method for claim 17.
19.,, granted the usufructuary master controller of reception bus and on the round-robin basis, judged whether to exist the slave controller that will send integrated data wherein at described step (e) according to the method for claim 17.
20. according to the method for claim 17, the step that wherein said step (f) comprises is:
An address signal is sent to the slave controller of selecting to be used for sending integrated data from obtaining to receive the usufructuary master controller of bus;
In slave controller, send packet header and parity values according to the address signal that receives;
In master controller, receive packet header and parity values, to packet header verification parity error, and the parity checking result sent to slave controller;
When parity error takes place when, packet header is resend master controller from slave controller, and
When parity error not taking place, integrated data is sent to master controller from slave controller.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019970081472A KR100285953B1 (en) | 1997-12-31 | 1997-12-31 | Packet bus and method for transmitting packet data using the packet bus |
| KR81472/1997 | 1997-12-31 | ||
| KR81472/97 | 1997-12-31 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1231445A true CN1231445A (en) | 1999-10-13 |
| CN1124549C CN1124549C (en) | 2003-10-15 |
Family
ID=19530583
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN98111658A Expired - Fee Related CN1124549C (en) | 1997-12-31 | 1998-12-31 | Grouped data communication between multiple controllers |
Country Status (2)
| Country | Link |
|---|---|
| KR (1) | KR100285953B1 (en) |
| CN (1) | CN1124549C (en) |
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461146C (en) * | 2004-01-22 | 2009-02-11 | 高通股份有限公司 | Two channel bus structure to support address information, data, and transfer qualifiers |
| CN100519210C (en) * | 2005-06-29 | 2009-07-29 | 三星电子株式会社 | Image forming apparatus and a communication method with trays thereof |
| CN102651705A (en) * | 2011-02-24 | 2012-08-29 | Ls产电株式会社 | Gateway apparatus for substation automation system |
| CN103744811A (en) * | 2013-12-27 | 2014-04-23 | 华中科技大学 | Serial data transmission system and method |
| CN109100978A (en) * | 2018-09-20 | 2018-12-28 | 中航锂电技术研究院有限公司 | A kind of setting of battery management system address and method of calibration |
| CN114047714A (en) * | 2021-09-27 | 2022-02-15 | 中天海洋***有限公司 | Multiprocessor cooperative control system and method |
-
1997
- 1997-12-31 KR KR1019970081472A patent/KR100285953B1/en not_active IP Right Cessation
-
1998
- 1998-12-31 CN CN98111658A patent/CN1124549C/en not_active Expired - Fee Related
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100461146C (en) * | 2004-01-22 | 2009-02-11 | 高通股份有限公司 | Two channel bus structure to support address information, data, and transfer qualifiers |
| US8879101B2 (en) | 2005-06-29 | 2014-11-04 | Samsung Electronics Co., Ltd. | Image forming apparatus and a communication method with trays thereof |
| CN100519210C (en) * | 2005-06-29 | 2009-07-29 | 三星电子株式会社 | Image forming apparatus and a communication method with trays thereof |
| US8184314B2 (en) | 2005-06-29 | 2012-05-22 | Samsung Electronics Co., Ltd. | Image forming apparatus and a communication method with trays thereof |
| US9205683B2 (en) | 2005-06-29 | 2015-12-08 | Samsung Electronics Co., Ltd. | Image forming apparatus and a communication method with trays thereof |
| CN102651705A (en) * | 2011-02-24 | 2012-08-29 | Ls产电株式会社 | Gateway apparatus for substation automation system |
| US8799551B2 (en) | 2011-02-24 | 2014-08-05 | Lsis Co., Ltd. | Gateway apparatus for substation automation system |
| CN102651705B (en) * | 2011-02-24 | 2015-04-01 | Ls产电株式会社 | Gateway apparatus for substation automation system |
| CN103744811A (en) * | 2013-12-27 | 2014-04-23 | 华中科技大学 | Serial data transmission system and method |
| CN109100978A (en) * | 2018-09-20 | 2018-12-28 | 中航锂电技术研究院有限公司 | A kind of setting of battery management system address and method of calibration |
| CN109100978B (en) * | 2018-09-20 | 2021-07-30 | 中航锂电技术研究院有限公司 | Battery management system address setting and checking method |
| CN114047714A (en) * | 2021-09-27 | 2022-02-15 | 中天海洋***有限公司 | Multiprocessor cooperative control system and method |
| CN114047714B (en) * | 2021-09-27 | 2024-06-25 | 中天海洋***有限公司 | Multiprocessor cooperative control system and method |
Also Published As
| Publication number | Publication date |
|---|---|
| CN1124549C (en) | 2003-10-15 |
| KR19990061216A (en) | 1999-07-26 |
| KR100285953B1 (en) | 2001-04-16 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN1212574C (en) | End node partitioning using local identifiers | |
| JP2536915B2 (en) | A computer mutual coupling coupler for use in a data processor cluster. | |
| CN100487685C (en) | Method and apparatus for sending data from multiple sources over a communications bus | |
| CN1703881A (en) | Integrated circuit and method for establishing affair | |
| CN1195813A (en) | System of reporting errors by hardward element of distributed computer system | |
| Luttik | Description and formal specification of the link layer of P1394 | |
| CN1075580A (en) | The frame pocket transmission and the reception of parallel/serial | |
| CN1010264B (en) | Local area network special function frames | |
| WO2006045015A2 (en) | Inspection system with data acquisition system interconnect protocol | |
| WO2010103564A1 (en) | Transmission/reception device, transmission device, reception device, and data transmission/reception method | |
| CN1118029C (en) | System and method of flow control for high speed bus | |
| CN1054344A (en) | The detection method of Frame Alignment Word and equipment in the data flow | |
| JPH04242463A (en) | State-change informing mechanism and method in data processing input/output system | |
| WO1997032254A1 (en) | System and method for bus contention resolution | |
| CN1279790A (en) | Fast 16-bit transaction I/O bus | |
| CN1773444A (en) | Method and system for synchronizing logical systems | |
| CN1124549C (en) | Grouped data communication between multiple controllers | |
| CN1260654C (en) | Method of reporting errors by hardward element of distributed computer system | |
| CN1751305A (en) | Communications in a processor array | |
| EP0291671A2 (en) | Apparatus and method for deferred parity checking of control signals across a bidirectional data transmission interface | |
| CN115269221A (en) | FPGA hardware abstraction layer design method and system based on shared memory mechanism | |
| EP0353249A1 (en) | Parallel networking architecture | |
| CN1262484A (en) | Bus, redundancy bus system for bus and method for internal transmission information | |
| CN1991811A (en) | Master module, function module, electronic device and identification data setting method thereof | |
| CN1227869C (en) | Arbitration scheme for serial interface |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| C19 | Lapse of patent right due to non-payment of the annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |