CN1230779A - Semiconductor device and method for fabricating thereof - Google Patents
Semiconductor device and method for fabricating thereof Download PDFInfo
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- CN1230779A CN1230779A CN99103428A CN99103428A CN1230779A CN 1230779 A CN1230779 A CN 1230779A CN 99103428 A CN99103428 A CN 99103428A CN 99103428 A CN99103428 A CN 99103428A CN 1230779 A CN1230779 A CN 1230779A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000000034 method Methods 0.000 title claims abstract description 17
- 239000011229 interlayer Substances 0.000 claims abstract description 82
- 239000010410 layer Substances 0.000 claims abstract description 71
- 239000002184 metal Substances 0.000 claims description 23
- 229910052751 metal Inorganic materials 0.000 claims description 23
- 239000000758 substrate Substances 0.000 claims description 19
- 238000009792 diffusion process Methods 0.000 claims description 13
- 238000000137 annealing Methods 0.000 claims description 11
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 9
- 229910052760 oxygen Inorganic materials 0.000 claims description 9
- 239000001301 oxygen Substances 0.000 claims description 9
- 238000004519 manufacturing process Methods 0.000 claims description 7
- 239000003990 capacitor Substances 0.000 abstract description 22
- 230000007850 degeneration Effects 0.000 abstract 1
- 230000010287 polarization Effects 0.000 description 31
- 230000006870 function Effects 0.000 description 8
- 239000000463 material Substances 0.000 description 8
- 238000000151 deposition Methods 0.000 description 7
- 230000008021 deposition Effects 0.000 description 7
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 6
- 230000008901 benefit Effects 0.000 description 5
- 230000007797 corrosion Effects 0.000 description 5
- 238000005260 corrosion Methods 0.000 description 5
- 230000006835 compression Effects 0.000 description 4
- 238000007906 compression Methods 0.000 description 4
- 230000008569 process Effects 0.000 description 4
- 238000003860 storage Methods 0.000 description 4
- 208000023414 familial retinal arterial macroaneurysm Diseases 0.000 description 3
- 230000004888 barrier function Effects 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 2
- 238000009413 insulation Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 230000009467 reduction Effects 0.000 description 2
- 108010032595 Antibody Binding Sites Proteins 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BOTDANWDWHJENH-UHFFFAOYSA-N Tetraethyl orthosilicate Chemical compound CCO[Si](OCC)(OCC)OCC BOTDANWDWHJENH-UHFFFAOYSA-N 0.000 description 1
- 238000001505 atmospheric-pressure chemical vapour deposition Methods 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 238000011112 process operation Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 230000003068 static effect Effects 0.000 description 1
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
- H01L28/57—Capacitors with a dielectric comprising a perovskite structure material comprising a barrier layer to prevent diffusion of hydrogen or oxygen
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/01—Manufacture or treatment
- H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
- H10B12/03—Making the capacitor or connections thereto
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- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B53/00—Ferroelectric RAM [FeRAM] devices comprising ferroelectric memory capacitors
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Abstract
A semiconductor device and a method for fabricating thereof are disclosed in the invention, without degeneration of ferroelectric capacitor property caused by overlaying interlayer insulating layer. The novel method can form an interlayer insulating layer on a capacitor to have a tensile stress relative to the capacitor. The interlayer insulating layer can be an oxide layer in low temperature, preferably one of PE-TEOS, USG, ECR-OX layers.
Description
The present invention relates to semiconductor device, particularly ferroelectric condenser and manufacture method thereof.
The most information that the modern data processing system requirements is stored in its memory is can be random-access to guarantee these information of fast access.Because the high speed operation of the memory that in semiconductor technology, carries out, so developed random access memory (" RAM "), wherein the small number of binary information storage is in single memory cell, it only can comprise a transistor and relevant capacitor, and a large amount of storage elements is combined becomes array.Utilize the dielectric RAMs that is suitable for usually of typical integrated-circuit capacitor to comprise dynamic ram s (" DRAMs ") and static RAM (SRAM) s (" SRAMs ").
The DRAM memory cell is in the capacitor of data storing in the substrate that is formed on the IC semiconductor material.Because the logic level of being determined by electric charge is stored in the capacitor rather than in the current status of bistable logic device,, and therefore need be updated periodically in order to protect memory contents so electric charge is tending towards dissipating.
In conventional single transistor DRAM memory cell, the electric charge that is stored in the memory cell capacitor is coupled in the storage bit line by the source/leakage path of access transistor is selected.The grid of access transistor also can be coupled to word line then.By the conducting access transistor, the electric charge that is stored in the capacitor is coupled to bit line by source/leakage path, it is generally compared with another charge reference more there, for example dummy argument memory cell or paratope line, this is the state for the memory cell that can determine to be represented by the electric charge that is stored in the capacitor.
Recently, ferroelectric material is as the dielectric in the memory cell capacitor.Ferroelectric material shows as intrinsic high-k.Use is used for the RAMs of the ferroelectric condenser of memory cell, and promptly FRAMs also shows as non-volatile remarkable advantage.FRAMs's is non-volatile by means of following true the realization: ferroelectric condenser comprises a pair of capacitor plate, between them, have ferroelectric material, it has two different stable polarized states, and this is to define with respect to the hysteresis loop that applies voltage with drawing polarization.By when voltage puts on ferroelectric condenser, measuring the electric charge that flows, can determine the polarized state of ferroelectric material.By arbitrarily logic level " zero " being distributed to a polarized state and logic " " is distributed to opposite polarized state, ferroelectric condenser can be used for storing binary message at the RAM storage array.Even the obvious advantage of nonvolatile memory is to flow to the power interruptions of device or remove, data still can continue to be stored in the memory cell the inside.
Fig. 1 is the polarization charge (Q: μ C/cm in the expression ferroelectric condenser
2) as the hysteresis loop of the function of the voltage (V) of ferroelectric condenser.Should be noted that when the voltage of ferroelectric condenser was zero, ferroelectric condenser can be in a kind of state in the polarization state, logic " one " polarized state or logic " zero " polarized state.
In Fig. 1, when voltage is supplied with when being zero, ferroelectric condenser is for example logic " zero " polarized state, for example " Qr " that is represented by " D ".When the voltage of ferroelectric condenser when the positive voltage direction increases, polarization charge (Qr) increases to+Q direction.As a result, if the voltage of ferroelectric condenser is increased to operating voltage "+Vs ", then polarization charge (Q) reaches " A " state of maximum "+Qs ".Polarization charge reaches capacity state " A " afterwards, even voltage reduces to zero, polarization charge can not be reduced to zero yet but stop at remanent polarization states "+Qr " " B " state, i.e. logic " " polarized state.On the other hand, when the voltage of ferroelectric condenser from zero when the negative voltage direction increases, promptly opposite direction with inceptive direction, polarization charge (Q) from "+Qr " to-Q direction reduction.As a result, if voltage is increased to " Vs ", then polarization charge reaches " C " state of maximum " Qs ".Polarization charge reaches capacity state " C " afterwards, even voltage increases to zero, polarization charge can not be reduced to zero yet but stop at remanent polarization states " Qr " " D " stage, i.e. logic " " polarized state.
As mentioned above, residual polarization " Qr " or "+Qr " will be present in the ferroelectric material when applying voltage to ferroelectric condenser and removing---in other words, applying potential pulse " V " or "+V "---again.Then, as the potential pulse "+V " of opposite polarity or " V " when imposing on capacitor, residual polarization changes direction.Can stablize two by means of potential pulse like this and repeat conversion between the polarized state.
Because the operation of the read and write in the FRAM unit is to be undertaken by the conversion of above-mentioned residual polarization, so its service speed depends on the change-over time of residual polarization.Be to be determined by the usable floor area of capacitor, ferroelectric film thickness and service voltage this change-over time.
In the ferroelectric memory manufacturing process, one of crucial processing is to form coverlay on ferroelectric condenser, and does not destroy any ferroelectric properties.Conventional ferroelectric memory manufacturing process is as follows.
At first, formation has the MOS transistor of diffusion layer, gate oxide and grid on Semiconductor substrate.On semiconductor and MOS transistor, form interlayer insulating film.On interlayer insulating film, form the ferroelectric condenser that constitutes by bottom electrode, ferroelectric film and top electrode.Opening contact hole in interlayer insulating film is to expose diffusion layer, lower and upper electrode.At last, deposited metal and composition are metal interconnected to form in contact hole and on the interlayer insulating film.
Ferroelectric material must have perovskite (perovskite) structure to show as shown in fig. 1 the ferroelectric properties as hysteresis loop.But in process for making, particularly the step of deposition insulating layer on ferroelectric condenser may produce compression or H
2, and the compression that therefore forms may influence the ferroelectric material structure, reduces residual polarization thus.
Generally speaking, preferably corresponding with compression in deposit interlayer insulating film process ferroelectric film is applied tension stress (promptly showing as compression about ferroelectric film).Therefore, need a kind of method, the interlayer insulating film that shows as tension stress can be provided on ferroelectric film.
The invention provides ferroelectric condenser and manufacture method thereof.Key feature of the present invention is, is the low temperature oxide layer that shows as tension stress with respect to ferroelectric condenser on the ferroelectric condenser.
Thereby, the purpose of this invention is to provide ferroelectric condenser and manufacture method thereof with excellent ferroelectric properties.
For realizing this and other advantage and according to purpose of the present invention, this method comprises provides the Semiconductor substrate that has formed on it such as the integrated circuit of the MOS transistor with diffusion layer.On Semiconductor substrate and MOS transistor, form first interlayer insulating film.On first interlayer insulating film, form bottom electrode, ferroelectric film and upper electrode layer and composition to form ferroelectric condenser.On the capacitor and first interlayer insulating film, form second interlayer insulating film.For improving capacitor specific characteristics, the interlayer insulating film of stack must show as tension stress.For this reason, second interlayer insulating film is formed by the low temperature oxide layer that shows as big tension stress with respect to ferroelectric condenser.This low temperature oxide layer can be selected from a kind of among PE-TEOS, USG and the ECR-OX.In second interlayer insulating film and first insulating barrier, open first contact hole that reaches bottom electrode and diffusion layer respectively.In oxygen atmosphere, carry out the annealing first time.Deposit the first metal layer on contact hole neutralizes second interlayer insulating film, composition is metal interconnected to form first then.On second interlayer insulating film and first form the 3rd interlayer insulating film on metal interconnected.In order to improve capacitor specific characteristics, the interlayer insulating film of stack must show as tension stress.For this reason, second interlayer insulating film is formed by the low temperature oxide layer that shows as big tension stress with respect to ferroelectric condenser.This low temperature oxide layer can be selected from a kind of among PE-TEOS, USG and the ECR-OX.Open second contact hole in the 3rd interlayer insulating film, it reaches top electrode.In oxygen atmosphere, carry out the annealing second time.At last, deposit second metal level on second contact hole neutralizes the 3rd interlayer insulating film, and composition is metal interconnected to form second.
For realizing this and other advantage and according to purpose of the present invention, semiconductor device comprises: the Semiconductor substrate that has the integrated circuit with diffusion layer, cover first interlayer insulating film of Semiconductor substrate and integrated circuit, by bottom electrode, ferroelectric film and top electrode constitute and are formed on ferroelectric condenser on first interlayer insulating film with such order, cover second interlayer insulating film of first interlayer insulating film and ferroelectric condenser, be formed on second interlayer insulating film and respectively by first contact hole in second interlayer insulating film neutralization, second and first interlayer insulating film and bottom electrode and diffusion layer electrically contact first metal interconnected, cover second interlayer insulating film and first the 3rd metal interconnected interlayer insulating film, wherein, each the second and the 3rd interlayer insulating film has the tension stress with respect to ferroelectric condenser, what form on the 3rd interlayer insulating film is second metal interconnected, and it electrically contacts by second contact hole and the top electrode in the 3rd interlayer insulating film.
In the aforesaid semiconductor device, the second and the 3rd interlayer insulating film is the low temperature oxide layer that is selected from PE-TEOS, USG and ECR-OX.
Be more readily understood the present invention with reference to the accompanying drawings, its purpose is more obvious for those skilled in the art, wherein:
Fig. 1 is the polarization charge (Q: μ C/cm in the expression ferroelectric condenser
2) as the hysteresis loop of the function of the voltage (V) of ferroelectric condenser;
Fig. 2 A-2D is the flow chart of the processing step of the expression new method that is used to form semiconductor device according to the present invention;
Fig. 3 A represents the relation between the deposition temperature of residual polarization and oxide layer;
Fig. 3 B represents residual polarization and the relation between the oxygen flow rate in deposition process;
Fig. 4 A represents the stress of ECR-OX and the relation between the deposition temperature;
Fig. 4 B represents the stress of ECR-OX and the relation between the oxygen flow rate;
Fig. 5 represents just on substrate after the deposited oxide layer (the various interlayer insulating films) stress that puts on silicon substrate as temperature funtion;
Fig. 6 A represents according to the present invention when the thick ECR-OX layer of 2000 and the thick USG layer of 2500 are used separately as second interlayer insulating film and the 3rd interlayer insulating film as the electric current and the residual polarization that apply the function of voltage; With
Fig. 6 B represents according to the present invention when the thick ECR-OX layer of 4500 is used as second interlayer insulating film and the 3rd interlayer insulating film as the electric current and the residual polarization that apply the function of voltage.
The preferred embodiments of the present invention are described with reference to the accompanying drawings.
Fig. 2 A represents to have carried out according to one embodiment of present invention the sectional view of the Semiconductor substrate 1 of several processing steps.At first, utilize the common process operation to form MOS transistor 5.MOS transistor 5 comprises the diffusion layer 2 in the Semiconductor substrate 1 of gate insulation layer 3, the grid on it 4 and gate insulation layer 3 sides.First interlayer insulating film 6 covers Semiconductor substrate 1 and MOS transistor 5 fully.The bottom electrode 7 that is made of platinum (Pt), the ferroelectric film 8 that is made of BST and the top electrode 9 that is made of platinum (Pt) are deposited on first interlayer insulating film 6, and with the dry corrosion composition with formation ferroelectric condenser 10.
Forming second interlayer insulating film 11 on first interlayer insulating film 6 and on the ferroelectric condenser 10.In the present invention, second interlayer insulating film 11 is to be formed by the low temperature oxide layer such as PE-TEOS layer, USG layer or ECR-OX layer, and they show as the tension stress with respect to ferroelectric condenser 10, and improve capacitor specific characteristics, for example residual polarization thus.
For example can use N
2O, SiH
4And O
2Gas is about deposit ECR-OX layer under 200 ℃ and the about 400W of RF power in temperature.The advantage of ECR technology is, even also can supply with the high beta plasma energy at low temperatures.The PE-TEOS layer can use TEOS and N
2O is about 400 ℃, RF power in temperature and is about and utilizes the plasma CVD technology to form under the 400W.The USG layer can use O
3-TEOS is about in temperature and utilizes the APCVD technology to form under 400 ℃.
Fig. 3 A and Fig. 3 B represent deposition temperature and the O as the ECR-OX layer respectively
2The capacitor residual polarization of the function of flow rate.In Fig. 3 A and Fig. 3 B, " as.cap " meaning is that capacitor is not covered by the ECR-OX layer.Shown among Fig. 3 A and Fig. 3 B, residual polarization (μ C/cm
2) along with the deposition temperature and the O of ECR-OX layer
2The increase of flow rate and reducing.On the other hand, Fig. 4 A represents the stress of ECR-OX and the relation between the deposition temperature, and Fig. 4 B represents the stress of ECR-OX and the relation between the oxygen flow rate.Shown in Fig. 4 A and 4B, the tension stress of ECR-OX layer is along with the deposition temperature and the O of ECR-OX layer
2The increase of flow rate and reducing gradually.
Therefore, deposit ECR-OX layer under about 200 ℃ temperature preferably has high residual polarization and ECR-OX layer at this temperature ferroelectric condenser and has high tensile stress with respect to capacitor.
Referring to Fig. 2 B, in interlayer insulating film by dry corrosion opening contact hole 12a to expose bottom electrode 7 and diffusion layer 2.For removing the plasma damage of contact hole 12a, carry out the annealing first time under 450 ℃, in oxygen atmosphere being lower than.
Referring to Fig. 2 C, deposit the first metal layer on contact hole 12a neutralizes second interlayer insulating film 11, and with the dry corrosion composition to form first metal interconnected 12.Then, on second interlayer insulating film 11 and first metal interconnected 12, form the 3rd interlayer insulating film 13.The 3rd interlayer insulating film 13 also is to be formed by the low temperature oxide layer such as PE-TEOS layer, USG layer or ECR-OX layer, and they show as the tension stress with respect to ferroelectric condenser 10, and improves capacitor specific characteristics, for example residual polarization thus.
Referring to Fig. 2 D, in the 3rd interlayer insulating film 13, open second contact hole to expose top electrode 9 by dry corrosion.Then, carry out second time annealing under 450 ℃ of temperature, in oxygen atmosphere being lower than.Deposit second metal level on contact hole neutralizes the 3rd interlayer insulating film 13, and metal interconnected with the dry corrosion composition to form second.
Wish to put in the whole annealing process of stress after deposit of oxide layer of ferroelectric condenser and have constant value.The STRESS VARIATION reduction in direct ratio of the characteristic of ferroelectric condenser and stack oxide layer.Fig. 5 is illustrated in after the deposit low temperature oxide layer on the substrate (the various low temperature oxide layers) stress that puts on substrate as the function of annealing temperature.In Fig. 5, " A " expression just puts on the stress of substrate after the deposit low temperature oxide layer, " D " expression is when be about 450 ℃ of stress that put on substrate when annealing in temperature, temperature was cooled to " A " state after " B " was illustrated in 450 ℃ of annealing, and " C " is illustrated in the stress difference between " A " and " B ".As shown in Figure 5,, compare with PE-TEOS, have low relatively STRESS VARIATION in the annealing process procedure of ECR-OX layer after deposit as the USG layer with other low temperature oxide layer.
Fig. 6 A represents according to the present invention when the thick ECR-OX of 2000 and the thick USG layer of 2500 are used separately as second interlayer insulating film and the 3rd interlayer insulating film as the electric current and the residual polarization that apply the function of voltage, Fig. 6 B represent according to the present invention when the thick ECR-OX layer of 4500 during as second interlayer insulating film and the 3rd interlayer insulating film conduct apply the electric current and the residual polarization of the function of voltage.
Fig. 6 A is compared with Fig. 6 B, wherein the ECR-OX layer be deposited on second with the 3rd interlayer insulating film on Fig. 6 B have relative low service voltage and relative high residual polarization.This is because as previously mentioned, USG is deposit under about 400 ℃ relatively-high temperature, and has a high relatively STRESS VARIATION, as shown in Figure 5.From Fig. 5 and Fig. 6 as can be seen, wish that the 3rd insulating barrier must be formed by low temperature oxide layer, so that improve the ferroelectric condenser characteristic.
Be appreciated that according to the present invention from the explanation of front, be deposited on the ferroelectric condenser having tension stress such as the low temperature oxide layer of ECR-OX, USG or PE-TEOS layer, and improve the ferroelectric condenser characteristic thus.
Those skilled in the art are easy to change these parameters to adapt to their condition.
The front represents with reference to its preferred embodiment and the present invention has been described, should be understood that those skilled in the art can make in form and the various changes on the details under the spirit and scope of the present invention situation not breaking away from.
Claims (5)
1. method of making semiconductor device may further comprise the steps:
On Semiconductor substrate, form integrated circuit with diffusion layer;
On described Semiconductor substrate, form first interlayer insulating film;
On described first interlayer insulating film, form the ferroelectric condenser that constitutes by bottom electrode, ferroelectric film and top electrode;
Form second interlayer insulating film to cover described ferroelectric condenser and described first interlayer insulating film;
In described second interlayer insulating film He in described second and first interlayer insulating film, form first contact hole in the position that corresponds respectively to described bottom electrode and described diffusion layer;
In oxygen atmosphere, carry out the annealing first time;
The deposit the first metal layer is to form be electrically connected with described diffusion layer and bottom electrode first metal interconnected in described first contact hole;
Form the 3rd interlayer insulating film to cover described first metal interconnected and described second interlayer insulating film;
In the described the 3rd and second interlayer insulating film, form second contact hole in position corresponding to described top electrode;
In oxygen atmosphere, carry out second time annealing, thereby make the described second and the 3rd interlayer insulating film have tension stress with respect to described ferroelectric condenser; With
Deposit second metal level is to form be electrically connected with described top electrode second metal interconnected in described second contact hole.
2. method according to claim 1, wherein each the described second and the 3rd interlayer insulating film is made of low temperature oxide layer.
3. method according to claim 2, wherein said low temperature oxide layer are selected from the group that is made of PE-TEOS, USG and ECR-OX.
4. semiconductor device comprises:
The Semiconductor substrate that has integrated circuit with diffusion layer;
Cover first interlayer insulating film of described Semiconductor substrate and described integrated circuit;
Constitute and be formed on ferroelectric condenser on described first interlayer insulating film in proper order by bottom electrode, ferroelectric film and top electrode with this;
Second interlayer insulating film of first interlayer insulating film and described ferroelectric condenser shown in the covering;
Be formed on first metal interconnected on described second interlayer insulating film, its respectively by in described second interlayer insulating film and first contact hole in described second and first interlayer insulating film be electrically connected with described bottom electrode and described diffusion layer;
Cover described second interlayer insulating film and described first the 3rd metal interconnected interlayer insulating film;
Wherein each the described second and the 3rd interlayer insulating film has the tension stress with respect to ferroelectric condenser;
Second metal interconnected shown in being formed on the 3rd interlayer insulating film, it is electrically connected with described top electrode by second contact hole in described the 3rd interlayer insulating film.
5. semiconductor device according to claim 4, wherein each the described second and the 3rd interlayer insulating film is to be made of the low temperature oxide layer that comprises PE-TEOS, USG and ECR-OX.
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KR1019980010989A KR100268453B1 (en) | 1998-03-30 | 1998-03-30 | Semiconductor device and its manufacturing method |
KR10989/1998 | 1998-03-30 |
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US (1) | US6368909B2 (en) |
JP (1) | JP3833841B2 (en) |
KR (1) | KR100268453B1 (en) |
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1998
- 1998-03-30 KR KR1019980010989A patent/KR100268453B1/en not_active IP Right Cessation
- 1998-11-13 TW TW087118834A patent/TW388989B/en not_active IP Right Cessation
- 1998-11-17 GB GB9825189A patent/GB2336030B/en not_active Expired - Fee Related
- 1998-12-30 DE DE19860829A patent/DE19860829B4/en not_active Expired - Fee Related
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1999
- 1999-03-10 FR FR9902959A patent/FR2776833B1/en not_active Expired - Fee Related
- 1999-03-18 JP JP07449199A patent/JP3833841B2/en not_active Expired - Fee Related
- 1999-03-30 CN CNB991034287A patent/CN1140925C/en not_active Expired - Fee Related
- 1999-03-30 US US09/281,706 patent/US6368909B2/en not_active Expired - Fee Related
Cited By (4)
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CN100362660C (en) * | 2003-04-24 | 2008-01-16 | 富士通株式会社 | Semiconductor device and its production |
CN100463182C (en) * | 2004-10-19 | 2009-02-18 | 精工爱普生株式会社 | Ferroelectric memory and method of manufacturing the same |
CN101064306B (en) * | 2006-04-27 | 2011-06-29 | 松下电器产业株式会社 | Semiconductor integrated circuit and system lsi including the same |
CN102184919B (en) * | 2006-04-27 | 2013-01-16 | 松下电器产业株式会社 | Semiconductor integrated circuit |
Also Published As
Publication number | Publication date |
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TW388989B (en) | 2000-05-01 |
KR19990076228A (en) | 1999-10-15 |
DE19860829B4 (en) | 2005-12-01 |
KR100268453B1 (en) | 2000-11-01 |
GB9825189D0 (en) | 1999-01-13 |
DE19860829A1 (en) | 1999-10-07 |
US20010023080A1 (en) | 2001-09-20 |
FR2776833A1 (en) | 1999-10-01 |
JPH11330390A (en) | 1999-11-30 |
GB2336030A (en) | 1999-10-06 |
JP3833841B2 (en) | 2006-10-18 |
US6368909B2 (en) | 2002-04-09 |
FR2776833B1 (en) | 2005-04-15 |
GB2336030B (en) | 2000-05-10 |
CN1140925C (en) | 2004-03-03 |
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