CN1226746C - High speed multiplex first-in first-out storage structure - Google Patents
High speed multiplex first-in first-out storage structure Download PDFInfo
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Abstract
The present invention relates to a high speed multiplex first-in first-out memory structure which comprises at least two memory cell arrays, a whole demoding circuit positioned between at least two memory cell arrays, a write-into control circuit, a read-out control circuit, two data-in buffers respectively positioned above at least two memory cell arrays, two multiplex circuits, two output circuits, a write-into clock buffer and a read-out clock buffer respectively arranged above and below the whole demoding circuit, wherein the write-into control circuit and the read-out control circuit are respectively positioned above and below the whole demoding circuit. The two multiplex circuits and the two output circuits are positioned below the two memory cell arrays in sequence.
Description
Technical field
The present invention relates to the memory construction of a kind of picture dynamic RAM (SRAM) and so on, particularly relate to a kind of high speed multiplex first-in first-out storage structure.
Background technology
In one chip, provide the memory construction of huge storage volume (referring to large scale) to be widely used in electronic system, as computer, communication and category of consumer electronic devices like product.Recently the progress on semiconductor technology, especially provide complete system on an one chip, make in an integrated circuit to embed (embedded) storer, so that the effect that might make this integrated circuit is as the holonomic system with huge data storage capability.
Because the tendency that industry member has requirement to continue to increase for each chip memory bit amount, the size that therefore is applied to the in-line memory of high speed, bifrequency, multiplexed output, multichannel separation input increases gradually.
Shown in Figure 1 is high speed bifrequency in the past, multiplexed output, multichannel is separated the large size memory structure of input, comprises a global solution decoding circuit (global decoder circuit) 11, four global solution decoding circuit 11 both sides and be connected to the memory cell array (memory cell array) 12 of global solution decoding circuit 11 of being placed in twos, one is positioned on the global solution decoding circuit 11 and connects the write control circuit (write control circuit) 13 of global solution decoding circuit 11, one is positioned under the global solution decoding circuit 11 and is connected to the read-out control circuit (read control circuit) 14 of global solution decoding circuit 11, one between global solution decoding circuit 11 and read-out control circuit 14 and be connected the predecode circuit (pre-decoder circuit) 15 of global solution decoding circuit 11 and read-out control circuit 14, be positioned at readout clock impact damper (read clock buffer) 16 and under the read-out control circuit 14 in regular turn and write clock buffer (write clock buffer) 17 and two spacing parallel arrangings on each memory cell array 12 and be connected to the data input buffer (data input buffer) 18 that writes clock buffer 17.Whole demoder 11 is to write whole decoded portion 111 and by one to read whole decoded portion 112.Each memory cell array 12 is formed by the structure cell time array 122 that a regional decoding device 121 and two lays respectively at regional decoding device 121 both sides, and each structure cell time array 122 is for having m row and the capable memory cell array of n, each structure cell time array is provided with a multiplexer 123, that is connected to each row for 122 times and connects the sensor amplifier 124 of multiplexer 123 and the output circuit 125 that is connected to sensor amplifier 124, and each output circuit 125 also is connected to readout clock impact damper 16.
Below writing with read operation of memory construction in the past done an explanation:
1, write operation:
The data that need write the corresponding stored unit can be delivered to data input buffer 18, when the address group of corresponding these data to write control circuit 13, write control circuit 13 is in order to produce the required control signal of write storage unit, and decode with 121 pairs of these address groups of regional decoding circuit through writing whole decoded portion 111, open driving with the storage unit which row corresponding address group decision is positioned at, be sent to corresponding storage unit in order to clocking (clock signal) with the data sync that is controlled in data input buffer 18 and write clock buffer 17, with with in the data write storage unit, finish write operation.
2, read operation:
When the address group that need are read is delivered to read-out control circuit 14, this read-out control circuit 14 is read the required control signal of storage unit in order to generation, and through predecode circuit 15, reading 121 pairs of address groups of whole decoded portion 112 and regional decoding part decodes, open driving with the storage unit that determines which row, and deliver to multiplexer 123 through the data that the control of control signal will be stored in the storage unit, the data of multiplexer 123 which storage unit of decision are exportable, and the data of which storage unit are not exportable, and the data that multiplexer 123 is exported are delivered to output circuit 125 after sensor amplifier 124 amplifies, and these readout clock impact damper 16 clockings are sent data to external device (ED) synchronously to control this output circuit 125 at last.
Yet memory construction still had following shortcoming in the past:
1, circuit clock may be inconsistent:
Owing to write clock circuit 17 and readout clock circuit 16 the same side at global solution decoding circuit 11, make its path long to the data input buffer 18 of the opposite side that is positioned at global solution decoding circuit 11, and may differ too many because of the RC effect makes the time of the diverse location 181,182 that arrives data input buffer 18 in the process of transmission, and can't synchronous working, cause the hiding clock of integrated circuit inconsistent, this external cause transmission course is long, a large amount of losses that clock signal is caused and the problem that causes clock signal to be interfered.
2, it is wrong that data transmit possibility:
Because multiplex's output, so data by memory cell array 12 feeble signal of sending, must be via transmitting again to multiplexer 123 at bit line (bit line), but in transport process, because the feeble signal on the bit line is actually on the plain conductor of long distance and transmits, the capacity effect (coupling effect) of the plain conductor of this long distance can disturb correct feeble signal, the signal that it is made a mistake, for example, original predetermined signal that transmits logic " 1 " forms logic " 0 " because of capacity effect, thereby produces the wrong problem of data possibility that memory cell array is sent to multiplexer.
3, integrated circuit is oversize:
In memory construction in the past, need setting area decoding circuit 121 in each memory cell array 12, make the memory cell array 12 must lateral magnification and cause size to increase, cause global solution decoding circuit 11 to the path lengthening of regional decoding circuit 121 with the unlatching driving of control store unit, and may produce rub-out signal because of the RC effect, and also extend in data input buffer 18 to the path of each storage unit thereupon, decay for fear of data-signal, data input buffer 18 in order to amplified data signal also strengthens thereupon, causes overall circuit size excessive.
Summary of the invention
The transmission path that fundamental purpose of the present invention is to provide a kind of clock signal that realizes shortening clock buffer with realize that clock signal can accurately be transmitted and the high speed multiplex first-in first-out storage structure of the effect that the integrated circuit clock is consistent.
A further object of the present invention is to provide a kind of high speed multiplex first-in first-out storage structure that can correctly transmit data.
Another purpose of the present invention is to provide a kind of high speed multiplex first-in first-out storage structure that can effectively utilize area and effective minification.
For achieving the above object, the present invention is a kind of high speed multiplex first-in first-out storage structure, comprise that at least four memory cell arrays, a global solution decoding circuit, a write control circuit, a read-out control circuit, two data input buffers, write clock buffer, two duplex circuits, two output circuits and a readout clock impact damper, wherein:
Each memory cell array is that to be aligned to m row capable with 2n, and each array storage unit has one group of corresponding bit lines and and is arranged at regional decoding unit in these row in putting in this array storage unit, makes formation one regional decoding device in each memory cell array;
This global solution decoding circuit is between this at least four memory cell array, and be connected to the regional decoding device of each memory array, and this global solution decoding circuit and regional decoding device be in order to decoding to external address group, drives with the unlatching of decision to the word line of array storage unit that should the address group;
This write control circuit is to be positioned at the top of this global solution decoding circuit and to be connected to this global solution decoding circuit, in order to receiving external address group, and produces and writes the required write control signal of this storage unit, is sent to this global solution decoding circuit together with this address group;
This read-out control circuit is to be positioned at the below of this global solution decoding circuit and to be connected to this global solution decoding circuit, in order to receiving external address group, and produce read this storage unit required read control signal, be sent to this global solution decoding circuit together with this address group;
Each data input buffer connects corresponding memory cell array, waits to import the data of corresponding stored unit in the memory cell array in order to temporary and amplification;
This writes the top that clock buffer is positioned at this write control circuit, and is connected to data input buffer, is temporary in data sync in this two data input buffer in order to control and inputs in the memory cell array in the corresponding stored unit;
Each duplex circuit is the capable storage unit of 4n that connects each memory cell array with bit line, and in order to receive data and the selectivity output that the storage unit of this 4n in capable exported;
Each output circuit connects corresponding duplex circuit respectively, in order to the temporary data of being exported by duplex circuit with amplification; And
This readout clock impact damper connects this two output circuit, uses so that the data sync in this at least two output circuit exports external device (ED) to.
Constitute by above-mentioned technology, when writing the address group and import this write control circuit and this data and input to data input buffer, this write control circuit generation write control signal and this global solution decoding circuit and this regional decoding device write the address group to this and decode, with drive column of memory cells that should the address group opened and is positioned at write state after, this writes clock buffer and is controlled in that data sync inputs in the storage unit in the data input buffer; On the contrary, when reading the address group when importing this read-out control circuit, this read-out control circuit produces to be read control signal and this global solution decoding circuit and this is read the address group decodes, to drive column of memory cells that should the address group is opened and is positioned at the state of reading, be stored in the interior data transmission of this storage unit to this duplex circuit, through this duplex circuit, read address group selection output data to this correspondence output circuit according to this and keep in, and export by the data sync that this readout clock impact damper control is temporary in the output circuit.
Description of drawings
Fig. 1 is the synoptic diagram of memory construction in the past;
Fig. 2 is the circuit diagram of a preferred embodiment of the present invention;
Fig. 3 is the circuit diagram of another preferred embodiment of the present invention;
Fig. 4 is the circuit diagram of regional decoding unit of the regional decoding device of Fig. 2;
Fig. 5 is the circuit diagram of regional decoding unit of the regional decoding device of Fig. 3.
Embodiment
Before the present invention is described in detail, should be noted that in the overall description book same numeral is to be used for indicating components identical.
Please refer to shown in Figure 2ly, The present invention be directed to and to satisfy bifrequency, multiplexed output (multiplex output), multichannel and separate the demand of input (demultiplex input), large-sized embedded (embedded) dynamic RAM (SRAM) and design.Preferred embodiment of the present invention comprises four memory cell arrays (memory cell array) 2, one global solution decoding circuit (global decoder circuit) 3, one write control circuit (write controlcircuit) 4, one read-out control circuit (read control circuit) 5, two data input buffers (data input buffer) 6, one writes clock buffer (write clock buffer) Freq1, two duplex circuits 8, two output circuits 9 and a readout clock impact damper (read clock buffer) Freq2.
Each memory cell array 2 is to be aligned to m row and the capable matrix of 2n, and in this array storage unit, have one group of corresponding bit lines (bit line) 211 and in each array storage unit and be arranged at regional decoding unit 221 in these row in putting, make each memory cell array be separated into the structure cell time array 21 of two m * n and be arranged in a regional decoding device 22 of twice array 21;
This global solution decoding circuit 3 is the central authorities that are positioned at memory cell array 2, and the both sides of global solution decoding circuit 3 connect the regional decoding device 22 of two memory cell arrays 2 respectively with whole word line (global word lines).And this global solution decoding circuit 3 and regional decoding device 22 be in order to decoding to external address group, drives with the unlatching of decision to the word line of array storage unit that should the address group.This global solution decoding circuit 3 is to write whole decoded portion 31 and by one to read whole decoded portion 32 and formed;
This write control circuit 4 is positioned at the top of this global solution decoding circuit 3 and is connected to this global solution decoding circuit 3, in order to receive the external address group that writes, and produce the required write control signal of write storage unit, transfer to the whole decoded portion 31 of writing of global solution decoding circuit 3 together with the address group;
This read-out control circuit 5 is positioned at the below of this global solution decoding circuit 3 and is connected to this global solution decoding circuit 3, in order to receive the external address group of reading, and produce read storage unit required read control signal, transfer to the whole decoded portion 32 of reading of global solution decoding circuit 3 together with the address group and decode.And in the present embodiment, one predecode circuit (Pre-decoder circuit) 51 more is set between this read-out control circuit 5 and the global solution decoding circuit 3, the whole decoded portion 32 of reading that connects this read-out control circuit 5 and global solution decoding circuit 3 is made partial decoding of h in order to send in the address group earlier before reading decoded portion 32;
Two data input buffers 6 connect the external device (ED) (not shown) and connect two memory cell arrays 2 respectively, send the data of waiting to import in the memory cell array 2 in order to temporary with the amplification external device (ED);
This writes the top that clock buffer Freq1 is positioned at this write control circuit 4, more in the past near two data input buffers 6, and be connected to these data input buffers 6, control in order to clocking (clock signal) and be temporary in these two data input buffers, 6 inter-syncs and input in the memory cell array 2 in the corresponding stored unit;
Two duplex circuits 8 are arranged at the both sides of read-out control circuit 5 respectively and lay respectively at the below of two memory cell arrays 2.In the present embodiment, each duplex circuit 8 comprises second multiplexer 82 of two first multiplexers 81 and between two first multiplexers 81, wherein second multiplexer 82 is the capable storage unit of n that connect a structure cell time array 21 that is close in two memory cell arrays 2 of its top with bit line respectively, and two first multiplexers 81 connect the n line storage unit of another structure cell time array 21 in two memory cell arrays 2 respectively, promptly second multiplexer 82 connects the capable storage unit of 2n, and the structure cell that is connected time array 21 is positioned at the central authorities of two memory cell arrays 2.The data that the bit line that each multiplexer 81,82 respectively is connected in order to reception is exported, and selectivity (promptly according to the decision of address group) is with the data output of which bit line;
Each output circuit 9 comprises three amplifying circuits 91 that connect corresponding multiplexer 81,82 respectively, in order to keep in multiplexer 81,82 data of being exported and to amplify the electric current of these data, to strengthen driving (driving) ability of data, be convenient to be sent to external device (ED);
This readout clock impact damper Freq2 connects this two output circuit 9, control the data output that is temporary in two output circuits 9 in order to clocking (clock signal), so that the data in two output circuits 9 can export the external device (ED) (not shown) synchronously to.Generally speaking, the frequency that writes clock buffer Freq1 and readout clock impact damper Freq2 institute clocking is inequality.
It should be noted that, be better than the feeble signal that bit line transmitted between memory cell array 2 and the duplex circuit 8 in order to add, signal is subjected to the interference of capacity effect and the problem of the generation that leads to errors effectively to avoid in the past, so in the present embodiment, below the memory cell array 2 a sensing amplifying circuit 7 is being set respectively in twos, and each sensing amplifying circuit 7 comprises that two first sensor amplifier (sense amplifier) SA1 and of n line storage unit of a structure cell time array 21 that connect memory cell array 2 respectively are between two first sensor amplifier SA1 and connect the second sensor amplifier SA2 of the n line storage unit of a structure cell time array 21 in two memory cell arrays 2 respectively.And identical with multiplexer be, the second sensor amplifier SA2 connects the 2n line storage unit, and each first sensor amplifier SA1 connects n line storage unit, and the structure cell time array 21 that connected of the second sensor amplifier SA2 is positioned at the centre of the inferior array 21 of the first sensor amplifier structure cell that SA1 connects.In addition, each first sensor amplifier SA1 connects the first corresponding multiplexer 81 respectively, and each second sensor amplifier SA2 connects with corresponding second multiplexer 82 respectively.Therefore, the data of the feeble signal of the storage unit output of each row are earlier to corresponding sensor amplifier SA1, SA2, the feeble signal of data is zoomed into the signal of full width (fullswing), be sent to duplex circuit 81 in bit line again, with the problem of effectively avoiding feeble signal in the past to be subject to disturb.
For the present invention is easier to understand, writing of present embodiment and read operation are described at following paragraph:
1. write operation:
Import this write control circuit 4 when writing the address group, and these data input to data input buffer 6 when temporary, this write control circuit 4 produces write control signal, write the address group together with this and import this global solution decoding circuit 3, and the whole decoded portion 31 that writes of global solution decoding circuit 3 writes the address group with 22 pairs of regional decoding devices and decodes, to drive column of memory cells that should the address group is opened, and owing to after the control of write control signal is positioned at write state, this writes clock buffer Freq1 control and is temporary in the data input buffer 6 data sync and inputs to the storage unit that is positioned at write state and carry out write activity, so that data can write in the storage unit of corresponding address group, finish write operation, and owing to of the present inventionly write the top that clock buffer Freq1 is arranged at write control circuit 4, compared to memory construction in the past more near data input buffer 6, so that the path of transmit clock signal was shorter, so to being positioned at the data input buffer 6 that writes the clock buffer Freq1 left and right sides are balances very, two data input buffers 6 can be because of the RC effect, and it is too many to cause clock signal to arrive the time phase difference of difference on the impact damper 6, effectively avoid in the past may synchronous working shortcoming.
2. read operation:
When reading address group input read-out control circuit 5, this read-out control circuit 5 produces reads control signal, together with read the address group by predecode circuit 51 to the whole decoded portion 32 of reading of global solution decoding circuit 3, so in read operation by predecode circuit 51, reading 32 pairs of whole decoded portion reads the address group and decodes, to drive column of memory cells that should the address group is opened, and owing to the effect of reading control signal makes these storage unit be positioned at the state of reading, so the data that are stored in these storage unit export sensing amplifying circuit 7 to, 7 pairs of this sensing amplifying circuits still amplify for the data of feeble signal, and make its data that become full width export duplex circuit 8 to through bit line again, and after this duplex circuit 8, according to reading the electric current of address group selection output data to this correspondence output circuit amplification data, to increase the driving force of data, the clock signal that is produced by readout clock impact damper Freq2 is controlled the data sync that is temporary in the output circuit and is exported external device (ED) at last.Can find out thus, the present invention earlier with data after sensing amplifying circuit 7 amplifies, be resent to duplex circuit 8, be different from the past and will directly be sent to the mode of multiplexer, so can effectively avoid in the past taking place because of feeble signal is subjected to the situation of the signal that the interference of capacity effect makes a mistake for the data of feeble signal.
Please refer to Fig. 3, it is the circuit diagram of another embodiment of the present invention, it is different with aforesaid embodiment be in regional decoding device 22 ', in order to solve the large-area shortcoming of regional decoding device 22 ' in memory cell array 2, accounted for, so in the present embodiment, with regional decoding device 22 ' part be arranged at outside the memory cell array 2, replacement is arranged at way in the memory cell array 2 with the Zone Full demoder, and because memory cell array 2 ' and data input buffer 6 between still have idle space, so with the part 222 of regional decoding device ' be arranged at memory cell array 2 ' on.The regional decoding device 22 of present embodiment ' can be arranged at respectively memory cell array 2 ' in main part 223 ' with the periphery 222 that is arranged at this memory cell array 2 ' outer ', wherein periphery 222 ' except with this main part 223 ' being connected, more be connected to write control circuit 4.But and this periphery 222 ' inclusion region demoder 22 ' at least one logic parameter part is set, for instance, please refer to shown in Figure 4, when the regional decoding unit 221 of the regional decoding device 22 of Fig. 2 as be one three input end with door (AND gate) 23 time, suppose that the signal of importing three input ends respectively is A, B, C, output end signal Y=ABC then, and utilize the Di Mogen law shown in following formula 1 and 2 (De Morgan ' s laws) to carry out computing:
AB ...=A+B+ ... (formula 1)
A+B+ ...=AB ... (formula 2)
So
Y＝ABC＝(AB)C＝(AB)+C
Thereby, as Fig. 5, can utilize a Sheffer stroke gate 24 (NAND gate) with two input ends to come difference input signal A, B and a phase inverter 25 (NOT gate) to come input signal C, then utilize a rejection gate 26 (NOR gate) to receive both output again, make the output Y=ABC of rejection gate 26, so in this example, regional decoding device 22 ' periphery 222 ' can be phase inverter 25, and main part 223 ' be remaining Sheffer stroke gate 24 AND 26.
Described before combining, the present invention has following advantage really:
1, clock signal can accurately be transmitted and integrated circuit clock unanimity;
Because in the present invention, respectively with two clock buffer Freq1, Freq2 is arranged at the both sides up and down of global solution decoding circuit 3 respectively and is positioned at the centre of integrated circuit, the same side that two clock buffers is placed integrated circuit different from the past, so one aspect of the present invention makes clock signal for the feed-in of the element that lays respectively at its left and right sides (as data input buffer 6 and output circuit 9) balance more, on the other hand owing to the path that writes clock buffer Freq1 transmit clock signal is shorter, the present invention can effectively be avoided in the past because of the long shortcoming that causes the clock signal distortion of clock signal transmission path, and make time error that clock signal arrives diverse location on the data input buffer 6 in allowable value, but and then reach the consistent effect of synchronousing working of integrated circuit clock with data input buffer 6.
2, data can correctly transmit;
The present invention will be resent to duplex circuit 8 for the data of feeble signal earlier after sensing amplifying circuit 7 amplifies, be different from data in the past and directly deliver to the mode that is sent to multiplexer in the plain conductor (bit line) of long distance, owing to earlier data are zoomed into the signal of full width in the present invention, so can avoid in the past taking place, can transmit the effect of correct data to multiplex's circuit 8 and reach memory cell array 2 because of feeble signal is subjected to the situation of the signal that the interference of capacity effect makes a mistake.
3, effectively utilize area;
In the present invention based on the idea of effectively utilizing area, with regional decoding device 22 ' outer memory cell array 2 exterior domains that are displaced to of part (periphery 222 '), so allow regional decoding device 22 ' shared area also can dwindle, memory cell array 2 can not expanded because of regional decoding device 22 excessive lateral, allow and write global solution decoding circuit to the bit line of each memory cell array 2 and can shorten thereupon, to reduce the chance that produces rub-out signal because of the RC effect, and data input buffer 6 to the path of each storage unit also can be shortened thereupon, so for amplifying signal also dwindles with the data input buffer 6 of avoiding signal attenuation and using thereupon, overall dimensions can be dwindled thereupon, and then reach more effective effect of utilizing area.
Claims (7)
1. high speed multiplex first-in first-out storage structure is characterized in that comprising:
At least four memory cell arrays, it is capable with 2n that each memory cell array is aligned to the m row, and each array storage unit has one group of corresponding bit lines and and is arranged at regional decoding unit in these row in putting in this array storage unit, makes and forms a regional decoding device in each memory cell array;
One global solution decoding circuit, be positioned at the centre of this at least four memory cell array, and be connected to the regional decoding device of each memory cell array, and this global solution decoding circuit and regional decoding device be in order to decoding to external address group, drives with the unlatching of decision to the word line of array storage unit that should the address group;
One write control circuit is positioned at the top of this global solution decoding circuit and is connected to this global solution decoding circuit, in order to receiving external address group, and produces the required write control signal of write storage unit, is sent to this global solution decoding circuit together with this address group;
One read-out control circuit is positioned at the below of this global solution decoding circuit and is connected to this global solution decoding circuit, in order to receiving external address group, and produce read storage unit required read control signal, be sent to this global solution decoding circuit together with this address group;
Two data input buffers are connected to this at least four memory cell array, wait to import the data of corresponding stored unit in the memory cell array in order to temporary and amplification;
One writes clock buffer, is positioned at the top of this write control circuit, and is connected to data input buffer, inputs to synchronously in the memory cell array in the corresponding stored unit in order to control the data in this two data input buffer of being temporary in;
Two duplex circuits, each duplex circuit connects the 4n line storage unit of this corresponding stored cell array with bit line, and in order to receive data and the selectivity output that the storage unit of this 4n in capable exported;
Two output circuits connect this corresponding duplex circuit respectively, in order to the temporary data of being exported by this duplex circuit with amplification; And
One readout clock impact damper connects this two output circuit, uses so that the data sync in this two output circuit exports external device (ED) to.
2. high speed multiplex first-in first-out storage structure as claimed in claim 1 is characterized in that:
Also comprise two respectively to should at least two memory cell array settings and the sensing amplifying circuit used of amplifying signal, and these two sensing amplifying circuits lay respectively between this corresponding memory cell array and the duplex circuit and are connected both, the data that cause memory cell array output earlier after the sensing amplifying circuit amplifies again to this corresponding duplex circuit.
3. high speed multiplex first-in first-out storage structure as claimed in claim 1 is characterized in that:
Each regional decoding device comprises that a main part and that is arranged in this memory cell array is positioned at the outer periphery of this memory cell array, and wherein this periphery connects this main part and this write control circuit.
4. high speed multiplex first-in first-out storage structure as claimed in claim 3 is characterized in that:
Each regional decoding device comprises that a plurality of logic parameters are provided with part, and each periphery comprises that at least a wherein logic parameter of each regional decoding device is provided with part.
5. as claim 3 or 4 described high speed multiplex first-in first-out storage structures, it is characterized in that:
Each periphery is a phase inverter.
6. high speed multiplex first-in first-out storage structure as claimed in claim 1 is characterized in that:
This global solution decoding circuit is to write whole decoded portion and by one to read whole decoded portion and formed.
7. high speed multiplex first-in first-out storage structure as claimed in claim 1 is characterized in that:
Also comprise a predecode circuit between this global solution decoding circuit and this read-out control circuit, in order to the address group of reception by this read-out control circuit output, and the decoding of going ahead of the rest, be resent to the whole decoded portion of reading of this global solution decoding circuit.
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| CN 01109554 CN1226746C (en) | 2001-03-30 | 2001-03-30 | High speed multiplex first-in first-out storage structure |
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| CN 01109554 CN1226746C (en) | 2001-03-30 | 2001-03-30 | High speed multiplex first-in first-out storage structure |
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| US7782287B2 (en) | 2006-10-24 | 2010-08-24 | Ili Technology Corporation | Data accessing interface having multiplex output module and sequential input module between memory and source to save routing space and power and related method thereof |
| CN100568382C (en) * | 2007-08-22 | 2009-12-09 | 威盛电子股份有限公司 | Push-up storage |
| CN113934372A (en) * | 2021-10-13 | 2022-01-14 | 长江先进存储产业创新中心有限责任公司 | Memory and control system thereof |
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