CN1225796C - 双载子晶体管及其制造方法 - Google Patents
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Abstract
一种双载子晶体管及其制造方法,该双载子晶体管包含有一介电层形成于一基底上,一开口形成于该介电层中且暴露部份该基底,一重掺杂硅层设于该开口的侧壁上,用来定义一自行对准基极区域,一本征基极掺杂区,经由该自行对准基极区域植入于该开口底部的该基底中,一侧壁子,设于该重掺杂硅层上并于该开口中定义一自行对准发射极区域,以及一发射极导电层,填入该自行对准发射极区域内,并与该本征基极掺杂区接触形成一PN接面;本发明的方法并不需要利用高温的热扩散制程以形成非本征基极区域,因此不但可以形成双载子晶体管,也可以用来形成异质接面的双载子晶体管的发射极区域/基极区域与集电极区域,同时达到简化制程步骤,降低制程成本的目的。
Description
技术领域
本发明涉及半导体制造技术,尤其是一种双载子晶体管(bipolarjunction transistor,BJT)及其制作方法,尤指一种利用自行对准(self-aligned)的双载子晶体管及其制作方法。
背景技术
由于双载子晶体管同时利用″电子″和″空穴″这两种载子来传导电流,所以双载子元件具有其开关速度快且可以在较小的空间中提供较大的电流的优点,并已成为集成电路的基本元件。然而由于硅的电子/空穴迁移率(mobility)太低,无法满足高频元件的需求,因此为了要提高双载子晶体管的操作速度,现行半导体制程多将硅基底的双载子晶体管改为砷化镓(GaAs)基底的双载子晶体管或是硅锗(SiGe)异质接面(hetero-junction)双载子晶体管(HBTs)。
请参照图1至图5,图1至图5为习知制作一硅基底10的双载子晶体管的方法示意图。如图1所示,一P型单晶硅基底10包含有一重掺杂N型区域12以及一重掺杂P型区域14。习知制作双载子晶体管的方法先于基底10上形成一厚度约为1.2微米的N型磊晶(epitaxial)层16,且在形成磊晶层16的同时,重掺杂N型区域12与重掺杂P型区域14中的掺质会扩散并进入磊晶层16中。接着于磊晶层16上依序形成一二氧化硅层18以及一氮化硅层20,并进行一微影与蚀刻制程,去除部分的氮化硅层20、二氧化硅层18与磊晶层16,以暴露出部分磊晶层16,并形成多个开口22。
随后如图2所示,进行一热成长制程。将暴露出的部份磊晶层16氧化成一氧化层24并填入开口22,直至氧化层24的上表面与氮化硅层20的上表面等高为止,然后去除氮化硅层20。在进行热成长制程的同时,重掺杂N型区域12与重掺杂P型区域14中的掺质会再扩散,而扩大重掺杂N型区域12与重掺杂P型区域14的范围。接着于氧化层24上沉积一光阻层26,并进行一曝光与显影制程,以于光阻层26中形成一开口27,然后进行一离子布植制程,将适量的N型掺质,例如磷离子经由开口27植入氧化层24下的磊晶层16中,以形成一重掺杂N型集电极(collector)区域28。
如图3所示,然后去除光阻层26,并于氧化层24上形成另一图案化光阻层(未显示),并进行一湿蚀刻制程或是反应离子蚀刻(RIE)制程,去除磊晶层16上方的氧化层24,以形成一开口30。接着于基底10上依序沉积一厚度约为8000埃的P型多晶硅层32以及一厚度约为5000至6000埃的二氧化硅层34,再于二氧化硅层34上形成一图案化光阻层(未显示),并进行一微影与蚀刻制程,去除部分的二氧化硅层34以及多晶硅层32,以形成一开口36,并暴露出部分磊晶层16。
如图4所示,进行一热成长制程,以于基底10上均匀形成一厚度约为0.2至0.4微米的二氧化硅层38,且二氧化硅层38均匀覆盖开口36的底部及其侧壁。而在进行热成长制程的同时,多晶硅层32中的P型掺质会扩散进入底下的N型磊晶层16中,以形成一P型非本征(extrinsic)基极区域40。接着进行一垂直型反应离子蚀刻制程,以去除开口36底部与氧化层24上的氧化层38,然后进行一低能量且高剂量的离子布植制程,将砷离子经由开口36植入磊晶层16中,以形成一厚度约为0.2微米N型浅发射极(emitter)区域42,再进行一高能量且高剂量的离子布植制程,将磷离子经由开口36植入磊晶层16中,以形成一厚度约为0.2微米的N型重掺杂凸起子集电极(raised subcollector)44,且突起子集电极44会深入重掺杂N型区域12中,接着进行一中能量且低剂量的离子布植制程,将硼离子经由开口36植入磊晶层16中,以形成一本征基极(intrinsic base)区域46。
最后如图5所示,进行一微影与蚀刻制程,以于多晶硅层32与集电极区域28上分别形成一接触窗开口(未显示),然后将金属填入接触窗开口以及开口36中,以形成金属接触(metal contact)50,52与48,完成习知双载子晶体管的制作。
习知制作双载子晶体管的方法,不但制程非常复杂,且虽然利用自行对准方法以形成双载子晶体管的基极与发射极,然而其非本征基极仍是利用热扩散制程以形成,因此无法精确控制本征基极区域与非本征基极区域以及集电极区域之间的接触面积,容易造成基极区域与集电极区域之间的电容过高,不符合高频元件的需求。此外,双载子晶体管的PN接面的介面越明显,元件的效能越好,可是在高温下,硅锗HBT的硅锗磊晶层(SiGe epitaxiallayer)与硅的介面将会产生许多差排而破坏其高速特性,因此制作硅锗磊晶层的温度必须控制在700℃以下,又由于习知的双载子晶体管必须用到多次的热扩散制程,因此并不适用于制作异质接面的双载子晶体管。
发明内容
本发明的主要目的在于提供一种自行对准(self-aligned)的双载子晶体管(bipolar junction transistor,BJT)中PN接合(PN junction)的制作方法。
本发明的另一目的在于提供一种自行对准的异质接面双载子晶体管(hetero-junction bipolar transistor,HBT),且适用于高频元件。
在本发明的最佳实施例中的一种双载子晶体管,包含有一基底,一介电层形成于该基底的一预定区域内,一开口形成于该介电层中且暴露部份该基底,一重掺杂多晶硅层形成于该开口的侧壁上,且该重掺杂多晶硅层于该开口中定义一自行对准基极区域,一本征(intrinsic)基极掺杂区,经由该自行对准基极区域植入于该开口底部的该基底中,一侧壁子,设于该重掺杂多晶硅层上,且该侧壁子于该开口中定义一自行对准发射极区域,以及一发射极导电层,填入该自行对准发射极区域内,并与该本征基极掺杂区接触形成一PN接面。
另外,本发明还提出了一种异质接面双载子晶体管,包含有:一基底;一介电层,形成于该基底的一预定区域内;一开口,形成于该介电层中且暴露部份该基底;一硅锗磊晶层,形成于该开口的侧壁及底部;一侧壁子,设于该硅锗磊晶层上,且该侧壁子于该开口中定义一自行对准发射极区域;及一发射极导电层,填入该自行对准发射极区域内,并与该硅锗磊晶层接触形成一PN接面。
本发明利用该重掺杂多晶硅层于该开口中定义一自行对准基极区域以形成该本征基极掺杂区,再利用设于该重掺杂多晶硅层上的侧壁子,定义一自行对准发射极区域以形成该发射极区域,最后直接填入导电层以形成该自行对准发射极区域,因此只需要形成一开口,就可以直接利用自行对准方法以形成发射极/基极与集电极,可制作小尺寸且高效能的双载子晶体管。
附图说明
图1至图5为习知制作一双载子晶体管的方法示意图;
图6为本发明一种自行对准的双载子晶体管的结构示意图;
图7至图11为本发明一种制作自行对准的双载子晶体管的方法示意图;
图12至图14为本发明另一实施例制作自行对准的异质接面双载子晶体管的方法示意图。
图示的符号说明:
10P型单晶硅基底 12重掺杂N型区域
14重掺杂P型区域 16N型磊晶层
18二氧化硅层 20氮化硅层
22开口 24氧化层
26光阻层 27开口
28重掺杂N型集电极区域 32P型多晶硅层
34二氧化硅层 36开口
38二氧化硅层 40P型非本征基极区域
42N型浅发射极区域 44N型凸起子集电极区域
46P型本征基极区域 48金属接触
50金属接触 52金属接触
70P型半导体基底 72重掺杂N型埋藏层
74N型非选择性磊晶层 76深隔离沟渠
78重掺杂P型通道停止区域 80绝缘层
84介电层 106侧壁子
86开口 88未掺杂多晶硅层
90重掺杂N型集电极接触区域 92二氧化硅层
94氮化硅层 96现场掺杂P型多晶硅层
98开口 100离子布植制程
102选择植入集电极 103硅锗磊晶层
104多晶硅层 105P型本征基极掺杂区
108发射极导电层 110自行对准硅化物层
112内层介电层 114金属接触
116金属接触 118金属接触
具体实施方式
请参照图6,图6为本发明的一种自行对准的双载子晶体管的结构示意图。本发明的双载子晶体管制作于一半导体基底70的主动区域I中,半导体基底70包含有一重掺杂N型埋藏层72与一N型非选择性磊晶(non-selective epitaxial)层74依序设于半导体基底70上,一深隔离沟渠76与一重掺杂通道停止区域78深入基底70中,以将每一个主动区域I电性绝缘并隔离,一介电层84形成于基底70的一预定区域内,一开口(未显示)形成于介电层84中且暴露部份磊晶层74,一重掺杂多晶硅层104形成于开口的侧壁上,且重掺杂多晶硅层104于开口中定义一自行对准基极区域,一本征(intrinsic)基极掺杂区105,经由自行对准基极区域植入于开口底部的磊晶层74中,一侧壁子106,设于重掺杂多晶硅层104上,且侧壁子106于开口中定义一自行对准发射极区域,以及一发射极导电层108,填入自行对准发射极区域内,并与本征基极掺杂区105接触形成一PN接面。
请参照图7至图11,图7至图11为本发明的一种自行对准形成一双载子晶体管的PN接面(PN junction)的方法示意图。如图7所示,本发明的双载子晶体管制作于一P型半导体基底70上,半导体基底70具有主动区域I,且重掺杂N型埋藏层72与N型非选择性磊晶硅层74依序设于半导体基底70上。本发明首先于主动区域I周围形成一深隔离沟渠76,且深隔离沟渠76穿越磊晶硅层74、埋藏层72直至半导体基底70中,接着进行一离子布植制程,将浓度约为1E13atoms/cm3的硼离子植入深隔离沟渠76中,以于深隔离沟渠76的底部形成一重掺杂P型通道停止区域78,最后再于深隔离沟渠76的侧壁与底部形成一绝缘层80,并于深隔离沟渠76中填入一二氧化硅或一未掺杂的多晶硅层,以形成一深沟渠隔离。其中,绝缘层80包含有一热氧化层与一氮化层。
接着于磊晶硅层74表面形成一介电层84,例如于磊晶硅层74表面进行一热氧化制程,以形成厚度约为5000埃的二氧化硅。然后于介电层84上形成一光阻层(未显示),并进行一微影与蚀刻制程以形成一集电极接触洞86。在去除光阻层后,接着进行一低压化学气相沉积(CVD)制程与一蚀刻制程,以于介电层84上沉积一厚度约为2500埃的未掺杂(undoped)多晶硅层88,并使未掺杂多晶硅层88填入集电极接触洞86中,再于介电层84上形成一图案化光阻层(未显示),以定义出一重掺杂N型集电极接触区域。随后进行一离子布植制程,将浓度约为5E15atoms/cm3磷离子植入暴露的未掺杂多晶硅层88中,并进行一热处理制程将植入的磷离子驱入磊晶硅层74中,以于集电极接触洞86下形成一重掺杂N型集电极接触区域90,使得未掺杂多晶硅层88中部分掺杂N型掺质不纯物,去除光阻层。其中,集电极接触区90域与埋藏层72形成一PN非整流(non-rectifying)接面。
如图8所示,进行一热成长或CVD制程以于介电层84上形成一厚度约为1300埃的二氧化硅层92,再于二氧化硅层92上形成一氮化硅层94以及一现场(in-situ)掺杂P型多晶硅层96。接着于多晶硅层96上形成一图案化光阻层(未显示),并进行一微影与蚀刻制程,以于多晶硅层96、氮化硅层94、二氧化硅层92及介电层84中形成一开口(opening)98,并暴露出部分磊晶硅层74。其中,现场掺杂多晶硅层96构成一延伸导电层,用来当作双载子晶体管的非本征(extrinsic)基极,主要作为电极电压控制之用。
如图9所示,进行一选择性离子布植制程100,以于开口98底部所暴露的磊晶硅层74中形成一选择植入集电极(selective implant collector,SIC)102。接着于基底70上均匀沉积一重掺杂P型多晶硅层(未显示),以覆盖开口98的侧壁与底部,其为植入浓度约为1E19至1E21atoms/cm3的硼离子的多晶硅层。然后进行一回蚀刻制程,去除部分的多晶硅层以暴露出开口98底部的磊晶硅层74,并残留部分的多晶硅层104于开口98的侧壁上,而多晶硅层104于开口98中定义出一自行对准基极区域。接下来,进行一离子布植制程,经由自行对准基极区域植入一浓度约为5E15atoms/cm3的硼离子,以于开口98底部的磊晶硅层74中形成一P型本征基极掺杂区105,作为基极区域。
如图10所示,于基底70上均匀形成一氧化层(未显示),并进行一回蚀刻制程,去除部分氧化层以暴露出开口98底部的磊晶硅层74,使得剩余的氧化层于多晶硅层104上形成一侧壁子106,且侧壁子106于开口98中定义一自行对准发射极区域。最后再于自行对准发射极区域中填入一发射极导电层108,使得发射极导电层108与本征基极掺杂区105接触以形成一PN接面。
如图11所示,进行一回蚀刻制程,以去除部分发射极导电层108。然后进行一微影与蚀刻制程,以图案化多晶硅层96,并进行一回蚀刻制程以去除部分氮化硅层94与氧化层92。最后再于发射极导电层108与图案化多晶硅层96上形成一自行对准硅化物层110,接着于基底70上形成一内层介电层112,并分别于发射极导电层108,集电极接触区域90以及非本征基极区域形成一金属接触,如图6所示,完成本发明的双载子晶体管的制作,
图12至图14为本发明另一实施例制作自行对准的异质接面双载子晶体管的方法示意图。如图12所示,一P型半导体基底70具有一主动区域I,且一重掺杂N型埋藏层72与一N型非选择性磊晶硅层74依序设于半导体基底70上。首先于主动区域I两侧形成一以形成一深沟渠隔离,接着于磊晶硅层74表面形成一介电层84,然后于介电层84上中形成一集电极接触洞86,将一未掺杂多晶硅层88填入集电极接触洞86中,再进行一离子布植制程,将磷离子植入暴露的未掺杂多晶硅层88中,并进行一热处理制程将植入的磷离子驱入磊晶硅层74中,以于集电极接触洞86下形成一重掺杂N型集电极接触区域90。于介电层84上依序形成一二氧化硅层92,一氮化硅层94以及一现场掺杂P型多晶硅层96,接着于多晶硅层96上形成一图案化光阻层(未显示),并进行一微影与蚀刻制程,以于多晶硅层96中形成一开口98,并暴露出部分磊晶硅层74。进行一选择性离子布植制程100,以于开口98中暴露的磊晶硅层74中形成一选择植入集电极102。
如图13所示,于基底上形成一硅锗(SiGe)磊晶层103,并覆盖开口98的侧壁及底部,接着于开口98中的硅锗磊晶层103上形成一氧化层(未显示),进行一离子布植制程,经由开口植入硼离子,以于开口98底部的磊晶层74中形成一P型本征基极掺杂区105。再于开口98中的硅锗磊晶层103上一氧化层以形成一侧壁子106,且侧壁子106于开口98中定义一自行对准发射极区域,于自行对准发射极区域中填入一发射极导电层108,使得发射极导电层108与本征基极掺杂区105接触以形成一PN接面。
如图14所示,进行一回蚀刻制程,以去除部分发射极导电层108以及硅锗磊晶硅层103,然后图案化多晶硅层96,氮化硅层94与氧化层92,再于发射极导电层108与图案化多晶硅层96上形成一自行对准硅化物层110。之后,于基底70上形成一内层介电层112,并分别于发射极导电层108,集电极接触区域90以及非本征基极区域形成一金属接触,完成本发明异质接面的双载子晶体管的制作,
简言之,本发明的自行对准的双载子晶体管,先利用重掺杂多晶硅层104于开口98中定义一自行对准基极区域以形成本征基极掺杂区105,接着再利用设于重掺杂多晶硅层104上的侧壁子106,定义一自行对准发射极区域以形成发射极区域,最后直接填入导电层以形成自行对准发射极区域108。因此本发明只需要形成一开口,就可以利用自行对准方法以形成发射极区域108/基极区域105与集电极区域102,进而制作一小尺寸且高效能的双载子晶体管。又本发明的非本征基极区域96为现场掺杂多晶硅层,因此无须利用热扩散制程来形成,因此可以精确的控制基极区域105与集电极区域102的接触面积,以降低非本征基极区域96下的集电极区域102与基极区域105间的接面电容。又因为本发明于硅锗磊晶层103形成之后,并没有使用到高温得热扩散制程,因此适用于异质接面的双载子晶体管。
相较于习知制作双载子晶体管的方法,本发明方法并不需要利用高温的热扩散制程以形成非本征基极区域,因此不但可以形成双载子晶体管,也可以用来形成异质接面的双载子晶体管的发射极区域/基极区域与集电极区域,同时达到简化制程步骤,降低制程成本的目的。
以上所述仅本发明的较佳实施例,凡依本发明申请专利范围所做的均等变化与修饰,皆应属本发明的涵盖范围。
Claims (17)
1.一种双载子晶体管,其特征是:包含有:
一基底;
一介电层,形成于该基底的一预定区域内;
一开口,形成于该介电层中且暴露部份该基底;
一重掺杂多晶硅层,形成于该开口的侧壁上,且该重掺杂多晶硅层于该开口中定义一自行对准基极区域;
一本征基极掺杂区,经由该自行对准基极区域植入于该开口底部的该基底中;
一侧壁子,设于该重掺杂多晶硅层上,且该侧壁子于该开口中定义一自行对准发射极区域;及
一发射极导电层,填入该自行对准发射极区域内,并与该本征基极掺杂区接触形成一PN接面。
2.如权利要求1所述的双载子晶体管,其特征是:该重掺杂多晶硅层植入浓度约1E19至1E21 atoms/cm3的硼原子。
3.如权利要求1所述的双载子晶体管,其特征是:该基底为一硅基底。
4.如权利要求1所述的双载子晶体管,其特征是:该基底为一磊晶硅基底。
5.如权利要求1所述的双载子晶体管,其特征是:该双载子晶体管另包含有一自行对准硅化物层形成于该发射极导电层上。
6.如权利要求1所述的双载子晶体管,其特征是:该双载子晶体管另包含有一选择植入集电极区设于该本征基极掺杂区下方的该基底中。
7.如权利要求1所述的双载子晶体管,其特征是:该双载子晶体管另包含有一延伸导电层电连接该重掺杂多晶硅层,且该延伸导电层设于该介电层上。
8.如权利要求7所述的双载子晶体管,其特征是:该双载子晶体管另包含有一氧化层及一氮化硅层介于该延伸导电层及该介电层间。
9.如权利要求7所述的双载子晶体管,其特征是:该延伸导电层由现场掺杂多晶硅所构成。
10.如权利要求1所述的双载子晶体管,其特征是:该介电层为一浅沟绝缘氧化层,且该预定区域为一浅沟绝缘区域。
11.一种异质接面双载子晶体管,其特征是:包含有:
一基底;
一介电层,形成于该基底的一预定区域内;
一开口,形成于该介电层中且暴露部份该基底;
一硅锗磊晶层,形成于该开口的侧壁及底部;
一侧壁子,设于该硅锗磊晶层上,且该侧壁子于该开口中定义一自行对准发射极区域;及
一发射极导电层,填入该自行对准发射极区域内,并与该硅锗磊晶层接触形成一PN接面。
12.如权利要求11所述的异质接面双载子晶体管,其特征是:该基底为一硅基底。
13.如权利要求11所述的异质接面双载子晶体管,其特征是:该基底为一磊晶硅基底。
14.如权利要求11所述的异质接面双载子晶体管,其特征是:该异质接面双载子晶体管另包含有一自行对准硅化物层形成于该发射极导电层上。
15.如权利要求11所述的异质接面双载子晶体管,其特征是:该异质接面双载子晶体管另包含有一选择植入集电极区设于该硅锗磊晶层下方的该基底中。
16.如权利要求11所述的异质接面双载子晶体管,其特征是:该硅锗磊晶层延伸出该开口外的该介电层上方。
17.如权利要求11所述的异质接面双载子晶体管,其特征是:该介电层为一浅沟绝缘氧化层,且该预定区域为一浅沟绝缘区域。
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AU6530298A (en) * | 1997-03-18 | 1998-10-12 | Telefonaktiebolaget Lm Ericsson (Publ) | Trench-isolated bipolar devices |
FR2764733B1 (fr) | 1997-06-11 | 2003-11-14 | Commissariat Energie Atomique | Transistor hyperfrequence a structure quasi-autoalignee et son procede de fabrication |
US6521974B1 (en) * | 1999-10-14 | 2003-02-18 | Hitachi, Ltd. | Bipolar transistor and manufacturing method thereof |
US6884689B2 (en) * | 2001-09-04 | 2005-04-26 | United Microelectronics Corp. | Fabrication of self-aligned bipolar transistor |
US6759731B2 (en) * | 2002-06-05 | 2004-07-06 | United Microelectronics Corp. | Bipolar junction transistor and fabricating method |
-
2002
- 2002-06-05 US US10/064,051 patent/US6759731B2/en not_active Expired - Lifetime
- 2002-12-27 CN CNB021590648A patent/CN1225796C/zh not_active Expired - Lifetime
-
2004
- 2004-05-14 US US10/709,569 patent/US6989557B2/en not_active Expired - Lifetime
- 2004-05-14 US US10/709,568 patent/US7297991B2/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
CN1466225A (zh) | 2004-01-07 |
US20030227071A1 (en) | 2003-12-11 |
US7297991B2 (en) | 2007-11-20 |
US6759731B2 (en) | 2004-07-06 |
US6989557B2 (en) | 2006-01-24 |
US20040227213A1 (en) | 2004-11-18 |
US20040195645A1 (en) | 2004-10-07 |
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