CN1222737A - Information recording method and apparatus and information recording medium - Google Patents

Abstract

In an information recording device, variable-speed reproduction by software control is to be enabled. To this end, the information recording device has an HDD for recording an audio/visual digital data stream with a logical sector as an accessing unit, and an AV micro-computer system 10. This AV micro-computer system 10 has, as a recording data unit, a fixed length of the audio/visual digital data stream corresponding to an integer number multiple of a frame length. The AV micro-computer system 10 allocates the recording data unit to a minimum number of the logical sectors that can record the recording data unit in its entirety, while stuffing dummy data in the remaining portion of a logical sector of the digital data stream.

Description

Information recording method and equipment and information recording carrier

The present invention relates to a kind of information recording method and equipment that is used on disc-shape recoding medium record audio and/or image digitization data stream, and a kind of recording medium.

Because hard disk drive has become the peripherals of personal computer gradually, the technological improvement in hard disk drive relates generally to as quickly as possible with the so-called discrete text data of high reliability random access.

In order to catch up with recent multimedia development, produced for the HDD of the inexpensive construction that allows so-called AVHDD system and the demand of host computer system, be stranded and except the AV data stream, for example, digital video (SD of DV system) standard with 28.6Mbps (megabit per second) transfer rate, or have audiovisual (AV) digital data stream that peak transfer rate is the MPEG 2 (moving picture expert group 2) of 15Mbps, and Random Access Data, can on disk, handle arbitrarily.

Lack a kind of information-recording apparatus now, this equipment considered with an AV digital data stream, and particularly compressed AV digital data stream is recorded in the situation on the disc-shape recoding medium, with variable speed reproducing.

Therefore, hope can record data, so that be unit with the logic sector, the performance of the disc-shape recoding medium by utilizing read/write data when recoding/reproduction AV digital data stream, can be convenient to be realized separately by the host computer side application software reproduction of variable velocity.

As the recoding/reproduction medium that is used for the AV digital data stream, recording tape is widely used.In order to realize the reproduction of all variable bit rates, need be controlled at the reproduction under the corresponding variable velocity by dissimilar hardware to being recorded in AV digital data stream on the tape.

Therefore; in order to be implemented in the reproduction under the various speed changes; in the AC data recording/reproducing apparatus; from beginning to design this hardware controls device; but; consider time, circuit scale or cost that exploitation is required, realize that the function that can select to change variable playback speed or continuously change variable playback speed is very difficult.

Therefore, an object of the present invention is to provide a kind of information recording method and equipment and a kind of recording medium, wherein, for example AV digital data stream can be recorded on the disc-shape recoding medium such as HDD, so that solve the variable speed reproducing of recorded stream.

Another object of the present invention provides a kind of reproducting method and equipment, makes playback speed can be set to a kind of speed of continuous variable.

In first aspect, the invention provides a kind of information-recording apparatus, be used for data are recorded in the recording medium of logic sector as access unit.This pen recorder comprises: input media is used to import the data that its regular length equals the integral multiple of a frame length; And control device, be used for giving the predetermined number of consecutive sector with the input data allocations.Specifically, with this pen recorder of the present invention, data are recorded on the recording medium of logic sector as access unit.Fixed-length data corresponding to the frame length integral multiple is used as a record cell.The present invention also provides control device, is used for record cell is distributed to the logic sector that record cell can be made the minimum number of as a whole record.

In yet another aspect, the invention provides a kind of information recording method, comprise that its regular length of input equals the data of the integral multiple of a frame length, and should import data allocations and give the predetermined number of consecutive sector.Specifically, use this information recording method of the present invention, data are recorded on the recording medium of logic sector as access unit.Fixed-length data corresponding to the frame length integral multiple is used as a record cell.The invention provides a controlled step, be used for this record cell is distributed to the sector that record cell can be made the minimum number of as a whole record.

In yet another aspect, the invention provides a kind of recording medium, by giving the predetermined number of consecutive sector with data allocations, the data that the length that is fixed equals a frame length integral multiple are recorded on this recording medium.Specifically, use this recording medium of the present invention, data are recorded on the recording medium of logic sector as access unit.Fixed-length data corresponding to the frame length integral multiple is used as a record cell.In the sector that data is recorded in the minimum number that record cell can be made as a whole record, record data are recorded on the recording medium.

According to the present invention, because can obtain a defined AV digital data stream based on the read command of logic sector sending one simply from host computer side, so the structure by host application software only, can easily in the AV digital data flow reproduction, realize such as put slowly, the reproduction of the variable velocity of static, quick retrieval, quick access or non-linear editing etc.

In reproduction equipment of the present invention, having an AV digital data stream that its regular length equals the frame length integral multiple is recorded in HDD and goes up and reproduce, be assigned to the logic sector of the predetermined quantity of HDD corresponding to the data of frame length integral multiple, and by only based on the Data Transmission Controlling of software, from any first sector of record cell, read this data in many ways, thereby obtain the recoding/reproduction function, do the representational role that can more easily realize variable velocity than existing method like this, the recoding/reproduction function designs in order to obtain by the data transmission by hardware controls and existing method is based on.

In addition, owing to can freely change the speed of variable speed reproducing, might control the speed of variable speed reproducing so continuously.

Fig. 1 shows the block scheme according to information-recording apparatus structure of the present invention.

Fig. 2 shows the block scheme according to the HDD structure of information-recording apparatus of the present invention.

Fig. 3 shows the block scheme according to the information-recording apparatus structure of a kind of practicality of the present invention.

Fig. 4 shows the block scheme according to the ATA adapter structure of information-recording apparatus of the present invention.

Fig. 5 has illustrated an example of the data that flow through information-recording apparatus of the present invention.

Fig. 6 has illustrated that the data transmission among the 2 row RAM regularly in information-recording apparatus of the present invention.

Fig. 7 shows the form of the HDD of record SD profile data stream.

Fig. 8 shows the HDD form of the SD specification data stream of record high compression.

Fig. 9 shows the HDD form of record SD specification data stream.

Figure 10 shows the process flow diagram of a series of reproduction steps in the information recording method of the present invention.

Figure 11 shows the process flow diagram of a series of images recording step in the information recording method of the present invention.

Figure 12 shows the mpeg signal based on GOP.

Figure 13 shows the block scheme of another modification of information-recording apparatus of the present invention.

Figure 14 shows the series of steps of the reproduction processes process of variable velocity in information regeneration method.

Figure 15 shows a series of jumps (skipping) step in information regeneration method.

Figure 16 shows a series of static (still) step in information regeneration method.

Figure 17 shows a series of (slow) the at a slow speed step in information regeneration method.

Figure 18 shows the step of a series of consulting in information regeneration method/at a slow speed.

Figure 19 shows the example of a kind of start unit in the display frame that is presented at transcriber.

Figure 20 shows the data structure that is used for transcriber.

Figure 21 shows the AAUX data structure that is used for transcriber.

Figure 22 shows the VAUX data structure that is used for transcriber.

With reference to the accompanying drawings, will describe a kind of information recording method of the present invention, a kind of information-recording apparatus and a kind of recording medium in detail.

As shown in Figure 1, this information-recording apparatus is a disk camera chain, wherein, a DV video camera 1 is arranged, be used to select the imaging picture of an object as the DV signal, as the DCR-TRV 7 that produces by Sony, this video camera is observed the DV standard, an AV microcomputer system 10, be used for handling the DV signal that receives from DV video camera 1, a pattern is provided with commander 8, is used for instruction mode is set to the RISC CPU 3 of AV microcomputer system 10, and display 7, be used to monitor the picture of DV video camera 1.

DV video camera 1 is such video camera, and it makes object image-forming by one such as lens or the such optical system of CCD, and outputs to the DV end with an encoder/decoder 1a with the result images signal encoding and with consequential signal.

AV microcomputer system 10 comprises: as a host bus 4 of the common bus that is used for information transmission; Interface buffer 2 is used to solve the information transmission between DV video camera 1 and the host bus 4; The HDD6 of recorded information thereon; And a so-called ATA (AT annex) adapter 5, be used to reconcile the information transmission between host bus 4 and the HDD 6.

Host bus 4 is parallel transmission-lines that are used for information transmission between the different parts of AV microsystem 10.

The audio frequency between interface (I/F) impact damper 2 conciliation DV video cameras 1 and the host bus 4 and/or the transmission of viewable numbers data stream (AV digital data stream).For example, interface buffer 2 is changed the transmission speed of AV digital data streams or is adjusted its transmission time.This interface buffer 2 has an inside being made up of 2 RAMS 2 row RAM 2a, and 2 RAMS wherein can alternately switch with adjustment information and transmit.

HDD 6 is disk sets of fixing, is used for writing down the digital data stream of input thereon.To explain the record format on the HDD 6 subsequently.ATA adapter 5 places between host bus 4 and the HDD 6, is used for the AV digital data stream from the parallel data of main frame bus 4 is converted to the data of HDD 6 available data format.

AV microsystem 10 comprises: RISC CPU 3, and it is the CPU (central processing unit) that concentrated message is handled; RAM 17, as volatile memory; With ROM 9, as nonvolatile memory.

RISC CPU 3 link to each other with host bus 4 be controlled at carry out in the current AV microsystem 10 information recording method a series of operations.This series operation for example is recorded on the ROM 9, so that read at any time and carry out.The computing machine that " RISC " expression minimizing instruction is provided with has wherein been simplified the elementary instruction of controlling CPU, instructs to reduce, thereby improves processing speed.

RAM 17 is the volatile memory in order to temporary transient storage data of linking to each other with host bus 4.ROM 9 is the nonvolatile memories that link to each other with host bus 4, and has existence initialize program or analog wherein.In this ROM 9, write down a control routine relevant with the sequence of operations of information processing method.

Monitor 7 has a display screen and a loudspeaker 7a, and exports image and the voice that obtained by DV video camera 1.By DV video camera 1 or by the reproduction of AV microsystem 10, will be recorded in image on the AV microsystem 10 and voice output to monitor 7.

Will be explained in the flowing of individual input signal of writing time below.At first, by the high efficient coding that is undertaken by the encoder/decoder of bearing video compress, the picture signal that is converted to video electrical signal by DV video camera 1 is encoded.This voice data constitutes an AV digital data stream of being made up of the DIF piece that defines in the DV system through multipath conversion.This AV digital data stream defines as standard by 3 technical manuals, these three technical manuals are: be applicable to single-definition (the standard definition that handles high-definition television (HDTV), SD), high compression (high-compression, SD) and high definition (highdefinition, HD).

The SD technical manual provides with the regular length of 119.2K byte compresses frame data stream.When the HD technical manual provided a frame to be the 238.4K byte, it was the 59.6K byte that high compression SD technical manual provides a frame.

This AV digital data stream is sent to the host bus 4 that links to each other with RISC CPU 3 by interface buffer 2.This AV digital data stream that is sent to host bus 4 has the data transmission of being controlled by the software of RISC CPU3, and this data stream is written on the HDD 6 based on the sector by ATA adapter 5.

With reference to figure 2, the structure of the HDD 6 that the explain information treatment facility is provided.

Rotating drive unit 121 is by axle motor 121A and be applicable to that the sensor 121B that detects its rotating speed is formed, and is configured for rotational head 122 (memory storage).The head portion 123 that is constituted be used for writing on tracer signal on the disk 11 and the signal record that is used for reading at disk 122.

In recording process, recoding/reproduction signal processing circuit 124 is carried out chnnel coding (record coding) on tracer signal, these tracer signals are written in recording process on the disk 122, simultaneously, playback duration the play signal of reading from disk 122 is carried out with write down during opposite conversion so that error detection and error recovery.The arm of magnetic head is supported in 125 controls of head arm Drive and Control Circuit, is used for magnetic head is moved to the predetermined track position of disk 122.The Spindle Motor 121A of rotation axis Drive and Control Circuit 126 drive controlling rotating drive unit 121.

Magnetic Disk Controller 127 controlling recording/reproducing signal treatment circuit 124, head arm driving circuit 125 and rotation axis Drive and Control Circuit 126.The disk interface unit 131 of forming Magnetic Disk Controller 127 is carried out in recoding/reproduction signal processing circuit 124, head arm Drive and Control Circuit 125 with rotation axis Drive and Control Circuit 126 on one side, and handles at the disc format controller 133 and the interface between the internal system bus of another side.

Disc format controller 133 is carried out the address translation control of the address translation of data on disk 122 according to being fixed on an address conversioning unit 133-1 on the storer, simultaneously, also carries out the format of disk 122.Data in magnetic disk timing control circuit 132 is delivered to recoding/reproduction signal processing circuit 124 with the clock signal corresponding with rotating speed.Data bus built-in system timing controller 134 is delivered to clock signal other parts of Magnetic Disk Controller 127.

Multiplexed data that provide by data FIFO 136 of multiplexer/demultiplexer 138 and from the order of register 114a, thereby will be routed to ATA adapter 5 through multiplexed data, perhaps will be decomposed into data and register command by the external data multichannel that ATA adapter 5 sends.

Data FIFO (first in first out) 136 is configured for the memory data that the order maintenance is provided by multiplexer/demultiplexer 138, and data are outputed to internal system bus 135 with the order that remains on storer, system bus 135 sends the data that remain in proper order in the storer internally, and data FIFO 136 also is used for the data that storer keeps are sent to multiplexer/demultiplexer 138.The register 114a that constitutes is used for the state that keeps order or receive from multiplexer/demultiplexer at storer, and should order or state outputs to internal system bus 135, and order or state that register 114a also keeps system bus 135 internally to transmit in storer, and should order or state is sent to multiplexer/demultiplexer 138.

CPU 142 is configured for according to the control program that is stored among the ROM 141 and controls different parts, thereby the Communication Control between drive system and the main frame is carried out in the driving of recording/reproducing data, control-driven system and according to different disk parameters, fill order or executing state.RAM 140 is configured for and keeps CPU 142 to handle required data and other data in storer.

When providing data and record order by interface 113 from the outside, multiplexer/demultiplexer 138 is separated data from record order, data are delivered to data FIFO 136, will order and state is delivered to register 114a.Reproduce order if send data from the outside by interface 113, this order is routed to register 114a so.A read/write host interface 143 is carried out the interface relevant with main frame and is handled.

An object lesson with reference to figure 3 explain information recording units.In this concrete example, AV microsystem 10 modules in the information-recording apparatus of Fig. 1 are separated into an interface buffer plate 19 and a RISC CPU board 20.Fig. 3 shows the concrete interface buffer plate 19 and the inner structure of RISC CPU board 20.

Interface buffer plate 19 has a network interface 11, is used for carrying out interface operation with network and 2 row RAM 2a, to adjust data transmission.Interface buffer plate 19 links to each other by host bus 4 with RISC CPU board 20.

Network interface 11 is connected to network and 2 groups of RAM 2a from DV video camera 1, is used to connect the data that enter by network.This 2 row RAMS has the terminal of oneself, and its other terminal links to each other with host bus 4 with network interface 11 respectively, a RAM 33 and the 2nd RAM34 of 2 row RAMS, change by first switch 31 and second switch 32, thereby allow to write in turn and read so that adjust the data transmission.

Interface buffer plate 19 has the control ram register 14 and the control I/O register 15 that is used to control I/O that are used to control each RAM.

Control ram register 14 is to link to each other with host bus 4 to be used for the volatile register of temporary transient data storage with control I/O register 15.

PISC CPU board 20 has one to have: PISC CPU 3, and it is a CPU with instruction group of minimizing; Nonvolatile memory ROM 9 and a volatile memory SRAM 17.RISCCPU 3, ROM 9 link to each other with host bus 4 with SRAM 7.

ROM 9 can be the product such as IBM.In a single day SRAM 17 is the RAM that keep data, promptly just writes to keep these data up to outage, so do not need to write once more always.The capacity of ROM can be, 2MB for example.

RISC CPU board 20 has an ATA adapter 5, a HDD 6 and a quartz (controlled) oscillator 21.

The ATA adapter 5 that is referred to as IDE is the interfaces that directly host bus 4 are coupled to HDD 6.ATA adapter 5 and HDD 6 are by described as American National Standards Institute, and the ATA modular system that is referred to as the intelligent drives electronic equipment (EIDE) of enhancing interconnects.This EIDE is the IDE compatibility interface, and the peak transfer rate that has each message transmission rate is the pattern of 33M byte per second.The data-transmission mode of for example enough 13.3M byte per seconds.

In the process that all data sector that are arranged on the disk are carried out the sector addressing, by all data sector are handled as logical block, EIDE has the system of an access sector that has this logical block number (LBN) (LBA), in addition, routinely, the system of this access sector also has cylinder/magnetic head/sector number.

HDD 6 is fixed magnetic-disk drives of a record AV digital data stream, and may be that for example the disk diameter is 3.5 inches HDD of 3.5 inches.

Quartz (controlled) oscillator 21 is the oscillators that the reference signal of predetermined frequency is provided.In the drawings, shown quartz (controlled) oscillator 21 produces the reference signal of the 28MHz that is sent to RISC CPU 3.

Present embodiment relates to recoding/reproduction AV numerical data under the control of ATA agreement, and the ATA agreement is used the hard disk that the ATA system interface is arranged.The circuit structure of ATA adapter 5 will be with reference to figure 4 simply to its explanation, wherein, ATA adapter 5 and RISC CPU and hard disk interconnection with ATA system interface, and as required in the ATA agreement, after the generation of the address signal that is exclusively used in ata device produces, adapter 5 access wait control signals, look-at-me and data byte buffer control signal.

The ATA adapter 5 of present embodiment uses an external vector interrupt system, so that allow a plurality of devices to arrive the host bus 4 of CPU.

ATA adapter 5 portion within it has first ata interface 101 and second ata interface 111.First ata interface 101 portion within it has address decoding circuitry 102, access to wait for unit 104 and bidirectional buffer 103.

From address bus 4a feed-in first ata interface 101 of the host bus 4 that has 32 bit address data (being equivalent to the full address data), so that selected cell 102a, selected cell 102b and selected cell 102c are selected.Selected cell 102a selects an ata interface address, and simultaneously, selected cell 102b selects the ATA data address of the digital data of 16 bit lengths, and device and selected cell 102c select 8 and deposit the ATA register address that data are set.

From the address decoder data, produce various control signals, and make it consistent with the ATA attachment unit interface of hard disk.From the input signal of CPU is to be equivalent to 32 address signal, the read and write control signal of CPU, vector to pick up control signal and wide upper and lower position (order) byte of 16 bit data bus, and wherein 16 bit data bus width have the data-bus width that the data bus that had facing to ATA adapter 5 from CPU by CPU is provided with.

The address signal that is equivalent to 32 means that in fact address signal has 32 address information in CPU.This address signal can comprise a kind of like this address signal: promptly, for some upper bytes of 32 bit address buses, this address signal has area part zone, the definite address access range as the regional selecting address signal that is used to select, and selection is the whole access address conversion from CPU.

Second ata interface 111 portion within it has a priority encoder 112 and an external vector to produce circuit 113.

As I/O with respect to an ATA standard signal of hard disk, first ata interface 101 comprises an address decoding circuitry 102, and this circuit is used for signal full address, 32 equivalent addresses with RISC CPU and is decoded to data register in the optional ata device in address and relevant register and the ata device.When OPADD signal during to ata device, corresponding to the low order address ADR[3 of 32 equivalent host buses ... 1], address bit moves one, address signal output CS 0-, CS1-, DA[2 ... 0] is input to ata device.

First ata interface 101 also comprises an access wait circuit 104, this circuit makes the RISC CPU of high speed processing speed be adapted to timing with respect to the ATA agreement of control input signals, this control input signals is except that the read/write signal that comprises from the IOR-of CPU side and IOW-, also be included in an access wait request signal IORDY from the ata device to the host CPU in the data transmission procedure, and an Interrupt Process request signal INTRQ in control register setting or the data transmission and processing that is controlled at disk drive in the ATA standard agreement flow to.

Access waits for that circuit 104 comprises that also being used for the vector that a vector reads signal reads signal input end, it is vector index State Control or gating signal that this vector reads control signal, is used for waiting for by producing the access that is used for the vectorial logarithmic data rise time at the external vector generative circuit 113 of explanation subsequently in response to the CPU of the external vector logarithmic data of external interrupt request when the retrieval.

When the data input and output, with respect to the controll block register and the command block register that in ATA standard hard disk drive device, are provided, for being used for low data byte [7 according to the ATA agreement read/write register value of setting ... 0] and the high position data byte DD-[15 that during the data of 16 words transmit, uses with the low data byte ... 8] provide input and output.

Second ata interface 111 is external vector interrupt circuits, and portion has within it: priority encoder 112 is used to be provided with the priority of Interrupt Process of CPU that those is submitted to the device of interrupt request; With external vector generative circuit 113, produce vectorial logarithmic data by address date according to the priority information that submits to the device of interrupt request, so that the vectorial logarithmic data that is produced delivered to the CPU that carries out access program by program.

Provide based on the interrupt request singal of installing to priority encoder 112, deliver to CPU so that will allocate in advance to each priority sequence that interrupts importing from those devices.The interrupt request singal INTRQ that priority encoder 112 receives from the ATA standard disk drive, and the priority of this disc driver is encoded to, 4 interrupt level signal IRL 0-to IRL 3-for example, and will be encoded signals output to the control bus 4c of host bus 4, make it in CPU, to be retrieved.

A read signal that a vectorial read strobe signal (state control signal) also is provided and sends to outside vector generated circuit 113 by the above-mentioned interrupt level signal of distributing to the device of obeying interrupt request of CPU response, also provide the interrupt priority level number of CPU output, in response to interruption priority signal IRL 0-to the IRL 3-that is in this state after the CPU internal conversion.This interrupt priority level number enters low 4 ARD[3 ... 0].

In the process of sending vectorial read strobe signal (state control signal), with low 4 interrupt priority level numbers that are used as from CPU of address bus.These 2 input signals and the input of low 4 bit address are offered external vector generative circuit 113, with output as the external vector of byte length in lower 4 of data bus, so that allow the CPU retrieval to distribute to the external vector logarithmic data of institute's screening device.

32 RISC CPU and the hard disk drive with this ATA system interface link to each other in mode as mentioned above.

In the present embodiment, information-recording apparatus uses centralized displaying type PC as mode initialization commander 8.According to the explanation on the PC display board, can carry out " record ", " broadcast ", " putting slowly ", " static " and " search " these operations by mode initialization commander 8 at least.

Explain the sketch that in this information-recording apparatus, flows through data with reference to figure 5.The encoder/decoder 1a of DV video camera 1 and the HDD 6 of EIDE standard are by network interface and 2 above-mentioned row RAM 2a exchange messages.By with HDD 6 and 2 row RAM 2a between transmission channel the RISC CPU 3 controlled encoders/demoder 1a, network interface and the HDD 6 that link to each other between information transmission.

According to the transfer rate of IEEE 1394 standards with 28.6Mbps, the data that the AV numerical data is streamed are transferred to 2 row RAM 2a by network interface from encoder/decoder 1a.The data that enter HDD 6 from 2 row RAM2a are with the transfer rate transmission of 34Mbps and be written into HDD 6.

On the contrary, the data of reading from HDD 6 pass to 2 row RAM 2a to write fashionable identical 34Mbps transfer rate with it.According to the transfer rate of IEEE 1394 standards with for example 28.6Mbps, the data that the AV numerical data is streamed pass to encoder/decoder 1a by network interface from 2 row RAM 2a.

Be noted that in the message transmission rate on the transmission channels between encoder/decoder 1a, network interface and the 2 row RAM 2a and be different from message transmission rate on the transmission channels between HDD 6 and the 2 row RAM 2a.

To input data rate height and the video data continuity of HDD 6, and to or high like this but show higher data continuity from the I/O data rate of network interface.

2 row RAM 2a have two frame memories, i.e. first frame memory 33 and second frame memory 34, and they are switched so that alternately carry out and write and read, to adjust the difference in the message transmission rate.

In other words, if data write one of them frame memory of 2 row RAM 2a in the time interval of a frame, and in a frame time interval, from another frame memory, read this data, from storer, write or read out the continuity that keeps data by in frame time interval, finishing so, although the continuity of message transmission rate or data is different, still can guarantee the continuity of data transmission.

Explain the data transmission procedure of arranging among the RAM 2a 2 with reference to data transmission timing block diagram shown in Figure 6.

Information is transferred between the data reading duration of network interface and: 1 transcoder/demoder 1a from HDD 6 in, shown in arrow A among the 2 row RAM 2a, transmit data.

In the first frame F0, in the first frame RAM 33, write data A1, simultaneously sense data B0 from the second frame RAM34.Be noted that respectively by label letter A and B and represent to be recorded in data among the first frame RAM 33 and the 2nd RAM 34.

RISC CPU 3 is the monitored state register always, and when with box lunch data A1 being written to first frame RAM33 end and when sense data from the second frame RAM 34 finishes, CPU status register respectively is set to " 1 " and " 0 ".Because it is short to write the required time of the required time ratio of data A1 sense data B0 in the second frame RAM 34 in the first frame RAM 33, when writing of data A1 finished and subsequently when reading of data B0 finished, status register was set to " 1 " and " 0 " respectively.

When status register was set to " 0 ", the mode of operation of first frame memory 33 and second frame memory 34 was changed so that data are read from first frame memory 33 and write in second frame memory 34.

Therefore, in following the first frame F0, the first frame F1 thereafter closely, the data A1 that writes the first frame F0 is read from first frame memory 33, simultaneously, data B1 is write second frame memory 34.

Shown in the arrow 42 of Fig. 6, with data B1 write first frame memory 33 and with data A1 since second frame memory 34, read when frame pulse during from low level to high level under status register " 0 " state.

This frame pulse decays after the schedule time as the rise time in experience.

In being right after the second frame F2 of the first frame F1, the data B1 that writes second frame reads from second frame memory 34, and simultaneously, data A2 writes first frame memory 33.

In the first frame F1 and the second frame F2, be used for writing and the time of reading identical with at first frame.

During writing, at CPU status register is set to " 1 " afterwards from " 0 ", CPU 3 writes and the corresponding 19.2k byte of a frame among the RAM.Between the data reading duration, CPU 3 deposits number with state and is set to " 0 " from " 1 " after finishing read operation.

Above-mentioned frame data as an overall flow are A0, B0, A1, B1, A2, B2, A3, B3, A4, B4 ...By adjusting the readout time and the write time of frame data in first frame memory 33 and second frame memory 34, change transmission speed, and the frame data of transmission through adjusting.

In ablation process, when information when encoder/decoder 1a is transferred to HDD 6, data transmit in 2 row RAM 2a as shown by arrow B.

In the first frame F0, data A1 writes first frame memory 33, and data B0 reads from second frame memory 34 simultaneously.

RISC CPU 3 is the monitored state register always, reads when finishing and when data A1 write 33 end of first frame memory, CPU was set to status register respectively " 1 " and " 0 " with convenient data B0 from second frame memory 34.Because sense data B0 required time is shorter than data A1 is write the required time of first frame memory 33 from second frame memory 34, so when reading of data B0 finished and when writing of subsequently data A1 finished, status register is set to " 1 " and " 0 " respectively.

When status register was set to " 0 ", the running status of first frame memory 33 and second frame memory 34 changed so that from first frame memory 33 sense data and in second frame memory 34, write data.

Therefore, in being right after the first frame F1 of the first frame F0, the data A1 that writes the first frame F1 reads from first frame memory 33, simultaneously, data B1 is write second frame memory 34.

Data B1 writes first frame memory 33 and data A1 is to rise to high level (shown in the arrow 42 of Fig. 6) when frame pulse from low level, beginning when being in " 0 " state at status register from reading second frame memory 34.

This frame pulse decays after the schedule time as the rise time in experience.

In the second frame F2 that follows the first frame F1, the data B1 that writes first frame reads from second frame memory 34, writes data A2 simultaneously in second frame memory 33.The first frame F1 and the second frame F2 write and read the used time with used identical in the first frame F0.

In ablation process, CPU 3 with status register when " 0 " is set to " 1 ", CPU3 writes the 19.2K byte corresponding to the frame among the RAM.For sense data, CPU 3 is set to " 0 " with status register from " 1 " after end is read.

Will be explained in the form of the recording medium of record AV digital data stream on it below.

Record format as the HDD of recording medium is to consider the sector 24 of 512 bytes is constructed as a unit.If the SD specification of the SD signal of DV system conformance with standard resolution, the AV digital data stream of 119.3K byte is a frame so.Therefore, from beginning part corresponding to continuous 233 sectors of 119.2K byte, continuous recording AV digital data stream, and in the marginal portion 23 of the last sector that does not write the AV digital data stream, filled data arbitrarily.

If the DV system is the system corresponding to the high compression SD specification of high compression SD signal, the leading end of the 59.904K byte area that constitutes from the sector 24 by 117 512 continuous bytes of the DV signal of 59.6K byte one frame of high compression SD specification is by continuous recording so.Wherein, the marginal portion 23 that does not write the last sector of AV digital data stream is filled.That is, write down the AV digital data stream of high compression SD specification as a unit with 117 sectors.These 117 sectors are made up of part 22 that writes the AV digital data stream and the marginal portion 23 that is filled.

If the DV system is the system corresponding to the HD specification of HD signal, so, the DV signal of 238.4K byte one frame of HD specification from the leading end of the 238.592K byte area that constitutes by 466 512 continuous byte sector 24 by record continuously.The marginal portion 23 that does not write the last sector of AV digital data stream is filled, and just, writes down the AV digital data stream of HD specification as a unit with 466 sectors.These 466 sectors are formed by the part 22 that writes the AV digital data stream with through the marginal portion 23 of filling.

The sequence of operations process of the information recording method that the reference flow sheet explanation is above-mentioned.

When the HDD of the AV digital data stream of the DV system of reproducing its SD specification that goes up with good grounds above-mentioned record format record, use sequence of operation as shown in figure 10.

At step S11, read the 0th frame of AV digital data stream.Under the DV of SD specification system situation, write down each frame of AV digital data stream as a unit with 233 sectors, so that if the start of record of AV digital data stream is the S sector, 233 sector zone corresponding to the AV digital data stream begin to be read out from this S sector so.Then, processing procedure forwards step S12 to.

At step S12, read first frame of AV digital data stream.Here, from begin to read zone corresponding to (S+233) sector of the record end points of the 0th frame of AV digital data stream and then corresponding to 233 sectors of AV digital data stream.

By the identical operations order, read from the DV signal of second frame to the (n-2) frame.Then, processing procedure forwards the step S13 corresponding to (n-1) frame to.

At step S13, read the content of (n-1) frame of AV digital data stream.Here, from begin to read 233 sector zone corresponding to (S+223* (n-1)) sector of the sector of the record end points of (n-2) frame of AV digital data stream and then corresponding to a frame AV digital data stream.Then, processing procedure forwards step S14 to.

At step S14, read n frame AV digital data stream.Here, begin to read 233 sector zone from (S+233 * n) sector corresponding to a frame of AV digital data stream corresponding to the sector of the record end points of (n-1) frame that is right after the AV digital data stream.Because finished reading like this from the 0th frame to n frame AV digital data stream, so, the sequence of operation that is used to reappear the AV digital data stream stopped.

With reference to the process flow diagram of Figure 11, the DV system according to above-mentioned SD specification explained is used for the AV digital data stream is recorded in sequence of operation on the HDD.

At first step S21, write the 0th frame of AV digital data stream.At this, begin to write content corresponding to 233 sector zone of a frame AV digital data stream of SD specification from leading end as the S sector of the starting end of the home record of AV digital data stream.Then, processing procedure is to step S22.

At step S22, write first frame of AV digital data stream.That is, begin first frame recording of AV digital data stream 233 sectors corresponding to a frame of SD signal from (S+233) sector corresponding to the sector of the record end points of the 0th frame that is right after the AV digital data stream.

Write down in an identical manner from the AV numerical data stream information of second frame to the (n-2) frame.Then, processing procedure forwards step S23 to.

At step S23, write (n-1) frame of AV digital data stream.At this, (n-1) content frame of AV digital data stream is recorded in 233 sectors of (n-1) frame.Then, processing procedure forwards step S24 to.

At step S24, write the n frame of AV digital data stream.At this, with the n frame recording of AV digital data stream in 233 sectors of n frame.Fashionable when the n frame of AV digital data stream is write, the sequence of operation of record AV digital data stream just is through with.

In above-mentioned explanation, given SD specification is for the DV system is described.Be noted that by read/write cell being changed into can handle high voltages the contract AV digital data stream of SD specification of 117 sectors, and by the read/write cell among the HDD being changed into the digital data stream that the AV of HD specification can be handled in 466 sectors.

The sequence of operation of above-mentioned information recording method is explained together in conjunction with the operating process of the various parts of above-mentioned information-recording apparatus.

In reconstruction processes, under the software control of program as shown in Figure 10,, alternately these data are write among the 2 row RAM 2a of interface buffer 2 through ATA adapter 5 and host bus 4 by reading the AV digital data stream from HDD 6 respective sectors; And, can obtain an AV digital data stream in real time by alternately on the basis of frame pulse, reading this data.The dynamic image that reproduces is sent to the high performance encoder/decoder 1a of DV video camera and it is presented on the monitor 7.Keep voice data in the same manner, so that from the voice data of loudspeaker (SP) 7a acquisition through reproducing by encoder/decoder 1a transmission.

If by the software set LBA (Logical Block Addressing) LBA on the main frame side HOST, can realize reading arbitrarily/write operation based on the sector of HDD 6 so, so that, if by above-mentioned record format record AV digital data stream, and when reading the particular sector of this data stream on writing it or from 2 row RAM 2a of interface buffer 2, reading, can save unnecessary padding data.By controlling the sector of reading changeably, and, can realize the reproduction of variable velocity individually by the software control of RISC CPU 3 by in the 2 row RAM 2a of host bus 4 with sense data write buffer 2 by software.

Pattern is provided with commander 8 will deliver to RISC CPU 3 through RS-232C corresponding to the ID of the control routine of recoding/reproduction/variable speed reproducing pattern.In RISC CPU 3, on the basis of these instruction devices ID data, start the read/write of relevant application software item with control HDD 6 by drive software.

Be noted that the asynchronous system that makes digital interface IEEE 1394 used in this invention can make the mode command signal enter RISC CPU 3 from the outside.Certainly, RISC CPU 3 can be the different CISC with a series of orders of instruction group with minimizing commonly used.

In the AV of present embodiment microsystem 10, as shown in Figure 1, used a single form, and 2 row RAM 2a of interface buffer wherein 2, register, RAM 17 and the ROM 9 of HDD 6 carry out conversion as a whole in the primary memory of RISC CPU 3.Allow so individually the data (AV data stream and IT data) that provided freely to be read or write from HDD 6 by the Data Transmission Controlling software of RISCCPU 3.

In the above-described embodiment, according to the DV standard record data being fixed in the frame is on the data length of basis record.In addition, as shown in figure 12, can will be fixed in the image sets of being formed by the 512KB/1024 group (GOPS) as the mpeg signal of image or Speech Signal Compression, and with this fixed-length record according to mpeg standard, be compressed than control.

Just, although the above embodiments are the systems at the reproduction of the variable velocity that realizes having good accessibility (accessibility) by a plurality of logic sector recording signals that use hard disk, use a DV video camera, although have the device that mpeg signal is provided, can realize having the reproduction of the variable velocity of fine access speed equally, when the same system of one of hope structure and above-mentioned AV microsystem 10, if use a device that receives and export mpeg signal to replace the DV video camera, can control the output GOP of mpeg signal and/or the maximum quantity of I frame data they are fixed, and adjust this number and make it equal the integral multiple of hard disk logic sector quantity.

With reference to Figure 13, the information-recording apparatus that is used for the recoding/reproduction mpeg signal is composed as follows: the tuner 151 of antenna 150 feed signals of the video and audio signal by receiving simulation system; The vision signal that enters tuner 151 is converted to the A/V change-over circuit of digital signal; Reception is from the ntsc decoder 153 of the vision signal of the digital display circuit of A/V change-over circuit 152; Reception is converted to MPEG 2 demoders 154 of the vision signal of baseband signal by ntsc decoder 153; With the multiplexer 155 that receives the digital display circuit mpeg data.

Equally, this information-recording apparatus comprises an A/V change-over circuit 156, receives the sound signal that passes to tuner 151, and receives MPEG 1 scrambler 157 that is converted to the sound signal of digital system signal by A/V change-over circuit 156.

The signal of NTSC National Television Systems Committee (NTSC) system that for example receives by antenna 150 is offered tuner 151.This tuner 151b receives and detects the video and audio signal that receives by antenna 150.Tuner 151 outputs to A/V change-over circuit 152 with vision signal after testing, simultaneously audio signal output is arrived A/V change-over circuit 156.

152 pairs of vision signals from video inputs or tuner 151 of A/V change-over circuit are carried out the A/D conversion to produce video data.The A/V change-over circuit 152 for example video data of TSC-system formula outputs to ntsc decoder 153.

To offer ntsc decoder 153 from the video data of the TSC-system formula of A/V change-over circuit 152.The video data of these ntsc decoder 153 expansion inputs is to produce baseband signal.Ntsc decoder 153 outputs to MPEG 2 scramblers 154 through the end points 1 of switch 158 with baseband signal.

154 compressions of MPEG 2 scramblers are from the baseband signal of ntsc decoder 153.Mpeg 2 encoder 154 is converted to the baseband signal of input the numerical data of MPEG 2 systems simultaneously.MPEG 2 scramblers 154 are encoded the baseband signal of input with predetermined ratio of compression, so that data capacity is corresponding to an integral multiple of the logic sector number of hard disk.Just, MPEG 2 scramblers 154 are realized compressed encoding, so that the picture signal of input will be a data capacity corresponding to the integral multiple of hard disk logic sector number.Can control ratio of compression equally, so that be compressed to the integral multiple that the data capacity of maximum of the coded data of 1 frame will equal hard disk logic sector number.

Also can will offer MPEG 2 scramblers 154 from the baseband signal of MPEG 2 demoders 160 by the end points 2 of switch 158 and the end points 2 of switch 162.These MPEG 2 scramblers 154 are encoded to the baseband signal from MPEG 2 demoders 160 with a predetermined ratio of compression.

Will be by tuner 151 at the audio signal output of antenna 150 input signals to A/V change-over circuit 156.This A/V change-over circuit 156 is converted to the sound signal A/D of input voice data and this voice data is outputed to MPEG 1 scrambler 157.

MPEG 1 scrambler 157 will be from the video data of MPEG 2 scramblers 154 and multiplexed from the voice data of MPEG1 scrambler 157.If video data and voice data are respectively V and A, so much path multiplexer 155 during with the GOP of mpeg signal unit of intercropping be VAVAVA along the time shaft packed data ... to produce a digital data stream.This multiplexer 155 will output to interface buffer 2 through the digital data stream of multiplexed mistake.

To offer multiplexer 155 from the digital data stream that is recorded on HDD 6 hard disks of interface buffer 2.This multiplexer 155 will be divided into video data and voice data from the digital data stream that interface buffer 2 sends.This multiplexer 155 outputs to multiplexer 169 through the end points 2 of switch 171 with the video data of telling, and end points 1 this vision signal of output through switch 159 arrives MPEG2 demoder 160 simultaneously.Multiplexer 155 separates the voice data that obtains to multiplexer 169 through a delay circuit 170 output, exports this voice data simultaneously to MPEG 1 demoder 161.

Current information-recording apparatus also comprises the antenna 166 that is used to receive the mpeg system numerical data, one group of top box (a set top box, STB) 167, digital I/F circuit 168, a multiplexer 169 and a delay circuit 170.

The numerical data of for example mpeg system is offered antenna 166.Antenna 166 will output to STB 167 as the numerical data that the RF signal receives.

STB through antenna 166 receiving digital datas of front end to detect the numerical data that has received.STB167 also incites somebody to action to the numerical data descrambling of scramble, and the numerical data of descrambling outputs to digital I/F circuit 1 68.

To offer STB 167 from the numerical data of digital I/F circuit equally.STB 167 has a built-in mpeg decoder.By this MPEG, demoder STB 167 will decode from the numerical data of digital I/F circuit 168, and the video and the voice data of compression expanded to picture signal and voice signal.

Numeral I/F circuit 168 comprises a Physical layer/linking layer treatment circuit, and with for example changing the numerical data of handling from STB 167, and the signal that will handle outputs to multiplexer 169.Numeral I/F circuit 168 output digital datas are to STB 167.

Multiplexer 169 will be separated into video data and voice data from the numerical data of digital I/F circuit 168.This multiplexer 169 will output to MPEG 2 demoders 160 through the video data as a result that the end points 2 of the end points 1 of switch 171 and switch 159 is separated.Multiplexer 169 is gone back outputting audio data to delay circuit 170.

To offer multiplexer 169 by switch 171 and with voice data through delay circuit 170 from the video data of multiplexer 155.The video of 169 pairs of inputs of multiplexer and voice data carry out multiplexed, so that will output to digital I/F circuit 168 through multiplexed data.

The voice data that delay circuit 170 is adjusted from multiplexer 169 makes it time-delay, these delay circuit 170 delay process voice datas, so as the voice data of adjusting input with respect to the mistiming of the video data of input and the data crossed of delay process output to multiplexer 155.

Have only voice data to be sent to delay circuit 170 in video data that separates by multiplexer 155 and the voice data.This delay circuit 170 is adjusted voice data, makes it output to multiplexer 169 with respect to the video data time-delay and with this voice data.

Information-recording apparatus comprises that the end points 2 by switch 159 is provided MPEG 2 demoders 160 of video data, receives and to separate MPEG 1 demoder 155 of the voice data that obtains, end points 1 by switch 161 by multiplexer 155 and receive by the NTSC scrambler 163 of the video data of MPEG 2 demoders 160 decodings, receive by the D/A change-over circuit 164 of NTSC scrambler 163 coded datas and receive the D/A change-over circuit 165 of the voice data of being decoded by MPEG 1 demoder 161.

End points 1 by switch 159 offers MPEG 2 demoders 160 with video data, this video data is by the digital data stream of data transmission software playback record on HDD 6 by RISC CPU 3, and separated by the digital data stream that multiplexer 155 will have been read through ATA adapter 5, host bus 4 and interface buffer 2 and obtain.The inputting video data that 160 expansions of MPEG 2 demoders have been compressed.End points 2 by switch 169 will offer MPEG 2 demoders 160 from the video data of multiplexer 169.The inputting video data that 160 outputs of MPEG 2 demoders have been expanded is to switch 162.

When the video data from multiplexer 169 enters MPEG 2 demoders 160 or when the video data from multiplexer 155 entered MPEG 2 demoders 160, gauge tap 159 linked to each other it respectively with end points 2 or 1.

When the video data from MPEG 2 demoders 160 outputs to switch 158 or when the video data from MPEG2 demoder 160 outputed to NTSC scrambler 163, gauge tap 162 linked to each other it respectively with end points 2 or 1.

End points 1 by switch 162 will offer NTSC scrambler 163 by the video data of MPEG 2 demoders 160 decodings.NTSC scrambler 163 is according to the video data of NTSC system compresses input, so that the video data of compression is outputed to D/A change-over circuit 164.

D/A change-over circuit 164 will be converted to vision signal from the video data of NTSC scrambler 163.These D/A change-over circuit 164 this vision signal to one of output video output terminals.

Will be from multiplexer 155, offer MPEG 1 demoder 161 by separating the voice data that obtains.The voice data that this MPEG 1 demoder 161 will have been expanded outputs to D/A change-over circuit 165.

D/A change-over circuit 165 will be exported the sound signal of its audio output from the voice data conversion of MPEG 1 demoder 161 by the D/A conversion with formation.

When the mpeg system digital data record that will receive from antenna 166 was to the hard disk of HDD 6, information-recording apparatus at first outputed to multiplexer 169 by STB 167 and digital I/F circuit 168 with numerical data.

Multiplexer 169 is separated into video data and voice data with the numerical data of input.Multiplexer 169 outputting audio datas are to delay circuit 170.

Multiplexer 169 outputs to MPEG 2 demoders 160 through switch 171 and 159 with video data.Simultaneously, gauge tap 171,159 links to each other them respectively with 2 with end points 1.

Then, MPEG 2 demoders 160 expansion compressed video datas and the video data expanded through switch 162,158 outputs are to MPEG 2 scramblers 154.Simultaneously, gauge tap 162,158 links to each other them respectively with 2 with end points 2.

Then, the video data of MPEG 2 scramblers 154 compression inputs.Simultaneously, MPEG 2 scramblers 154 are with the ratio of compression compression GOP and/or the I image of the integral multiple of hard disk logic sector number among the HDD 6.Therefore, enter and have its ratio of compression through MPEG 2 ENC 154 conversions with MPEG 2 video data streams of a predetermined ratio of compression coding by antenna 166.

Voice data by delay circuit 170 time-delays regularly is output to multiplexer 155 a control, and the video data from MPEG 2 scramblers 154 is output to multiplexer 155 simultaneously.

Multiplexer 155 is the Voice ﹠ Video data multiplex of input, thereby produces one with after interface buffer 2, host bus 4 and ATA adapter are recorded in the digital data stream on the hard disk of HDD 6.Therefore use present information-recording apparatus, mpeg data can be recorded on the logic sector as the hard disk of a unit.

If in this information-recording apparatus, be recorded on the hard disk of HDD 6 from the simulating signal of the NTSC system that antenna 150 receives, so at first the simulating signal with the NTSC system outputs to tuner 151.

Tuner 151 detections are from the simulating signal of antenna 150, so that outputting video signal to A/V change-over circuit 152, outputs to voice data A/V change-over circuit 156 simultaneously then.At this moment, A/V change-over circuit 152 will be offered, simultaneously, A/V change-over circuit 156 will be input to from the sound signal of audio input end from the vision signal of its video inputs.

A/V change-over circuit 152 is converted to the video data that outputs to ntsc decoder 153 by the A/D conversion with the vision signal A/D that imports.

Ntsc decoder 153 expansion is from the video data of A/V change-over circuit 152, so that this video data is converted to the baseband signal that outputs to MPEG 2 scramblers 154.Simultaneously, gauge tap 158 makes it to link to each other with end points 1.

Through switch 158 baseband signal is offered MPEG 2 scramblers 154.MPEG 2 scramblers 154 are encoded to mpeg data with a predetermined ratio of compression with the baseband signal of importing, to constitute MPEG 2 system video data.In order to compress GOP and/or I frame data, MPEG 2 scramblers 154 are with the baseband signal coding of the several integral multiples of the logic sector of hard disk among the HDD 6 to this input.MPEG 2 scramblers are exported this video data to multiplexer 155.

The A/V change-over circuit 156 that is provided to the sound signal of self-tuner 151 outputs to sound signal A/D conversion the voice data of MPEG 1 scrambler 157 with formation.

MPEG 1 scrambler 157 will also be incited somebody to action from the audio data coding of A/V change-over circuit 156 according to MPEG 1 system, and coded data outputs to multiplexer 155.

Thereby multiplexer 155 will produce a digital data stream from the video data of MPEG 2 scramblers 154 input with from the voice data of MPEG 1 scrambler 157 inputs is multiplexed.

Multiplexer 155 is recorded in the digital data stream that is produced on the hard disk of HDD 6 through interface buffer 2, host bus 4 and ATA adapter 5.Therefore, in this information-recording apparatus, the digital data stream of mpeg system is unit record by the logic sector number with hard disk.

In this information-recording apparatus,, be the digital data stream that storage among the HDD 6 is read by unit by the data transmission software that starts by RISC CPU 3 with the logic sector of hard disk so if reproduce digital data stream on the hard disk be recorded in HDD 6.Simultaneously RISC CPU 3 can read the digital data stream that is stored among the HDD 6 by for example various variable velocity modes under software control.

Then, in this information-recording apparatus, this numerical data of reading from HDD 6 ATA adapter 5 of flowing through, host bus 4 and interface buffer 2 enter multiplexer 155.Thereby multiplexer 155 separates the digital data stream of input produces video and voice data.

In this information-recording apparatus, if the digital data stream that is recorded on the hard disk will reproduce as numerical data, video data is outputed to multiplexer 169 from multiplexer 155 through switch 171, adjusts voice data by delay circuit 170 simultaneously and makes it time-delay and it is outputed to multiplexer 169.

Thereby multiplexer 169 outputs to digital I/F circuit 168 with multiplexed data with the voice data of video data and input is multiplexed.This voice data and video data are provided to STB 167 and are converted to the voice and video signal by the mpeg decoder among the STB 167, so that its variable speed reproducing, seamless-reproduced or non-linear editing are reproduced under software control by RISC CPU 3.

On the other hand, in information-recording apparatus,, so video data is outputed to MPEG 2 demoders 160 through the end points 1 of switch 159 from multiplexer 155 if the digital data stream that is recorded on the hard disk is used as the simulating signal reproduction.

Thereby MPEG 2 demoders 160 will output to NTSC scrambler 163 with decoded video data through the end points 1 of switch 162 from this video data decoding of multiplexer 155 then.

NTSC scrambler 163 will be the video data of NTSC system from the digital data conversion of MPEG 2 demoders 160 then.NTSC scrambler 163 outputs to D/A change-over circuit 164 with the video data of NTSC system.

Thereby will carrying out D/A conversion then from the video data of NTSC scrambler 163, D/A change-over circuit 164 will output to video output terminals as the translation data of the vision signal of NTSC system.

Multiplexer 155 outputs to voice data MPEG 1 decoder circuit 161 equally.This MPEG 1 demoder 161 will and be exported decoded data to D/A change-over circuit 165 from the decoding of the voice data of multiplexer 155.

D/A change-over circuit 165 will carry out the D/A conversion from the voice data of MPEG 1 demoder 161 and export switched sound signal at audio output.

Therefore, when writing down the numerical data of being compressed by mpeg system, information-recording apparatus is by MPEG2 demoder 160 decoded datas, and MPEG 2 scramblers 154 are with the predetermined ratio of compression coding and the record data of the integral multiple of hard disk logic sector number among the HDD 6.If the NTSC system signal that provides, MPEG 2 scramblers 154 equally can be by scrambler 154 with this digital coding so.So, by using for example data transmission software, thus the access hard disk address information of coming to determine simply hard disk easily, numerical data that can reproducing recorded.Therefore, by this information-recording apparatus, can adopt various playback systems with the reproduction of variable reading speed more conveniently.

In above-mentioned information-recording apparatus, equal the coefficient packed data that the hard disk logic sector is counted integral multiple with one by MPEG 2 scramblers 154.Yet, may use many fixed speeds to realize compression for MPEG 2 scramblers 154.Particularly, if the digital data stream that use is compressed and is recorded on the hard disk is used for editor, standard play (SP) and is used for long-time broadcast (LP), MPEG 2 scramblers 154 can use 8Mbps, 4Mbps and 2Mbps compressibility coefficient so.In order to reproduce the digital data stream that is recorded on the hard disk, can control the data volume that is read out under the control of the data transmission software in RISC CPU 3, so that realize in the same manner as described above reproducing by information-recording apparatus.

The above-mentioned various reproducting methods of reference flow sheet.

For the reproduction of a routine, use operation steps as shown in figure 14.

At first step S511, read the 0th frame of AV digital data stream.In the DV of SD specification system, being recorded in a frame AV digital data stream with 233 sectors is on the sector of unit.Therefore, if the start of record of this AV digital data stream is S frame sector, begin to read zone so from this S district corresponding to 233 sectors of a frame AV digital data stream.

In step S512, read first frame of AV digital data stream.In this step, read the zone of 232 sectors of a frame AV digital data stream that begin corresponding to (S+233) sector from the record terminal point of the 0th frame that follows the AV digital data stream closely.

By same operation steps, read from the DV signal of second frame to the (n-2) frame.Then, handle the step S513 that forwards (n-1) frame to.

At step S513, read (n-1) frame of AV digital data stream.In this step, before processing forwards step S514 to, read the zone of 233 sectors of a frame AV digital data stream that begins corresponding to (S+233* (n-1)) sector from the record terminal point of (n-2) frame of following the AV numerical data closely.

At step S514, read the n frame of AV digital data stream.In this step, read the zone of 233 sectors of a frame AV digital data stream that begins corresponding to (S+233*n) sector from the record terminal point of (n-1) frame of following the AV numerical data closely.Because so just finished reading of AV digital data stream from the 0th frame to the n frame, so stop the operation steps of reproduction of AV digital data stream.

Therefore, 233 sectors of a sector beginning, the current sector of the HDD by reading stop from represent the record data unit continuously and by continuously the data presentation of reading being obtained common representational role at screen.

Secondly, explain the operation steps of jumping.This jump is to finish by an operating process shown in Figure 15.

At first step S615, by a frame of SD specification will with read among the volatile memory STAM as corresponding (S+233) sectors of data of front, the S sector AV digital data stream of DA data origination.Processing procedure forwards step S616 to then.

Before processing procedure forwards step S617 to,, will write again at the mark that step S615 writes the AV digital data stream of SRAM at step S616.

At step S617, will read among the SRAM and it is marked at the AV digital data stream that step S616 writes again and is presented on the screen at step S61 5.Then, processing procedure forwards step S618 to.To explain the mark of the AV digital data stream that writes again subsequently.

At step S618, whether sent generation branch according to Next Command.If (being) sent in next order, stop the running program in this step so so that enter next control.If do not send Next Command (denying), handle resetting into previous step S617.

Therefore, by reading a frame or 233 sectors of data that are positioned at as the front, the current sector of HDD of the point of interruption of record data unit, when pushing skip key, the data storage of reading is obtained skip functionality by the frame data that are stored among the SRAM in SRAM and by showing continuously on screen.

Next, the explanation operation steps of finishing a static operation as shown in figure 16.

At first step S721, will begin to be read into the SRAM from S sector corresponding to 233 sectors of data of a frame of the AV digital data stream of SD specification as DV data starting point.Then, processing procedure proceeds to step S722.

Before processing enters into step S723,, will write again in the sign that step S721 reads in the AV digital data stream of SRAM at step S722.

At step S723, will read in the AV digital data stream that SRAM and its sign write again at step S722 at step S721 and be presented on the screen.Then, processing procedure proceeds to step S724.

At step S724, according to Next Command whether transfer flow has taken place.Just,, stop the operation steps in this step, so that control enters next process if Next Command sends (being).If do not send Next Command (denying), processing procedure resets into back S723.

In this mode, represent 233 sectors that the current sector at abutment, record data unit begins by reading from HDD, and the sector of reading deposited among the SRAM and, realize static function by on screen, showing the frame data that are stored among the SRAM continuously.

Explain the operation steps of putting operation slowly.Suppose that playback speed is lowered to 1/5 of speed.Figure 17 shows and is used for this operation steps of putting operation slowly.

Before processing procedure proceeds to step S832,, will read among the SRAM corresponding to a frame AV digital data stream of SD specification and corresponding to 233 sectors of data of the starting point of DV data at first step S831.

Before processing procedure proceeds to step S833,, be written in the sign that step S831 reads in the AV digital data stream among the SRAM again at step S832.

Before processing enters step S834,, will read in SRAM and its at step S831 and be identified at the data presentation 5 times that step S832 rewrote at step S833.

At step S834, be to enter working direction (+1/5) still to enter reverse direction (1/5) flow path switch according to putting slowly.If put slowly is working direction, and processing procedure enters step S835, otherwise processing procedure enters step S844.

At step S835, will read in SRAM corresponding to 233 a sector datas frame of SD specification and that begin from (S+233) sector of the terminal point sector that follows the 0th frame that belongs to the AV digital data stream closely.Then, processing procedure forwards step S836 to.

Before entering step S837,, be overwritten in the sign that step S835 reads in the AV digital data stream of SRAM at step S836.At step S837, will read in SRAM and its at step S835 and be identified at the data that step S836 is rewritten and on screen, show 5 times.

Before step enters S838, carry out continuously in an identical manner from the operation steps of the 2nd frame to the (n-2) frame.

At step S838, will read in SRAM corresponding to a frame of SD specification and 233 sector datas that begin from (S+233* (n-1)) sector of the terminal point sector that follows the AV digital data stream that belongs to (n-2) step closely.Then, processing procedure forwards step S839 to.

Before processing procedure enters step S840,, be overwritten in the sign that step S838 reads in the AV digital data stream of SRAM at step S839.

Before processing enters step S841,, will read in SRAM and its at step S838 and be identified on the data screen that step S839 was rewritten and show 5 times at step S840.

At step S841, will read in SRAM corresponding to a frame of SD specification and 233 sector datas that begin from (S+233*n) sector of the terminal point sector that follows the AV digital data stream that belongs to (n-1) step closely.Then, processing procedure enters step S842.

Before processing enters step S843,, be overwritten in the sign that step S841 reads in the AV digital data stream of SRAM at step S842.

At step S843, will read in SRAM and its at step S840 and be identified at these data that step S842 was rewritten and on screen, show 5 times.Because the demonstration to the AV digital data stream of n frame has finished now, so the terminating operation step.

At step S844, will be corresponding to a frame of SD specification and from reading in SRAM to 233 sector datas of the 0th frame of AV digital data stream as (S-233) sector of the initial sector of former frame.Then, processing procedure forwards step S845 to.

Before processing procedure forwards step S846 to,, will write the sign rewriting of the AV digital data stream of SRAM at step S844 at step S845.At step S846, will be read into SRAM and its at step S844 and be identified at these data that step S845 has been rewritten and on screen, show 5 times.

In an identical manner, processing procedure enter be used to handle the step S847 of (n-1) frame before, finish from the operation steps of second frame to the (n-2) frame.

At step S847, corresponding to the AV digital data stream of 233 sectors of a frame of SD specification from being read into SRAM as (S-233 * (n-1)) sector prior to the beginning sector of the frame of (n-2) frame of AV digital data stream.Then, processing enters step S848.

Before processing procedure enters step S849,, be overwritten in the sign that step S847 reads in the AV digital data stream of SRAM at step S848.

Before processing procedure enters step S850,, will be read into SRAM and its at step S847 and be identified at these data that step S848 has been rewritten and on screen, show 5 times at step S849.

At step S850, corresponding to the AV digital data stream of 233 sectors of a frame of SD specification from being read into SRAM as (S-233 * n) sector at the initial sector of a frame of (n-1) frame front of AV digital data stream.Then, processing enters step S851.

Before processing enters step S852,, be overwritten in the sign that step S850 reads in the AV digital data stream of SRAM at step S851.

At step S852, will read in SRAM and its at step S850 and be identified at these data that step S851 has been rewritten and on screen, show 5 times.Owing to be accomplished to the demonstration of the AV digital data stream of n frame, stop this operation steps.

By this way, slow playing function is read 233 sectors that begin from the current sector of frame abortion, and the sector of reading is deposited among the SRAM, is stored in the sign of data among the SRAM so that rewrite, thereby these frame data are shown on screen 5 times.Realize the speed of putting slowly by selected arbitrary number of times that on screen, shows.

Next, the step of interpret prompts checked operation.Realize this prompting checked operation by operation steps shown in Figure 180.

In this prompting checked operation step, be similar to and put operation slowly, carry out sequence of operations, that is, read the AV digital data stream, the AV digital data stream that the AV digital data stream is read in SRAM and will read in SRAM is presented on the screen.For simplicity, represent these operations with an independent block diagram.

At first step S961, the AV digital data stream of a frame SD specification begins to be read into SRAM from the S sector as the starting point of AV digital data stream and the AV digital data stream that will be read into the SRAM is presented on the screen.Then, processing enters step S962.

At step S962, be prompting or check flow process branch according to operation.In the previous case (being), handle and forward step S963 to, and, handle forwarding step S966 to latter event (denying).

At step S963, carry out the demonstration of first frame, here,, and the AV digital data stream that is read in is presented on the screen from 233 sectors that begin to read the AV digital data stream corresponding to (S+233 * 6) sector at a frame of the 0th frame front 6 frames.

In an identical manner, before processing enters step S964, show the 2nd frame to the (n-2) frame continuously.

At step S964, carry out the demonstration of (n-1) frame, here, from 233 sectors that begin to read the AV digital data stream corresponding to (S+233 * (the n-1)) sector at a frame of (n-2) frame front 6 frames, and the AV digital data stream that will so read before processing enters step S965 is presented on the screen.

At step S965, carry out the demonstration of n frame.Here, from (S+233*n*6) corresponding to a frame of (n-1) frame front 6 frames) begin to read 233 sectors of the AV digital data stream of 233 sectors, and the AV digital data stream that will so read is presented on the screen.

When the image demonstration up to the n frame has finished, the terminating operation process.

At step S966, carry out the demonstration of first frame.Here, begin to read the AV digital data stream of 233 sectors from (S-233*n*6) sector, and the AV digital data stream that will so read is presented on the screen corresponding to a frame of the 0th frame front 6 frames.

In an identical manner, before processing enters step S967, show that continuously the 2nd frame is to (n-2) frame.

At step S967, carry out the demonstration of (n-1) frame.Here, begin to read the AV digital data stream of 233 sectors, and the AV numerical data that will therefore read is presented on the screen before processing enters S968 from (S-233 * (n-1) * 6) sector corresponding to a frame of (n-2) frame front 6 frames.

At step S968, carry out the demonstration of n frame.Here begin to read the AV digital data stream of 233 sectors from (S-233 * n*6) sector, and the AV digital data stream that will therefore read is presented on the screen corresponding to a frame of (n-1) frame front 6 frames.

When being shown to the n frame, the terminating operation process.Particularly, prompting/audit function is jumped corresponding to the number of sectors of 6 times of 233 sectors that begin from any sector of representing frame interruption, thereby the AV digital data stream of reading is presented on the screen.This prompting/inspection playback speed is to realize by the arbitrary integer of adjusting the sector of being jumped.

In above-mentioned explanation, shown SD specification as the DV system specialization.Be noted that the AV digital data stream of high speed SD specification and the AV digital data stream of HD specification can handle by read/write cell being become 117 and 466 respectively.

Carry out search slowly and search fast in the same manner.Slow function of search is read from 233 sectors representing that current sector that a frame interrupts begins and with the sector of reading and is deposited in the SRAM.Then, search for the frame data that will be stored among the SRAM slowly and on screen, show arbitrary number of times, so that on screen, show this data arbitrary number of times continuously frame by frame.Control flow by the commander that links to each other with RS-233C changes the value that repeats to be presented at the arbitrary number of times on the screen continuously, thereby can change playback speed continuously.

Fast function of search jump equal 233 sectors beginning from arbitrary sector of interrupting corresponding to a frame an arbitrary integer doubly sector number and read frame data so as with this data presentation on screen.Control flow by the instruction device that links to each other with RS-232C changes the quantity of institute jump sector continuously, thereby changes playback speed serially.

Explain now that the pattern that is used to control above-mentioned functions is provided with the control flow of commander 8.This pattern is provided with commander 8 and links to each other with RISC CPU board 20 and make it to be adapted to by RS-232C and controlled by control strip (controlbar), but so that can be on its control flow the continuous variation in the control speed playback speed delicately.

This control flow is by some buttons and line up a vertical elongated window that is roughly the rectangle window, as shown in figure 19.In other words, look to bottom from the top of Figure 19, be arranged with a row " playback (PlayBack) " 71, one row " stepping (Step) " 72, " putting (Slow) slowly " 73 and " record (Rec) " 74, one row " quick search (Fast Search) " 78, one row " quick access (Fast Access) " 75 and one row " editor's detection (Edit Test) " 76 and " artificial window (Emulation Window) " 77.

" playback " 71 has such as " ← ", " playing (Play) ", " → ", " previous (Pre) ", " top (Top) ", " stopping (Stop) " or " next (Next) " button can select various playing functions.Determine screen simulated light target position and click the mouse and to select these buttons by the mouse on button.

" stepping " 72 has an individual left-hand button "＜" and a dextrad button "〉" stepping that can fall back respectively and advance selects.

" putting " 73 slowly has button " 1/5 ", " 1/5 " and " 1/10 " and can realize that 1/5 " slowly " of reverse direction select and in 1/5 and 1/10 selection slowly of working direction.The selection of " record " 74 can realize determining the record of item.

This row " search fast " 78 has a controller that is used to move in the horizontal direction the velocity correlation button.By moving the button of this and definite velocity correlation, can from-50 to 50 change playback speed continuously, that is, and at the playback speed of reverse direction from the playback speed of 50 gulp to 50 gulp of working direction.

This row " quick access " 75 be useful on the so-called trigger button " Go to " of on/off switch and " Preview Scan ", one can roll and select such as the window of " AAA ", " BBB ", " Camera " or " CCC " content and be used to carry out the function of selecting at content by trigger button.

This row " editor detects " 76 has a button that detects editting function and the window that this row " artificial window " 77 has the actual content that is used to show an instruction delivering to RISC CPU.

Although make as above explanation, notice that the present invention can be applied to high compression DS and HD specification simply with reference to the SD specification of DV system.

Here explain the data structure of SD specification for the reference reason.As shown in figure 20, the data volume corresponding to a frame data stream of SD specification is 119200 bytes.Every frame by from the 0th to the 9th track totally 10 tracks form, each track is 11920 bytes.Each track is made up of data " title ", " subcode ", " VAUX " and " audio frequency/image ".

Forward the mark of above-mentioned data structure to, " speed " of data structure that stops the AAUX to comprise in ON/OFF control mark and 10 tracks that constitute a frame data stream of mute function of voice output is relevant.If this " speed " has a normal value " 0100000 ", export voice so, otherwise, if not so, the mute state that stops voice output being set.If this transcriber is in a kind of state rather than common playback mode, so this mute state is general.

Be used for static and frame on the scene static between " FF " of data structure of the VAUX that provided of mark and each track of switching controls relevant with " FC ".Here, " FF " and " FC " represents frame, field flag and first and second mark respectively.

If " FF " is 1, output constitutes 2 fields of a frame, otherwise, if it is 0, one of 2 fields of so continuous 2 output.If " FF " is 1 or 0, export first " FS " or second continuously.

If broadcast state is a static broadcast, wherein static to be switched to wherein so-called of one of first and second outputs static for the so-called frame exported continuously of first and second of a frame quilts.Even be displayed on the screen such as occurring in the discontinuous motion that produces when golf club is swung, so also can prevent the unintelligible of image.

On the other hand, by determining a sector, can realize utilizing the seamless repeat function of the zero access characteristic of HDD at an easy rate corresponding to the AV data of desired repetition.

Do above-mentioned explanation although be on the basis of the variable speed reproducing by realizing having better maintainability with the speed recoding/reproduction DV signal of the integral multiple that equals sector number on the hard disk, can be by the fixing data bulk of GOP and frame data of mpeg signal, and the data volume of fixing by making is suitable for the integral multiple of sector number, realizes having the identical variable speed reproducing of better maintainability in MPEG.

Claims (23)

1. information-recording apparatus comprises:

Input media is used to import and has the data that its regular length equals a frame length integral multiple;

Control device is used for giving the predetermined number of consecutive sector with the data allocations of input; With

Pen recorder is used for the data of described regular length are recorded in the predetermined number of consecutive sector.

2. information-recording apparatus according to claim 1, wherein:

Described data comprise view data and/or voice data at least.

3. information-recording apparatus according to claim 2, wherein:

Described view data is the data that are designated as accurate basic coding with DV.

4. information-recording apparatus according to claim 2, wherein:

Described view data is to be the data of standard code with MPEG.

5. information-recording apparatus according to claim 1 further comprises:

Switching device shifter is used for according to switching the sector number that is distributed by the data pattern of described input media input.

6. information-recording apparatus according to claim 4, wherein:

Described input media input has the data based on the regular length of GOP.

7. information recording method comprises:

Import the data that its regular length equals the integral multiple of a frame length;

To import data allocations and give the predetermined number of consecutive sector; With

Described fixed-length data is recorded on the predetermined number of consecutive sector.

8. according to the information recording method of claim 7, wherein:

Described data comprise view data and/or voice data at least.

9. information recording method according to Claim 8, wherein:

Described view data is to be the data of basic coding with the DV standard.

10. information recording method according to Claim 8, wherein:

Described view data is to be the data of basic coding with the mpeg standard.

11. the information recording method according to claim 7 further comprises:

According to switching the sector number that is distributed by the data pattern of described input media input.

12. according to the information recording method of claim 10, wherein:

It is the data of basic fixed length that described input media has with GOP.

13. an information reproduction device comprises:

Transcriber is used to reproduce write down on it by being assigned with the predetermined quantity contiguous sector and makes it have the recording medium of the data of the regular length that equals a frame length integral multiple.

14. information reproduction device according to claim 13 further comprises:

Static/step device, be used to read frame data, and the frame data that will so read are stored in the impact damper, and show these frame data that are stored in this impact damper since the regular length of first sector.

15. information reproduction device according to claim 13 further comprises:

The variable speed reproducing device, be used to read frame data since the regular length of first sector, and the frame data that will so read deposit a frame buffer in, and in order to change reproduction speed and to repeat to show these frame data that are stored in this impact damper by reproducing.

16. information reproduction device according to claim 13 further comprises:

Prompting/the testing fixture of variable velocity be used for reading the integer frame of many times of described fixed-length datas since single/a plurality of sectors of first sector by jumping, and the sector that is used for so reading is presented at screen.

17. information reproduction device according to claim 13 further comprises:

Slow searcher is used for reading since first sector frame of described fixed-length data, deposits frame data of so reading in an impact damper, and continuously changes and be stored in the number of times that these frame data in this impact damper repeat to show.

18. information reproduction device according to claim 13 further comprises:

Searcher is used for when reading the integer frame of many times of described fixed-length datas by the single/a plurality of sectors of jumping since first sector fast, changes the sector number that was jumped continuously, so that the sector that will so read is presented on the screen.

19. information reproduction device according to claim 15, wherein, the transcriber of described variable velocity is useful on by being positioned at first setting device that control strip on the display screen is provided with variable reproduction speed.

20. information reproduction device according to claim 15, wherein, described variable-ratio prompting/testing fixture comprises second setting device that is used for being provided with by the control strip on the display screen prompting/inspection speed.

21. information reproduction device according to claim 13 further comprises:

Be used to stop voice output mute function the ON/OFF control mark and be used for static and frame on the scene static between another mark of switching of control.

22. an information regeneration method comprises:

Reproducing to have write down on it by being assigned with the predetermined quantity contiguous sector makes it have the recording medium of the fixed-length data that equals a frame length integral multiple; With

Sequentially export the data of described reproduction.

23. a recording medium has the data that regular length equals a frame length integral multiple on it, by giving the predetermined quantity contiguous sector with this data allocations and it being recorded on this recording medium.

Images