CN1220927C - Apparatus for dynamically regulating computer system power consumption - Google Patents
Apparatus for dynamically regulating computer system power consumption Download PDFInfo
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- CN1220927C CN1220927C CN 02143996 CN02143996A CN1220927C CN 1220927 C CN1220927 C CN 1220927C CN 02143996 CN02143996 CN 02143996 CN 02143996 A CN02143996 A CN 02143996A CN 1220927 C CN1220927 C CN 1220927C
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Abstract
The present invention relates to an apparatus for dynamically regulating the consumed power of a central processing unit, which comprises a current detector, a comparator, a hardware frame and a software frame, wherein the current detector detects the current of a current-limiting resistor and sends out a detection signal; the comparator receives the detection signal and compares the detection signal with a first preset value, a warning signal is sent out if the detection signal is larger than the first preset value, or else any signal is not sent out; the hardware frame is triggered by a warning signal to send a frequency reducing command with a particular frequency to the central processing unit; the software frame is triggered by the warning signal, the inner set value of the software frame is firstly overwriten, the frequency is reduced by sending the frequency reducing command to the central processing unit according to the inner set value which is firstly overwritten, and simultaneously the software frame continually monitores the signal of a detection result, and compares the signal with a second preset value. If the signal of the detection result is smaller than the second preset value, the inner set value of the software frame is secondly overwritten, and the frequency reducing command of the central processing unit is relieved according to the inner set value which is secondly overwritten.
Description
(1) technical field
The invention relates to a kind of device of adjusting the computer system power consumption, particularly relevant for a kind of power consumption device that can dynamically adjust computer system.
(2) background technology
Surging along with environmental consciousness, the computer industry also blows afloat a burst of trend of environmental protection, and the computer of some compliance with environmental protection requirements is kept up a steady flow of such as green computer, and in many environmental protection standards, and important criterion is promptly in the quality of computer electricity-saving function.
Notebook computer is the invention of most convenient in modern age, has the advantage of conventional desktop computer, for example powerful arithmetic capability and extendible ability, and have the advantage that conventional desktop lacks, for example volume is little, and is easy to carry.But notebook computer is a fatal shortcoming under cover, the power that continues of its use just.At ordinary times, because electricity consumption is convenient, so notebook computer can use civil power to serve as power supply, and to battery charge.But work as the people under the situation that outdoor no civil power can connect, the running of notebook computer promptly needs full battery on one's own account, yet the battery ability is strong again, and electric power also has one day that uses up.Therefore, if number increases when wanting to make notebook computer to use, outer two kinds of methods, the one, increase the electric power of battery, but the method often is accompanied by huge volume and weight, this is not to be kind of a good scheme; Another kind is the power consumption that reduces central processing unit in the notebook computer, and identical electric power is survived the long time.
General normal making is used for controlling the central processing unit electricity saving method and has following several, a kind of is to be notebook computer with speed change (SpeedStep) technology that central processing unit developed out by Intel (Intel) company, its basic skills is to allow central processing unit when being used as power supply with electric main and use battery to be used as power supply, allows the clock pulse difference of central processing unit.Another kind is at the inner speed-regulating function (throttlingfunction) of carrying out of central processing unit, that is in a work period width, the operating system of computer can produce an operations policies, can't allow central processing unit continue running in the whole work period width, this speed-regulating function mechanism can allow central processing unit only carry out certain number percent in a work period width, if that is central processing unit is when continuing with working at high speed, system temperature will continue to raise, this moment, operating system can make central processing unit slow down automatically, to reduce central processor temperature.Wherein above-mentionedly do not support desk-top central processing unit by speed change (SpeedStep) technology that Intel company developed, and another kind of speed-regulating function (throttling function) can be supported desk-top and the notebook central processing unit simultaneously, but this kind method mainly is to use the generation at the control heat, just can move in the time of need being higher than certain temperature, can't cooperate for the dynamic performance requirements of system.
Today, using desk-top central processing unit on notebook computer is to force down cost, improves the effective method of computer performance, but the high heat of desk-top central processing unit, high consumption rate but is the bottleneck that need overcome.Though by Intel (Intel) speed change that company developed out (SpeedStep) technology, can be by operating system (operatingsystem, OS) to the control of system, change the running speed of central processing unit rapidly, reduce the consumption of power supply, but the desk-top central processing unit that Intel company developed is not supported this speed change (SpeedStep) technology, if in notebook computer, use the words of desk-top central processing unit rashly, tend to cause high power consumption, unrealistic on the contrary.Therefore a kind of monitor current at any time if can develop, send warning signal in good time, to produce the frequency that signal to reduce the speed and central processing unit reduce central processing unit, so can not only in notebook computer, use desk-top central processing unit, to reduce the cost of notebook computer, also can reduce simultaneously the power consumption of desktop computer, reach the purpose of real green computer.
(3) summary of the invention
In computer system, central processing unit is a critical elements and suitable consumed power, and the influence of this element power notebook computer that consumption brings is more obvious, it not only can consume the electric power of notebook computer in a large number, and the power that is consumed is changed into heat come out, make own and ambient temperature increases, make system become the state of rather unstable, more thereby cause the situation of system mistake.In order successfully to get rid of this heat, we must install large-scale heat radiator and large-scale fan additional, so that hot gas can be got rid of smoothly, reduce the harmful effect of hot gas to system, and heavy parts are obviously too luxurious in mini notebook-computer system of simplifying.
Though traditional power conservation techniques, as Intel (Intel) speed change that company developed out (SpeedStep) technology, though can be by operating system (operating system, OS) to the control of system, change the running speed of central processing unit rapidly, reduce the consumption of power supply, but the desk-top central processing unit that Intel company developed is not supported this speed change (SpeedStep) technology.And on the other hand, traditional speed-regulating function (throttling function) mainly is at the central processing unit working at high speed, under the situation that temperature is too high in the system, operating system will make central processing unit slow down automatically, to reduce central processor temperature, that is to say that the fundamental purpose of this function is the generation that is to control heat, but not dynamic fit system effectiveness demand adjusts.Therefore the present invention proposes a kind of dynamic adjusting gear at above-mentioned shortcoming, utilization is to the dynamic monitoring of electric current, can send warning signal immediately, the notice central processing unit carries out inner frequency reducing, suppresses the load of central processing unit, and is excessive to solve electric current, the shortcoming that power consumption increases, also can solve simultaneously when central processing unit when load is excessive, can't provide system required electric current, cause system to work as the generation of machine or outage phenomenon.
Fundamental purpose of the present invention promptly provides a device that can dynamically change the dynamic adjustment central processing unit consumed power of central processing unit frequency, in order to working condition according to central processing unit, dynamically change the central processing unit internal frequency, avoid the excessive generation that causes system to work as machine or outage phenomenon of load.
Another object of the present invention provide a kind of can be according to the size of immediately monitoring electric current, dynamically change the device of the dynamic adjustment central processing unit consumed power of central processing unit frequency of operation, avoid because of electric current excessive, cause the rapid rising of central processor temperature, and have the situation of job insecurity to produce.
Another purpose of the present invention provides a kind of method of dynamic adjustment central processing unit consumed power of dynamic change central processing unit frequency of operation; the method can not only be taken into account the task performance of central processing unit, and can protect central processing unit not make the rapid rising of internal temperature because of electric current is excessive.
According to above-mentioned purpose, the device of dynamic adjustment central processing unit consumed power of the present invention comprises a current sensing means, a comparer, an embedded controller, a D flip-flop and frequency generator at least.
Wherein current sensing means detects the size of current of the current-limiting resistance of flowing through and sends a detection signal, judge via comparer whether this detection signal size can be greater than a particular value, and the big I of this particular value is by the ultimate load of user according to computer system central processing unit desire load, that is set by acceptable power consumption; If this detection signal greater than this particular value size, then can send warning signal, to trigger frequency generator and D flip-flop, after frequency generator was triggered ,-STPCLK# signal can be sent to central processing unit to carry out the frequency reducing of central processing unit; And on the other hand, after D flip-flop is triggered, one latch-up signal can be sent to the embedding controller, allow the embedding controller change its inner system manipulation and interrupt the setting of (SMI) value, send smi signal simultaneously, after basic output/input system receives this smi signal, can notify south bridge, to send STPCLK# signal and central processing unit, the frequency reducing of control central processing unit.
And on the other hand, the detection signal that current detector is sent also can transmit and embed controller, this embeds controller can monitor this detection signal, and whether the size of judging this detection signal can be less than a particular value, that is judge whether the electric current that this moment, total system circulated is still excessive, if not excessive embedding controller can be sent reset signal and D flip-flop with this D flip-flop of resetting, allow it no longer send latch-up signal, changing its inner SMI value simultaneously sets, monitor the change of this smi signal when basic output/input system after, can not send STPCLK# signal and central processing unit again by the notice south bridge, this moment, central processing unit promptly can be adjusted the lifting situation of internal frequency automatically according to practical work amount situation.
(4) description of drawings
Be clearer understanding purpose of the present invention, characteristics and advantage, below in conjunction with accompanying drawing to of the present invention preferable
Embodiment is elaborated.
Fig. 1 is the skeleton diagram of dynamic adjustment power consumption device of the present invention;
Fig. 2 is for being the detailed block diagram of dynamic adjustment power consumption device of the present invention;
Figure 3 shows that the waveform comparison diagram of each point;
Figure 4 shows that the present invention dynamically transfers central processing unit down conversion process process flow diagram; And
Figure 5 shows that the present invention dynamically adjusts the processing flow chart that central processing unit is not subjected to the STPCLK# signal controlling.
(5) embodiment
Under the situation that does not limit spirit of the present invention and range of application, below promptly introduce enforcement of the present invention with an embodiment; Person skilled in the art person is after understanding spirit of the present invention, when using dynamic adjusting gear of the present invention in various computer system, by circuit design of the present invention, the shortcoming that the operation rate of central processing unit traditionally can be caused power consumption increase in default of dynamic adjusting gear corrects, and also can solve simultaneously when central processing unit can't provide the required electric current of system and cause system in case of system halt or the generation problem of outage phenomenon when load is excessive.Below introduce the power consumption that the present invention is applied to notebook computer with an embodiment and dynamically adjust, but application of the present invention is when the preferred embodiment that be not limited only to the following stated.
Generally speaking, the power consumption of computer cpu can reduce by dynamically changing the operating rate of central processing unit, that is, allow the central processing unit operation rate dynamically change according to the charge capacity of itself.This tactful fundamental purpose is that the mode that allows central processing unit utilize the present invention dynamically to adjust when charge capacity is excessive allows its instant reduction of speed, takes place with the situation of avoiding system in case of system halt.In other words, dynamic debugging system of the present invention can be adjusted the speed of central processing unit at any time according to the loading condition of central processing unit, and moment is suppressed the charge capacity of central processing unit, solves the excessive problem of electric current.Therefore the present invention utilizes to allow the operating rate of central processing unit along with loading condition dynamically changes, and reduces the power consumption of central processing unit, avoids the central processing unit load excessive simultaneously, causes system in case of system halt or outage situation to take place.
With reference to figure 1, skeleton diagram for dynamic adjustment power consumption device 100 of the present invention, it is electric current 134 sizes that flow through resistance 104 in order to detection for a current detector 102, and amplifying back output one signal to a comparer 106 through current detector thus 102, the electric current 134 of the current-limiting resistance 104 of wherein flowing through is to be supplied to the system load use by a rectifier 108 outputs after by this current-limiting resistance 104.
Still see also Fig. 1, after receiving the signal of being exported by current detector 102 when comparer 106, this signal and a predefined fixed signal (not shown) can be compared, wherein fixed signal can be by the ultimate load of user according to computer system central processing unit desire load, that is acceptable power consumption set, and its setting means can be carried out the fixed point design of power consumption by conventional art in one of comparer two input ends.When the signal of being exported when current detector 102 surpasses this fixed signal, promptly represent the charge capacity of central processing unit to exceed the charge capacity that desire is loaded, the electric current 134 that is supplied to computer system is excessive, and can export a caution signal and trigger a D flip-flop 110 and a frequency generator 112 simultaneously this moment.Otherwise the signal of being exported when current detector 100 is during not as good as this fixed signal, and the charge capacity of promptly representing central processing unit is in accessible scope, that is it is not excessive to be supplied to the electric current 134 of computer system, and this moment, comparer 106 can't be exported caution signal.With most preferred embodiment of the present invention, the size of current of this computer system central processing unit desire load is to be set in 4.7 amperes, that is acceptable power consumption is to be set in 90 watts (W), the size that detects electric current 134 when current detector 100 surpasses 4.7 ampere-hours, comparer 106 can send a warning message, otherwise then can not export any caution signal.
Still please continue to consult Fig. 1, after comparer 106 sends warning signal, can trigger a D flip-flop 110 and a frequency generator 112 simultaneously.After frequency generator 112 is triggered, can be according to the frequency setting of this frequency generator 112, with this frequency of setting output STPCLK# signal, wherein this STPCLK# signal is to be used for declaring that the inside clock pulse of central processing unit 120 temporarily stops, also being about to clock pulse speed reduces, simultaneously and reduce the voltage of central processing unit, so can reduce the power consumption of central processing unit 120, and reach the function that load descends immediately.And on the other hand, the caution signal that comparer 106 is sent also can trigger D flip-flop 110, embed controller 116 to send latch-up signal 114 to, interrupt (SMI) (System Management Interrupt) signal to send a system manipulation, change the SMI initial set value that embeds in the controller 116 simultaneously, wherein this smi signal is in order to there to be an interrupt event to take place in the announcement system, as basic input/output system (Basic Input/Output System, BIOS) 118 detect embed in the controller 116 the SMI initial set value change after, can there be an interrupt event to take place by notice south bridge 122, south bridge 122 also can be sent a STPCLK# signal and give central processing unit 120 at this moment, when central processing unit 120 is received this STPCLK# signal, its inner clock pulse frequency can descend, reduce the consumption of power, wherein basic input/output system 118 can set for according to need the clock pulse frequency that reduced for originally 50%, 60% or 87.5%.It should be noted that, the STPCLK# signal of being sent by frequency generator 112, the STPCLK# signal of being sent with south bridge 122 can be sent to one with (AND) logic gate 124, in other words, the reduction of speed control of central processing unit 120, controlled by the STPCLK# signal that south bridge 118 is sent, the STPCLK# signal of being sent by frequency generator 112 is controlled exactly.
After central processing unit 120 inner clock pulse frequencies descend, its execution speed can reduce, therefore, working as central processing unit 120 consumed powers this moment can descend, that is the electric current 134 of the current-limiting resistance 104 of flowing through can reduce, work as comparer 106 this moment and receive the signal of being exported by current detector 102, and this signal and a predefined fixed signal compared, according to most preferred embodiment of the present invention, that is the electric current 134 of the current-limiting resistance 104 of ought flowing through is less than 4.7 amperes, comparer 106 can't be exported caution signal and trigger frequency generator 112 at this moment, and in other words, this moment, frequency generator 112 can't send STPCLK# signal and central processing unit.But then, though comparer 106 also can not exported warning and trigger D flip-flop 110, but because the latch-up signal 114 that D flip-flop 110 is exported is still being controlled embedding controller 116, therefore it still carries out reduction of speed by south bridge control central processing unit 120, allows the flow through electric current 134 of current-limiting resistance 104 continue to remain in below 4.7 amperes.
And on the other hand, current detector 102 is except meeting continues to send current detection signal and comparer 106, embed controller 116 and also can continue to monitor detection signal, according to preferred embodiment design of the present invention, when going out overall power consumption, the signal reaction that detects has been lower than 75 watt-hours, promptly represent the pending work of total system this moment not have much to do, embed controller 116 and can send a reset signal (Clear) 126 replacement D flip-flops 110, D flip-flop 110 is promptly no longer sent latch-up signal and is embedded controller 116, embed controller 116 and can heavily fill out its inner SMI setting value this moment, inform that interrupt event no longer exists, as basic input/output system 118 (Basic Input/Output System, BIOS) detect the SMI setting values that embed in the controller 116 and change after, can disappear by notice south bridge 122 interrupt events, south bridge 122 is no longer sent the STPCLK# signal and is given central processing unit 120 at this moment, this moment central processing unit can be according to the state of the pending work of system inner clock pulse frequency voluntarily the adjustment period, until excessive because of central processing unit 120 operating loads, the electric current 134 that causes the current-limiting resistance 104 of flowing through just can start dynamic adjustment power consumption device of the present invention this moment once more again greater than 4.7 amperes.
The present invention can use hardware structure and software architecture to send the inside clock pulse frequency of STPCLK# signal controlling central processing unit 120 simultaneously, and the present invention utilizes the mode of the dual framework control of this kind to have following advantage at least.Wherein in the hardware structure aspect, after receiving the warning message of being sent by comparer 106 when frequency generator 112 1, can send the STPCLK# signal immediately and reduce central processing unit 120 inner clock pulse frequencies, after in case central processing unit 120 inner clock pulse frequencies descend, the electric current 134 that can reflect the current-limiting resistance 104 of flowing through descends, frequency generator 112 is promptly no longer sent the STPCLK# signal and is given central processing unit 120 at this moment, this moment is when still having a large amount of work to wait to carry out as if central processing unit, the electric current of current-limiting resistance 104 of flowing through can rise again rapidly, can allow comparer 106 send the STPCLK# signal once more gives central processing unit 120 inner clock pulse frequency is turned down, the mode that so repeats to allow central processing unit 120 inner clock pulse frequencies adjust, can cause the total system instability, that is, if only control the frequency reducing of the clock pulse frequency of central processing unit by hardware structure, repeating the result switched in short time, is the unsettled origin cause of formation of system on the contrary.
Yet the present invention is outside hardware structure, utilize software architecture to control the frequency reducing of the clock pulse frequency of central processing unit 120 separately, that is, by current detector 102 exported signal except meeting is sent to comparer 1 06, also can deliver to D flip-flop 110 in addition, the latch-up signal that utilizes D flip-flop 110 to be sent will embed controller 116 and keep central processing unit 120 is controlled under a certain clock pulse frequency, whether reflected and be lower than a predefined power consumption value and also continue current detection signal that monitoring sent by current detector 104 on the other hand, if in case be lower than default power consumption value, promptly represent the pending work of total system this moment not have much to do, therefore embedding controller 116 can send reset signal 126 replacement D flip-flops 110, allows it no longer send latch-up signal.This moment central processing unit can be according to the state of the pending work of system inner clock pulse frequency voluntarily the adjustment period, until excessive because of central processing unit 120 operating loads, the electric current 134 that causes the current-limiting resistance 104 of flowing through is again greater than 4.7 amperes, just can start dynamic adjustment power consumption device of the present invention this moment once more, immediately central processing unit 120 inner clock pulse frequencies are downgraded by hardware structure part of the present invention, then partly continue central processing unit 120 inner clock pulse frequencies are remained under the frequency by software architecture.In other words, this device hardware structure is asynchronous generation with the STPCLK# signal that software architecture is partly produced partly, when the electric current of the current-limiting resistance of flowing through exceeds setting value, just having begun is that the STPCLK# signal that immediately partly produced by hardware structure is controlled central processing unit 120 and carried out frequency reducing, then transfers to STPCLK# signal that software architecture partly produced again and continues and control central processing unit 120.
See also the detailed block diagram of Fig. 2 for dynamic adjustment power consumption device 100 of the present invention, the electric current of rectifier 108 output wherein, with the electric current behind the current-limiting resistance R1 that flows through, two-end-point RS+ and RS-by current detector 102 received respectively, it is in order to the detection current-limiting resistance R1 size of current of flowing through, by detecting the size of current difference that two ends received, export a voltage detection signal through the output of current detector 102 (OUT) end points thus, embed controller 116 and comparer 106 respectively, wherein this current detector 102 can be selected the logical circuit of the model MAX4173F that MAXIM company produced for use.Electric current by current-limiting resistance is to be supplied to system load to use.
Wherein after second end points 2 of comparer 106 is received the voltage detection signal of being exported by current detector 102, this signal and-predefined fixed signal can be compared, wherein fixed signal is first end points, 1 input by comparer 106, and the big I of this fixed signal is by the ultimate load of user according to computer system central processing unit desire load, according to being added on the voltage swing of resistance R 3 outward with R4, the size of adjusting resistance R 3 and R4 obtains certain point voltage, with regard to most preferred embodiment of the present invention, be that resistance R 3 and the size of R4 are set for, can reflect consumed power in first end points, 1 input of comparer 106 and be 90 watts situation.The voltage detection signal exported of current detector 102 also can be sent to and embed controller 116 on the other hand, in the course of work of central processing unit 120, embeds the voltage detection signal that controller 116 monitoring is always received.
Consult the waveform comparison diagram that Figure 3 shows that each point, still please walk abreast simultaneously and consult Fig. 2, suppose that the voltage detection signal that current detector 102 is exported is the string ripple signal 300 shown in the figure, wherein because the different loading condition of central processing unit, can show different size of current in the current-limiting resistance place, so the voltage detection signal that current detector 102 is exported has the situation that just rises and falls.Comparer 106 can compare this signal and a fixed signal 301, when string ripple signal 300 during greater than fixed signal 301, can be in the output terminals A place of comparer 106 output higher order signal, otherwise, if string ripple signal 300 is during less than fixed signal 301, can export the low order signal in the output terminals A place of comparer 106, and form square-wave waveform 302 as Fig. 3.When the square-wave waveform 302 that is positioned at the A place during in the high-order state, can be with 201 conductings of BJT transistor, the external voltage source 203 of transistor this moment is understood via BJT transistor 201 ground connection, cause the voltage at B point place to descend, otherwise when the square-wave waveform 302 that is positioned at the A place during in the low order state, BJT transistor 201 is to be in closed condition, this moment, BJT transistor 201 external voltage sources 203 can draw high the voltage of B, therefore, form square-wave signal 304 as shown in Figure 3, it should be noted that A, the square-wave signal that B is 2 is to be anti-phase situation each other.
Wherein the B square-wave signal of ordering can be sent to an OR logic gate 205, in or (OR) logic gate 205 places formed as shown in Figure 3 waveform 305 with sending the waveform adder of tool characteristic frequency by frequency generator, according to preferred embodiment of the present invention, the characteristic frequency of this frequency generator is to select 4K hertz (Herze) for use, promptly can send STPCLK# signal and central processing unit 120 to reduce inner clock pulse frequency according to this characteristic frequency this moment, reaches the function of instant reduction load.
And on the other hand, after square-wave signal 302 that A is ordered is sent to D flip-flop 110 via transistor 204, signal 3021 parts of square-wave signal 302 can be sent to the CLK end points of D flip-flop 110 to trigger D flip-flop 110, and send a latch-up signal 114 and embed controller 116 in the Q of D flip-flop 110 end points, the higher order signal meeting turn-on transistor 302 that while Q end points is sent, the current potential of CLK end points of leaving behind is closed transistor 204, so that D flip-flop 110 and comparer 106 are isolated.It should be noted that, after D flip-flop 110 is triggered, the latch-up signal 114 of its Q end points place output can be equal to the input signal at D end points place, according to embodiments of the invention, D end points place connects a noble potential, and therefore the latch-up signal of being exported 114 also is noble potential, and on the other hand, these latch-up signal 114 states only are admitted to a reset signal 126 at the CLR of D flip-flop 110 end points place, and these latch-up signal 114 states just can change.In other words, after the latch-up signal 114 that embedding controller 116 of the present invention is sent by D flip-flop 110 is controlled, unless embed the CLR end points that controller 116 sends out a reset signal 126 and D flip-flop 110, otherwise embedding controller will continue to be controlled by latch-up signal 114, even in the CLK of D flip-flop 110 end points place, one low-potential signal is arranged, 3021 parts as Fig. 3 square-wave waveform 302, be sent to CLK end points place, do not send any reset signal 126 and D flip-flop 110 as long as embed controller 116, embed controller 116 and will continue to be controlled by latch-up signal 114.Therefore, the present invention utilizes above-mentioned characteristic, allow an end that embeds controller 116 also the voltage detection signal of being exported by the OUT end points place of current detector 102 be monitored, after this signal is lower than a particular value, promptly send reset signal 126 and D flip-flop 110, allow embed the control that controller 116 breaks away from latch-up signal 114.Wherein this D flip-flop 110 can be selected the logical circuit of the model NC7SZ175 that FairChild company produced for use.
Still see also Fig. 2, when the embedding controller is controlled by latch-up signal 114, it can send a smi signal, change the SMI initial set value that embeds in the controller 116 simultaneously, wherein this smi signal is in order to there to be an interrupt event to take place in the announcement system, when basic input/output system (not showing among the figure) detect embed in the controller 116 the change of SMI initial set value after, can there be an interrupt event to take place by notice south bridge (not showing among the figure), this moment south bridge also can send-the STPCLK# signal gives central processing unit 120, when central processing unit 120 is received this STPCLK# signal, its inner clock pulse frequency can descend, reduce the consumption of power, wherein basic input/output system can set for according to need the clock pulse frequency that reduced for originally 50%, 60% or 87.5%.And on the other hand, embedding controller 116 of the present invention can continue to monitor the detection signal that is sent out by current detector 102 in the course of work of central processing unit 120, according to preferred embodiment design of the present invention, when going out overall power consumption, the signal reaction that detects has been lower than 75 watt-hours, represent the pending work of total system this moment not have much to do, embed controller 116 and promptly can send a reset signal 126 replacement D flip-flops 110, embedding controller 116 controlled by latch-up signal, embed controller 116 and can heavily fill out its inner SMI setting value this moment, inform that interrupt event no longer exists, when basic input/output system detect embed in the controller 116 the change of SMI setting value after, can disappear by notice south bridge interrupt event, south bridge 122 is no longer sent the STPCLK# signal and is given central processing unit 120 at this moment, this moment, central processing unit can be adjusted its inner clock pulse frequency voluntarily according to the state of the pending work of system, until excessive because of central processing unit 120 operating loads, the electric current 134 that causes the current-limiting resistance 104 of flowing through just can start dynamic adjustment power consumption device of the present invention this moment once more again greater than setting value.
See also and Figure 4 shows that the present invention dynamically adjusts central processing unit down conversion process process flow diagram.At first can detect the size of current of the current-limiting resistance of flowing through and send a detection signal in step 401 current detector, then can judge in step 402 place whether this detection signal size can be greater than a particular value, wherein the big I of this particular value is by the ultimate load of user according to computer system central processing unit desire load, that is set by acceptable power consumption.If this detection signal is less than this particular value size, can get back to step 401 and detect the size of current of the current-limiting resistance of flowing through once more, otherwise then entering step 403 sends warning signal, trigger frequency generator and D flip-flop respectively at step 404 with 405, wherein step 404 and 405 is to carry out simultaneously, and after being triggered in step 404 frequency generator, a STPCLK# signal is sent to central processing unit in step 410 place, carry out the frequency reducing of central processing unit, reach the function of instant reduction load.And on the other hand, when step 405, the caution signal that step 403 is sent can trigger a D flip-flop, to send latch-up signal control and to embed controller, and this latch-up signal can be when step 406, allowing the embedding controller change its inner SMI value sets, send smi signal simultaneously, when basic output/input system after step 407 receives this smi signal, can be in step 408 notice south bridge, sending STPCLK# signal and central processing unit, the frequency reducing of control central processing unit, wherein basic input/output system can set for according to need the clock pulse frequency that reduced for originally 50%, 60% or 87.5%.
See also and Figure 5 shows that the present invention dynamically adjusts the processing flow chart that central processing unit is not subjected to the STPCLK# signal controlling.At first can detect the size of current of the current-limiting resistance of flowing through in step 501 current detector, and send a detection signal and embed controller, then embed controller and can monitor this detection signal in step 502 place, and judge in step 503 whether the size of this detection signal can be less than a particular value, wherein the big I of this particular value by the user according to the computer system central processing unit in when work of treatment, whether this detection signal has reflected is lower than a predefined power consumption value, if in case be lower than default power consumption value, promptly represent the pending work of total system this moment not have much to do, therefore embed controller in step 504 and can send reset signal and D flip-flop with this D flip-flop of resetting, allow it no longer send latch-up signal, when step 505, embed controller simultaneously and can change its inner SMI value setting, after basic output/input system monitors the change of this smi signal in step 506, can be in step 507 notice south bridge, do not send STPCLK# signal and central processing unit again shown in step 508, this moment, central processing unit promptly can be adjusted the lifting situation of internal frequency automatically according to practical work amount situation.
Understand as the person skilled in the art, the above only is preferred embodiment of the present invention, is not in order to limit scope of patent protection of the present invention; All other do not break away from the equivalence of being finished under the disclosed spirit and changes or replacement, all should be included in the claim institute restricted portion.
Claims (15)
1. device of in computer system, dynamically adjusting the central processing unit consumed power, wherein the flow through electric current supply computer system of current-limiting resistance is required, it is characterized in that device comprises at least:
One current detector detects the size of current of current-limiting resistance of flowing through, and sends a testing result signal;
One comparer receives the testing result signal and compares with first preset value, if the testing result signal is promptly sent a caution signal greater than first preset value, otherwise can not send any signal;
One frequency generator, frequency generator can send a frequency reducing instruction and a central processing unit with the rated frequency of frequency generator after being triggered by caution signal;
One D flip-flop is by sending a latch-up signal after the caution signal triggering; And
One embeds controller, can embed the rewriting first time that controller system is handled the interruption setting value after receiving latch-up signal, and send out the basic input/output system of first system manipulation look-at-me notice computer system, the control south bridge interrupts setting value transmission frequency reducing instruction according to the system manipulation of rewriting for the first time and central processing unit carries out frequency reducing, embed controller simultaneously and can continue the monitoring and detection consequential signal, and it and second preset value is compared, and first pre-sets greater than second and pre-sets, if the testing result signal is promptly sent a reset signal and D flip-flop less than second preset value, remove latch-up signal, embed controller system manipulation interruption setting value this moment and can carry out the rewriting second time, and sending out second system manipulation look-at-me notice basic input/output system, the control south bridge interrupts setting value according to the system manipulation of rewriting for the second time removes central processing unit frequency reducing instruction.
2. dynamic adjustment central processing unit consumed power device as claimed in claim 1 is characterized in that, described first preset value is the ultimate load according to computer system central processing unit desire load, that is acceptable power consumption is set.
3. dynamic adjustment central processing unit consumed power device as claimed in claim 1 is characterized in that described first preset value is 90 watts.
4. according to claim 1 or the 3rd described dynamic adjustment central processing unit consumed power device, it is characterized in that described second preset value is 75 watts.
5. dynamic adjustment central processing unit consumed power device as claimed in claim 1 is characterized in that, described frequency reducing instruction is STPCLK#.
6. a device of dynamically adjusting the central processing unit consumed power is to use in computer system, wherein, have a basic input/output system and south bridge in the computer system, and an electric current of flowing through current-limiting resistance supplies computer system required electric current, it is characterized in that device comprises at least:
One current detector detects the size of current of current-limiting resistance of flowing through, and sends a testing result signal;
One comparer receives the testing result signal and it and first preset value is compared, and promptly sends a caution signal as if the testing result signal greater than first preset value, otherwise can not send any signal;
One frequency generator is by sending a frequency reducing instruction and a central processing unit with the rated frequency of frequency generator after the caution signal triggering;
One D flip-flop is by sending a latch-up signal after the caution signal triggering; And
One embeds controller, can embed the rewriting first time that controller system is handled the interruption setting value after receiving latch-up signal, and send out first system manipulation look-at-me notice basic input/output system, the control south bridge interrupts setting value transmission frequency reducing instruction according to the system manipulation of rewriting for the first time and central processing unit carries out frequency reducing, embed controller simultaneously and can continue the monitoring and detection consequential signal, and it and second preset value is compared, and first preset value pre-sets greater than second, if the testing result signal is promptly sent a reset signal and D flip-flop less than second preset value, remove latch-up signal, embed controller system manipulation interruption setting value this moment and can carry out the rewriting second time, and sending out the second system manipulation interrupt notification basic input/output system, the control south bridge interrupts setting value according to the system manipulation of rewriting for the second time removes central processing unit frequency reducing instruction.
7. dynamic adjustment central processing unit consumed power device as claimed in claim 6 is characterized in that, described first preset value is the ultimate load according to computer system central processing unit desire load, that is acceptable power consumption is set.
8. dynamic adjustment central processing unit consumed power device as claimed in claim 6 is characterized in that described first preset value is 90 watts.
9. dynamic adjustment central processing unit consumed power device as claimed in claim 6 is characterized in that described second preset value is 75 watts.
10. dynamic adjustment central processing unit consumed power device as claimed in claim 6 is characterized in that, described frequency reducing instruction is STPCLK#.
11. a method of dynamically adjusting the central processing unit consumed power is to use in computer system, wherein, have a basic input/output system and south bridge in the computer system, and an electric current of flowing through current-limiting resistance supplies computer system required electric current, it is characterized in that method comprises at least:
The detection size of current of current-limiting resistance of flowing through, and send a testing result signal;
The testing result signal and first preset value are compared,, otherwise can not send any signal if the testing result signal is promptly sent a caution signal greater than first preset value;
Trigger a frequency generator with caution signal, and send the frequency reducing instruction and the central processing unit of a tool characteristic frequency;
Trigger behind the D flip-flop and send a latch-up signal with caution signal; And
Utilize latch-up signal control one to embed controller, send out the first system manipulation look-at-me and notify this basic input/output system, and rewrite the embedding controller system for the first time and handle the interruption setting value, when basic input/output system monitors the change that system manipulation interrupts setting value, the notice south bridge interrupts setting value transmission frequency reducing instruction according to the system manipulation of rewriting for the first time and central processing unit carries out frequency reducing, embed controller and can continue the monitoring and detection consequential signal, and it and second preset value is compared, and this first preset value pre-sets greater than second, if the testing result signal is promptly sent a reset signal and D flip-flop less than second preset value, remove latch-up signal, embed controller system manipulation interruption setting value this moment and can carry out the rewriting second time, and sending out second system manipulation look-at-me notice basic input/output system, the control south bridge interrupts setting value according to the system manipulation of rewriting for the second time removes central processing unit frequency reducing instruction.
12. dynamic adjustment central processing unit consumed power method as claimed in claim 11 is characterized in that, described first preset value is the ultimate load according to computer system central processing unit desire load, that is acceptable power consumption is set.
13. dynamic adjustment central processing unit consumed power method as claimed in claim 11 is characterized in that described first preset value is 90 watts.
14. dynamic adjustment central processing unit consumed power method as claimed in claim 11 is characterized in that described second preset value is 75 watts.
15. dynamic adjustment central processing unit consumed power method as claimed in claim 11 is characterized in that, described frequency reducing instruction is STPCLK#.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02143996 CN1220927C (en) | 2002-09-28 | 2002-09-28 | Apparatus for dynamically regulating computer system power consumption |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02143996 CN1220927C (en) | 2002-09-28 | 2002-09-28 | Apparatus for dynamically regulating computer system power consumption |
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| Publication Number | Publication Date |
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| CN1485707A CN1485707A (en) | 2004-03-31 |
| CN1220927C true CN1220927C (en) | 2005-09-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 02143996 Expired - Lifetime CN1220927C (en) | 2002-09-28 | 2002-09-28 | Apparatus for dynamically regulating computer system power consumption |
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| Country | Link |
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| CN (1) | CN1220927C (en) |
Families Citing this family (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100347679C (en) * | 2004-07-16 | 2007-11-07 | 佛山市顺德区顺达电脑厂有限公司 | System power supply monitoring apparatus |
| CN1949128A (en) | 2005-10-14 | 2007-04-18 | 鸿富锦精密工业（深圳）有限公司 | Central processor frequency regulating circuit |
| CN102043458B (en) * | 2009-10-19 | 2013-03-20 | 英业达股份有限公司 | Detection method for detecting management function of dynamic power node manager |
| CN105739668A (en) * | 2016-01-20 | 2016-07-06 | 合肥联宝信息技术有限公司 | Power management method and power management system of notebook computers |
| CN107228087B (en) * | 2016-03-25 | 2019-06-25 | 台达电子工业股份有限公司 | A kind of monitoring circuit and monitoring method |
| CN106708232B (en) * | 2017-02-28 | 2019-09-24 | 联想(北京)有限公司 | A kind of electronic equipment and control method |
| CN107102631A (en) * | 2017-04-10 | 2017-08-29 | 成都因纳维特科技有限公司 | A kind of system and method for controlling vehicle mounted guidance terminal cpu frequency and running number |
| CN107340846B (en) * | 2017-08-31 | 2023-07-14 | 广东虹勤通讯技术有限公司 | Power-down prevention logic circuit and notebook computer |
| CN116774804A (en) * | 2023-08-18 | 2023-09-19 | 合肥联宝信息技术有限公司 | Power supply control circuit and method and electronic equipment |
-
2002
- 2002-09-28 CN CN 02143996 patent/CN1220927C/en not_active Expired - Lifetime
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| Publication number | Publication date |
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| CN1485707A (en) | 2004-03-31 |
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