CN1219056A

CN1219056A - Buffer withs imultaneous asynchronous read and write

Info

Publication number: CN1219056A
Application number: CN 98103535
Authority: CN
Inventors: 徐元欣; 王匡; 袁雪芬
Original assignee: Hi-Tech Research & Development Center State Science & Technology Commission
Current assignee: Hi-Tech Research & Development Center State Science & Technology Commission
Priority date: 1998-07-31
Filing date: 1998-07-31
Publication date: 1999-06-09
Anticipated expiration: 2018-07-31
Also published as: CN1090859C

Abstract

The present invention relates to a buffer used in data code speed regulator in communication, especially buffer with simultaneous asynchronous read and write constituted with combined single-port RAM to replace double-port RAM. The buffer includes memory, comparator and decoder, and features that it also has M selectors, M ADN gates and 2M tristate gates. The decoder includes read address higher Ah bit decoder and write address higher Ah bit decoder, the selector is 1-of-2 selector, and the memory consists of M small single-port RAM modules. The code speed regulating module can be combined organically with other modules in data transmission system to reduce system cost.

Description

Has the buffer of asynchronous read and write simultaneously

The buffer devices that uses in the data yardage adjusting device in the present invention relates to communicate by letter.

In transfer of data, often have the justification module of data, constitute by the clock relevant of the buffer with FIFO (push-up storage) function, control circuit when this modular circuit realizes, see Fig. 1 with it.The input data are with fm speed write buffer, simultaneously dateout is read with fout speed, and this just requires this buffer to have FIFO (push-up storage) function (tentation data is first in first out) and asynchronous read and write (because the read-write clock is generally different) simultaneously.The data writing format of writing controller control input, the form of Read Controller control dateout.This buffer generally has ready-made FIFO (push-up storage) device or realizes with dual-ported memory, need increase read/write address when realizing with dual-ported memory and produce circuit and read-write control circuit.

Because chip-scale is limited, it is fewer that inside has other logical block of PLD (programming device) of FIFO (push-up storage) or dual-ported memory, just not competent to realizing the monolithic PLD of system (programming device) that complex data handles.

The objective of the invention is to adopt the combination of fritter one-port memory (will have only the memory of an address and FPDP to be called one-port memory (being called for short RAM) herein) to replace dual-ported memory to constitute buffer with while asynchronous read and write.

The object of the present invention is achieved like this.Single port RAM only has an address, a data port, can not carry out the read and write operation simultaneously, and we combine a plurality of single port RAM fritters, read and write different RAM fritter (promptly write a certain, read another piece) respectively.M RAM fritter (its capacity is N * k position) combined, add and write its peripheral address, read-write control circuit just to have constituted capacity be the buffer of M * N * k, the width of tentation data transmission here is k.Only otherwise operate, just can reach the function that reads while write of dual-ported memory fully at same RAM fritter, thus the buffering of realization data.

Below in conjunction with drawings and Examples the present invention is further described.

Fig. 1, existing justification module.

Fig. 2, buffer of the present invention constitute schematic diagram.

The port figure of Fig. 3, embodiment buffer.

Buffer of the present invention is called simulated dual port ram buffer.A kind of buffer of asynchronous read and write simultaneously, comprise memory 1, comparator 2 and decoder 3, its special sheet be also to be provided with M selector 4, with door 5 and 2M triple gate 6, wherein decoder 3 is to read high Ah bit decoder in address and the high Ah bit decoder of write address, selector 4 is 2 to select 1 selector, and memory 1 is made up of M single port RAM fritter; Low AI position connects " 1 " end of selector 4 among the write address bus AW, read " O " end of low AI position connection selection 4 devices among the address bus AR, high Ah position connects the input of the high Ah decoder 3 of write address among the write address bus AW, its M decoding output connects the control end of M selector 4 and the control end of M triple gate 6 respectively, the address input end of M the RAM fritter of output butt joint of M selector 4; M of write address Ah bit decoder 3 decoding output connect respectively M with 5 input, be connected with the Writing/Reading signal with another input of door 5, with the output termination RAM fritter Writing/Reading control end of door 5; Read that high Ah position connects the input of reading the high Ah bit decoder 3 in address among the address bus AR, its M decoding output is connected with the control end of M triple gate 6 respectively, the input of M triple gate 6 is corresponding to be connected with the data terminal of M RAM fritter, triple gate 6 export readout data bus DR to; Write data/address bus DW and be connected with the input of M triple gate 3, the output of M triple gate 3 is corresponding to be connected with the data terminal of M RAM fritter; High Ah position connects the P input of comparator 2 among the write address bus AW, reads the Q input that high Ah position among the address bus AR connects comparator 2, and the output of comparator 2 connects the read/write conflict indication.

It is as follows that its realization reads while write process:

The low AI position of write address bus AW is selected the address (AI position) of 1 selector (4) as each RAM fritter with the low AI position of reading address bus AR by 2, and the capacity of each RAM fritter is that (k is the bit width of transmission data units, N=2 in N * k position ^A1Unit number for the RAM fritter); M (M=2 after the high Ah position of write address bus AW deciphered ^Ah) the position signal selects the selection signal of 1 selector (4) as 2 of each RAM fritter address, suppose that decoding value is P, then the operation address of P#RAM fritter is the low AI of write address bus AW, the data that the triple gate (6) of opening this P#RAM fritter simultaneously will write data/address bus DW input to this RAM fritter, and the write signal W of this RAM fritter of gating is 1, this RAM fritter is carried out write operation, data are write the AI determining unit of the AW of this RAM fritter, the operation address of other RAM fritter is the low AI that reads address bus AR, and its Writing/Reading is 0 promptly it to be carried out read operation.M (M=2 after the high AI position of reading address bus AR deciphered ^Ah) the position signal is as the data strobe signal of each RAM fritter, suppose decoding value position Q, the triple gate (6) of the dateout of Q#RAM fritter then by opening, the data of the unit that the low AI that reads address bus AR is definite are delivered to readout data bus DR.As long as any moment P ≠ Q does not promptly read while write same block RAM, just guarantee that the read-write of this simulated dual port ram buffer is normal.Read while write same block RAM when P=Q, then read/write conflict makes the data of read-write undesired.

Make this analog port RAM buffer operate as normal,, data can be read and write normally as long as the minimum interval of address AW, the AR of control read-write just can guarantee not read while write same block RAM fritter greater than the code word capacity N of RAM fritter.

The periphery of buffer of the present invention increases by what counter was formed reads address production electric circuit and write address generation circuit, and write address bus AW is connected with the write address output, read address bus AR and read address output end and be connected, constitute a numeric data code velocity modulation mould preparation piece circuit, be used for transfer of data (communication).

As from the foregoing, can realize FIFO (push-up storage) function fully, to realize the data justification in the transfer of data with the combination of RAM fritter.

Claims

1, a kind of buffer of asynchronous read and write simultaneously, comprise memory 1, comparator 2 and decoder 3, it is characterized in that also being provided with M selector 4, with door 5 and 2M triple gate 6, wherein decoder 3 is to read high Ah bit decoder in address and the high Ah bit decoder of write address, selector 4 is 2 to select 1 selector, and memory 1 is made up of M single port RAM fritter; Low AI position connects " 1 " end of selector 4 among the write address bus AW, read " O " end of low AI position connection selector 4 among the address bus AR, high Ah position connects the input of the high Ah decoder 3 of write address among the write address bus AW, its M decoding output connects the control end of M selector 4 and the control end of M triple gate 6 respectively, the address input end of M the RAM fritter of output butt joint of M selector 4; M of the high Ah bit decoder 3 of write address decoding output connect respectively M with 5 input, be connected with the Writing/Reading signal with another input of door 5, with the output termination RAM fritter Writing/Reading control end of door 5; Read that high Ah position connects the input of reading the high Ah bit decoder 3 in address among the address bus AR, its M decoding output is connected with the control end of M triple gate 6 respectively, the input of M triple gate 6 is corresponding to be connected with the data terminal of M RAM fritter, triple gate 6 export readout data bus DR to; Write data/address bus DW and be connected with the input of M triple gate 3, the output of M triple gate 3 is corresponding to be connected with the data terminal of M RAM fritter; High Ah position connects the P input of comparator 2 among the write address bus AW, reads the Q input that high Ah position among the address bus AR connects comparator 2, and the output of comparator 2 connects the read/write conflict indication.

2, press the application of the described buffer of claim 1, it is characterized in that peripheral the increasing by what counter was formed of buffer read address production electric circuit and write address generation circuit, and write address bus AW is connected with the write address output, read address bus AR and read address output end and be connected, constitute a numeric data code velocity modulation mould preparation piece circuit.