CN1211826A - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
CN1211826A
CN1211826A CN98119811A CN98119811A CN1211826A CN 1211826 A CN1211826 A CN 1211826A CN 98119811 A CN98119811 A CN 98119811A CN 98119811 A CN98119811 A CN 98119811A CN 1211826 A CN1211826 A CN 1211826A
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groove
semiconductor device
region
type
conduction type
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二宫仁
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NEC Corp
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NEC Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66674—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/66712—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/66734—Vertical DMOS transistors, i.e. VDMOS transistors with a step of recessing the gate electrode, e.g. to form a trench gate electrode
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7811—Vertical DMOS transistors, i.e. VDMOS transistors with an edge termination structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

An MOSFET semiconductor device provided by the invention has an epitaxially grown N-field relaxation region on an N-type semiconductor substrate, a P-type body region formed at specified depth from the surface of this relaxation region, an N source region selectively formed from the surface of the body region, a trench formed in the substrate direction from the source region surface, penetrating through the source region and body region to reach the field relaxation region, and a gate electrode provided in the trench through an insulation film on inner wall of the trench. The trenches are disposed as a mesh structure and interconnected at their terminal ends through an edge trench to remove a special structure of a top end of the trench which results concentrating of an electric field, thereby improving the source-drain withstand voltage and insulation of the gate insulation film.

Description

Semiconductor device
The present invention relates to a kind of semiconductor device such as power MOSFET (metal-oxide semiconductor fieldeffect transistor) and IGBT (igbt) of controlling high voltage and electric current, and be particularly related to the insulated-gate semiconductor device that a kind of length direction that comprises the sidewall of the raceway groove that forms on the substrate is formed with raceway groove.
The application is based at the flat 9-269202 of the number of patent application No. of Japanese publication, with reference to it its content is comprised wherein.
In the ordinary course of things, the power semiconductor such as MOSFET and IGBT of control high voltage and electric current all is that form with the MOS device forms usually.The composition of MOS device generally includes epitaxially grown weakened region of the one deck that is formed on the semiconductor chip, one deck diffusion layer that be called base (or tagma) opposite with the conductivity model of field weakened region, that is to say, electric current wherein flows along the direction opposite with the field weakened region, and another layer diffusion layer that be called source region identical with the conductivity model of field weakened region, that is to say that electric current wherein flows along the direction identical with the field weakened region.
Fig. 1 illustrates the power MOSFET as example that forms with this structure.The composition of MOSFET comprises one deck field weakened region 102 that is formed on the semiconductor chip 101, conductivity model on the contrary and direction of current flow wherein is called the diffusion layer 103 of base with opposite one deck in the weakened region and conductivity model is identical and direction of current flow wherein and identical one deck of a weakened region are called the diffusion layer 104 in source region, one deck gate oxide 105, one deck gate electrode 106, one deck interlayer insulating film 107, and one deck source electrode 108.The semiconductor device of said structure is commonly referred to as planar device.When such transistor is converted to conducting state, on the surface of substrate with regard to horizontal the raceway groove of this semiconductor device.Owing to the width that dwindles gate electrode 106 for the increase integrated level is restricted, thereby almost be to be difficult to improve integrated level.
Fig. 2 illustrates to overcoming the improvement structure of the MOSFET that above-mentioned defective makes.Improving structure is the semiconductor device of a MOS, it comprises epitaxially grown the weakened region 202 of the one deck that is formed on the semiconductor chip 201, the identical diffusion layer that is called the source region 204 in the opposite diffusion layer 203 that is called base (or tagma) in one deck direction of current flow wherein and the weakened region 202 and one deck direction of current flow wherein and the field weakened region 202.And, in this improved semiconductor device, arrive a weakened region 202 by source region 204 and base 203 and form a groove.
By forming above-mentioned structure, because channel region is to form along the vertical direction on the substrate surface, even shortened the width of gate electrode 206, channel length is guaranteed, this just might realize higher integrated level.This structure is commonly referred to " groove-shaped " structure.
Slot type structure is convenient to realize the integrated level higher than plane.Yet, find that in performance test trench type device has a shortcoming, exactly when the field weakened region of two types of devices and the impurity concentration in the base remain on same level, low than in the planar device of withstand voltage between the source of trench type device and the leakage.
In order to overcome low withstand voltage shortcoming, in the flat 6-214628 of No. that announces first of Japanese patent application, a kind of way was as shown in Figure 3 proposed.This proposal be will by form than trench bottom darker base 303 and from forming a NPN (or PNP) structure between the diffusion region 309 of trench bottom surfaces formation to make up a vertical MOSFET.This structure has weakened the electric field of channel bottom and has avoided electric field to concentrate on the bottom of groove deeply than the bottom surface of groove because of the base; Thereby might restrain the withstand voltage shortcoming that is lower than planar device of newspaper trench type device.
As shown in Figure 7, in order to improve the high current capacity of this grooved semiconductor device, build up mesh or the trellis form that comes down to expand channel width as the groove of the gate electrode of imbedding.Yet these ends that like the sieve lattice of groove well but are formed on the outermost edge of chip like the comb point that " some end " respectively arranged.This problem (Fig. 5) with regard to having occurred concentrating at each top end electric field, it need form one deck diffusion layer 602 that conduction type is identical with the base as shown in Figure 6, extends deeplyer than groove 601.
Yet, even formed the identical darker diffusion layer of such one deck conductivity model in the end of groove 601, but because of at the gate insulation layer of groove 601 ends near substrate surface, it makes the puncture voltage of gate insulation layer be reduced to other position that is lower than chip.This is lower than the problem of planar device with regard to the puncture voltage of having brought trench type device, also is like this under the identical situation of the gate insulation layer thickness of two kinds of devices even.
Thereby the objective of the invention is to provide a kind of way of avoiding producing the electric field of concentrating in groove ends.Make in having the semiconductor device of imbedding the gate electrode in the groove withstand voltage between the unlikely reduction leakage and source.
Fig. 1 illustrates the profile of a conventional plane bilateral diffusion MOS FET.
Fig. 2 illustrates the profile of a conventional groove-shaped bilateral diffusion MOS FET.
Fig. 3 illustrates the profile of a conventional groove-shaped bilateral diffusion MOS FET.
Fig. 4 illustrates the plane graph of groove ends at the outermost chip edge place of a conventional groove-shaped bilateral diffusion MOS FET.
Fig. 5 illustrates the profile of groove ends at the outermost chip edge place of a conventional groove-shaped bilateral diffusion MOS FET.
Fig. 6 illustrates the profile of the deep-well that the outermost chip edge place of a conventional groove-shaped bilateral diffusion MOS FET is provided with.
Fig. 7 illustrates the profile of groove ends at the outermost chip edge place of a conventional groove-shaped bilateral diffusion MOS FET.
Fig. 8 illustrates the profile of groove ends at the outermost chip edge place of the groove-shaped bilateral diffusion MOS FET of the present invention.
Fig. 9 illustrates the profile of groove ends at outermost chip edge place of the groove-shaped bilateral diffusion MOS FET of first embodiment of the invention.
Figure 10 A to 10D illustrates the production stage of the semiconductor device of first embodiment of the invention.
Figure 11 illustrates the profile of groove ends at outermost chip edge place of the groove-shaped bilateral diffusion MOS FET of second embodiment of the invention.
Figure 12 A to 12D illustrates the production stage of the semiconductor device of second embodiment of the invention.
Because the top can cause electric field to concentrate, the objective of the invention is will be by eliminating each groove end The special construction at end place improves the insulating properties of gate insulating film. In fact, as shown in Figure 8, this The semiconductor devices of invention is provided with an edge groove, in order to the end of each groove and all other Link to each other, in order to eliminate the special construction on groove top; Thereby the raising source and leak between also withstand voltage Significantly improve the insulating properties of gate insulating film.
Fig. 9 illustrates the profile of semiconductor device of the present invention.In Fig. 9, on the back side of the semiconductor chip 901 that first conduction type is arranged, form the drain electrode (not shown), and the upside of substrate 901 be formed with the field weakened region 902 of first conduction type and second conduction type is arranged and its electric current along base 903 that the rightabout with first conductivity regions flows.903 inboards, base on semiconductor device surface are formed with the source region 904 of first conduction type.Pass source region 904 and base 903 arrival electric field weakened regions, 902 formation grooves from the surface towards substrate surface.Be filled with material that forms transistor gate 906 and sidewall and bottom surface and gate electrode 906 isolation that make groove with the insulating material 905 of silicon dioxide and so in the groove.
Be arranged in semiconductor chip transistor chip edge each trellised groove end with link to each other for being connected the gate material 909 that the terminal edge groove of establishing of the transistorized trellis groove of each separate unit filled out.Source region 904 links to each other with the source electrode made from the electric conducting material of metal and so on 908, and source electrode 908 remains on the same current potential with the base.906 of source electrode 908 and gate electrodes are isolated mutually by one deck interlayer insulating film 907.Thereby, as previously mentioned, be built into the MOS transistor that is respectively equipped with gate electrode, source and leakage.
Operation to first embodiment of the invention is described with reference to accompanying drawing in the back.When adding a voltage between drain electrode of MOS transistor shown in Fig. 9 and source electrode, if the potential difference between grid and the source electrode surpasses the threshold voltage of MOS transistor, transistor just is opened.When adding voltage between source and drain electrode, if potential difference is zero, the MOS transistor of this moment just is in closed state.
Be added in Lou and the voltage between the electrode of source is applied on the PN junction between electric field weakened region 902 and the base 903.That is to say, stretch one deck depletion layer from PN junction to electric field weakened region 902, and apply voltage by the length that exhausts.Groove ends makes up by cell transistor with being equal to, does not produce (representing with the X mark) the electric field centrostigma as shown in Fig. 5 and 7; Thereby, withstand voltage between leakage that need not to adopt dark diffusion region just can improve MOS transistor and the source.
When keep leaking and source electrode when adding voltage when being in same current potential between grid and source electrode, if gate insulating film 905 made by thermal oxidation, then electric field surpasses 8MV/cm and will puncture.In the conventional structure shown in Fig. 5 and 7, because electric field concentrates on the end, the groove end resembles and will be punctured most.In contrast, produce the position that electric field is concentrated, just might improve withstand voltage between the grid of MOS transistor and the source electrode owing to eliminated in the present embodiment.
Figure 10 illustrates the production stage that applies the present invention to require to have leak and between the source the withstand voltage N channel enhancement power MOSFET of 30V.
At first, has the N type epitaxial loayer that resistivity is 0.3-0.6 at the growth one deck of mixing on the arsenic N type substrate with 0.001-0.006 Ω cm resistivity.This one deck N type epitaxial loayer forms electric field weakened region 1002 (Figure 10 (A)).
Subsequently, through photoetching, the groove that gate electrode position selectivity forms 0.5 to the 1.5 μ m width and 1.0 to the 2.0 μ m degree of depth is being set.The end of each groove is linked to each other by the outermost groove 1009 that is positioned at chip edge; Aforesaid in order to eliminate " top ".The inwall of groove uses the film of the 500 dust thickness that formed by thermal oxidation to cover then.The heat oxide film of these one deck 500 dusts is used for the gate insulating film 1005 of MOS transistor.Subsequently, form the polysilicon film of 8000 dust thickness and in polysilicon film, spread phosphorus to form one deck N type polycrystal layer therein through thermal diffusion.N type polysilicon film by on the anisotropic etching removal semiconductor chip stays the N type polysilicon in the groove.Stay the gate electrode (Figure 10 (B)) that N type polysilicon film in the groove is used for MOS transistor.
By carrying out on (on the surface of electric field weakened region) on the substrate surface that ion injects and heat treatment, be located at the diffusion layer that one deck on the electric field weakened region will be used for base 1003 and form a PN junction at 1.0 to 1.9 μ m degree of depth places by carrying out subsequently.Then by utilizing photoetching technique to carry out the selectivity ion injection of BF2 and determining that at 1.0 to the 1.9 μ m degree of depth places formation PN junction one deck is used for the diffusion layer of back gate contact zone 1010 by heat treatment subsequently.And, inject and heat treatment by subsequently forms PN junction the diffusion layer (Figure 10 (C)) that one deck is used for the source region is set at 1.0 to 1.9 μ m degree of depth places by the ion that utilizes photoetching technique to carry out selectivity arsenic.
Subsequently, growth PSG (phosphorosilicate glass) forms the film of 6,000 to 10,000 angstroms depths, and utilizes photoetching technique to carry out anisotropic selective etching and remove the surface that this layer growth layer exposes back gate contact zone 1010 and source region 1004.The psg film that stays after the etching is used as interlayer insulating film 1007 (Figure 10 (D)).
By the aluminum metal film of sputtering deposit 3.0 to 5.0 μ m thickness, and the part that stays by the removal of anisotropy selective etching forms source electrode 1008 (Fig. 9).
When adding a voltage in the source of the power MOSFET that forms like this with between leaking when making short circuit between grid and the source keep transistor to be in closed state, this voltage just fills on the PN junction that is downloaded between base 903 and the electric field weakened region 902, and this voltage equally also is to fill to be downloaded on the depletion layer that stretches in electric field weakened region 902.
Power MOSFET of the present invention does not have groove " top ", and the edge at transistor chip does not concentrate with regard to accumulation and electric field not occurring like this.In addition, because MOSFET of the present invention does not contain the top in the conventional device, when between grid and source, adding a voltage, although voltage is to be added on the gate oxidation films.Also can not produce electric field in transistor chip edge concentrates.
Figure 11 illustrates the profile of second embodiment of the invention.As shown in Figure 11, be provided with the drain electrode (not shown) of first conduction type at the dorsal part of substrate 1101.On the upper surface of substrate 1101, form first conduction type electric field weakened region 1102 and with the base 1103 of second conduction type of first conductivity type opposite.In the base of substrate surface, form the source region 1104 of first conduction type.Pass source region 1104 and base 1103 from the top towards the back back side of substrate and arrive electric field weakened region 1102 formation one groove.Groove is filled with the material as gate electrode 1106.The top of gate electrode and the inwall of groove and diapire are isolated with the insulating material 1105 of silica and so on.The inwall of groove is made smoothly through the high-temperature oxydation under 1000 ℃.The groove of transistor edge is terminal to link to each other with an edge groove 1109 of being located at the transistor edge.Edge groove 1109 is will divide other groove end to couple together with the gate material of inserting in the edge groove.Source region 1104 at substrate surface links to each other with the source electrode of being made by the material that resembles metal 1108, and source electrode 1108 and gate electrode are remained in identical current potential.Source electrode 1108 is separated by interlayer insulating film 1107 with base electrode.MOS transistor is just according to top illustrated formation.
Then, in the back the running of the semiconductor device of second embodiment of the invention is described.
When adding a voltage between leakage of the MOS transistor shown in Figure 11 and source electrode, as long as the potential difference between grid and the source electrode surpasses threshold voltage, MOS transistor just is opened.Even when adding a voltage between leakage and the source electrode, as long as the potential difference between grid and the source electrode is zero (same current potential), MOS transistor of the present invention just remains on closed state.
Be added in Lou and the voltage between the electrode of source is accounted for altogether by the PN junction of electric field weakened region 1102 and base 1103.That is to say that depletion layer stretches to electric field and weakens layer 1102, voltage is then occupied by depletion layer length.Groove of the present invention terminal with cell transistor in identical, and do not cause the concentrated top (representing) of electric field with the X mark; Thereby, just might improve withstand voltage between the leakage of MOS transistor and the source.
Situation conversely is, when leaking and the source electrode remains in same current potential, and when adding voltage between grid and the source electrode, if gate insulating film 1105 is made through thermal oxidation, then punctures when voltage is higher than 8MV/cm.In conventional structure, as shown in Fig. 5 and 7, electric field concentrates on the groove end.Yet device of the present invention does not have to occur the position that electric field is concentrated, and makes the groove inboard smooth through thermal oxidation before gate insulating film 1105 forms, so just further withstand voltage between raising grid and the source.
Experiment shows, even the formed condition of gate oxide of the groove inboard of trench MOSFET is the same with the condition of formation 500 dust gate oxides in the plane MOSFET manufacturing, as long as have particular point in the groove, the dielectric voltage withstand of oxide-film will descend about 30% to 50%.Yet because device of the present invention does not have such particular point, the dielectric voltage withstand of the gate oxide almost situation with plane MOSFET is identical.
Figure 12 illustrate use provided by the present invention have leak and the source between the production stage of the withstand voltage N channel enhancement power MOSFET of 30V.
The epitaxial loayer that on substrate, has 0.3 to 1.0 Ω cm resistivity with arsenic doping growth one deck 5 to 10 μ m thickness with 0.001 to 0.006 Ω cm resistivity.This one deck N type epitaxial loayer weakens layer 1202 (Figure 12 (A)) as electric field.
Subsequently, form the groove of 1.1 to the 1.9 μ m degree of depth and 0.5 to 1.5 μ m width with photoetching technique, and the end of each groove is linked to each other with the groove 1209 of outermost edge.High-temperature oxydation under by 1000 ℃ make trench wall smooth after, remove the oxide layer that forms through oxidation.Form the heat oxide film of 500 dusts then.The heat oxide film of this layer 500 dust is as the gate insulating film 1205 of MOS transistor.The layer thickness of growing reaches the polysilicon layer of 8000 to 12000 dusts, and spreads phosphorus through thermal diffusion in polysilicon layer, forms N type polysilicon layer.After anisotropic etching, remove N type silicon layer and only stay the interior polysilicon layer of groove.Stay the gate electrode 1206 (Figure 12 (B)) of the interior polysilicon layer of groove as MOS transistor.Carry out the boron ion to substrate surface (on the surface of electric field weakened region) (Figure 10 (D)) and inject, and, weaken the diffusion layer that is formed for base 1203 on the layer, the knot of a degree of depth 1.1 to 1.9 μ m is provided at electric field through subsequently heat treatment.Inject and subsequently heat treatment is formed for the diffusion layer of contact zone, base 1210 in base 1203 by BF2 ion optionally, it is the knot of 0.3 to 0.6 μ m that a thickness is provided.And, utilizing photoetching technique to carry out the selectivity arsenic ion and inject, and heat-treat the diffusion layer that is formed for source region 1204 subsequently, it is the knot (Figure 12 (C)) of 0.3 to 0.6 μ m that thickness is provided.
Subsequently, the PSG film of growth one deck 6,000 to 10,000 dust thickness, and utilize photoetching technique to carry out anisotropic selective etching removal film and expose the surface of back gate contact zone 1210 and the surface in source region 1204.The psg film that stays after the etching is used as interlayer insulating film 1207 (Figure 12 (C)).
Then, the aluminum metal film that forms 3.0 to 5.0 μ m thickness by sputter forms source electrode 1208 and gate electrode, then carries out anisotropy selective etching removal aluminium film by reactive ion etching (RIE) method of utilizing photoetching technique and stays these electrodes (Figure 11).
When adding a voltage between this transistorized leakage and source when the power MOSFET that makes the such manufacturing of short circuit maintenance between grid and the source is in closed state, this voltage just fills and is loaded on the gate oxide.Yet, because device of the present invention does not have in the conventional power MOSFET formed top and owing to the raceway groove inwall becomes smooth through high-temperature oxydation, concentrating of electric field just can not appear in device of the present invention in the gate oxide at cell transistor outermost edge place, this has just improved the puncture voltage of gate oxide.
As mentioned above, the invention provides a kind of semiconductor device, its groove end at chip outermost edge place is connected in the edge groove to eliminate the top shape special construction of groove end, makes Lou and withstand voltage between the source can be obtained and increase and the insulation property of gate insulation layer are significantly improved.

Claims (6)

1, a kind of semiconductor device of insulated-gate type is characterized in that, it comprises:
One is formed on the field weakened region of first conduction type on the semiconductor chip of first conduction type;
One from the tagma of described weakened region with second conduction type of desired depth formation.
One selects the source region of first conduction type that forms from the surface in described tagma;
One rises towards substrate surface with surface, described tagma and to pass described source region and described tagma arrives the groove that described electric field weakened region forms by etching; And
Be located at gate electrode in the groove once covering one deck dielectric film that trench wall forms;
Whole ends of wherein said groove interconnect and make it can not form the top.
According to the described semiconductor device of claim 1, it is characterized in that 2, described first conduction type is the N type, described second conduction type then is the P type.
According to the described semiconductor device of claim 1, it is characterized in that 3, described first conduction type is the P type, described second conduction type then is the N type.
According to the described semiconductor device of claim 1, it is characterized in that 4, described groove comprises and is formed on the lip-deep a plurality of grooves that comprise described source region, and whole ends of a plurality of grooves are interconnected by an edge groove that is located at the outermost edge place.
5, according to the described semiconductor device of claim 1, it is characterized in that, described groove comprises the groove that is formed on the lip-deep a plurality of sieve trellis configurations that comprise described source region, and whole ends of these grooves are interconnected by an edge groove that is located at the outermost edge place.
According to the described semiconductor device of claim 1, it is characterized in that 6, the smooth treatment of once being undertaken by oxidation is stood in the inwall of described groove and bottom surface.
CN98119811A 1997-09-17 1998-09-14 Semiconductor device Pending CN1211826A (en)

Applications Claiming Priority (2)

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JP9269202A JPH1197689A (en) 1997-09-17 1997-09-17 Semiconductor device
JP269202/97 1997-09-17

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CN1211826A true CN1211826A (en) 1999-03-24

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