CN1209810C - 3-D space element structure for internal-inlaid storage logical circuitand making method thereof - Google Patents
3-D space element structure for internal-inlaid storage logical circuitand making method thereof Download PDFInfo
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- CN1209810C CN1209810C CN 02105011 CN02105011A CN1209810C CN 1209810 C CN1209810 C CN 1209810C CN 02105011 CN02105011 CN 02105011 CN 02105011 A CN02105011 A CN 02105011A CN 1209810 C CN1209810 C CN 1209810C
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Abstract
The present invention relates to a three-dimensional space element structure for a built-in memory logic circuit and a manufacturing method thereof, which is mainly characterized in that a memory device is formed on a concave area (on a silicon substrate), and a logic circuit is formed on a convex area (on an SOI substrate); the logic circuit is formed on the convex area so as to increase the action speed of components, and since the memory and the logic circuit are respectively formed on the concave area and the convex area, the height difference of the two areas, namely the memory and a logic component, can be decreased after the two areas are completed.
Description
Technical field
The present invention relates to a kind of embedded memory logic circuit, particularly relevant for a kind of three dimensions component structure that is applied to embedded memory logic circuit and preparation method thereof.
Background technology
In known semiconductor fabrication process, as at United States Patent (USP) the 6th, 272, No. 054 with described in No. the 594997th, the Taiwan patent, embedded memory logic circuit (Embedded-Memory LogicCircuit) is that logic (Logic) device and storage (Memory) device are formed at above the chip simultaneously, this kind device that is so-called embedded semiconductor storage, for example ERAM (Embedded Random Access Memory) device.
But, along with the integrated level of integrated circuit increases day by day, storage device on same chip mixes setting with logic device, its to each other can because of on the processing procedure with structural different generation one height fall values, cause connector contact hole depth-to-width ratio (aspect ratio) increasing, can't meet the demand of present embedded semiconductor memery device.
Summary of the invention
In view of this, in order to address the above problem, main purpose of the present invention is to provide a kind of three dimensions component structure that is applied to embedded memory logic circuit and preparation method thereof, memory and logical circuit are respectively formed at depressed area and convex region, so that reduce the difference in height between two zones (memory and logic element), reduce the depth-to-width ratio of connector contact hole.
For achieving the above object, the present invention proposes a kind of manufacture method that is applied to the three dimensions element of embedded memory logic circuit, its step comprises, on semiconductor silicon base material, define at least one first depressed area and at least one convex silicon island district, wherein this semiconductor silicon base material surface is exposed in this bottom, first depressed area, and this convex silicon island district comprises a silicon layer and oxide layer, wherein this silicon layer is the top layer, this oxide layer is followed between this semiconductor silicon base material at this silicon layer, form at least one first metal-oxide semiconductor element on this depressed area, form at least one second metal-oxide semiconductor element in this convex silicon island district, comprehensive formation one first sedimentary deposit, implement a planarisation step in this first sedimentary deposit, define one second depressed area in this top, first depressed area in this first Shen lamination, form at least one capacitance structure in this second depressed area, and this capacitance structure is connected in this semiconductor silicon base material surface according to mat one first contact hole, comprehensive formation one second sedimentary deposit, define one second contact hole in this top, convex silicon island district, wherein this surface, district, convex silicon island is exposed in this bottom, second contact hole, and the wide open mouth of this second contact is positioned at this second sedimentary deposit surface.
Further, this oxide layer is a silicon dioxide layer; This first sedimentary deposit be silicon dioxide, silicon nitride and silicon oxynitride one of them; This second sedimentary deposit be silicon dioxide, silicon nitride and silicon oxynitride one of them; This planarisation step is the chemical-mechanical polishing method; This first contact hole contacts the hole with second be the filled conductive metal material; The transistor that this first metal-oxide semiconductor element is a P type metal-oxide semiconductor or the transistor of N type metal-oxide semiconductor one of them; The transistor that this second metal-oxide semiconductor element is a P type metal-oxide semiconductor or the transistor of N type metal-oxide semiconductor one of them.
For achieving the above object, purpose of the present invention also proposes the other one three dimensions component structure that is applied to embedded memory logic circuit, include, semiconductor silicon base material, on this semiconductor silicon base material, define at least one first depressed area and at least one convex silicon island district, wherein this semiconductor silicon base material surface is exposed in this bottom, first depressed area, and this convex silicon island district comprises a silicon layer and oxide layer, wherein this silicon layer is the top layer, and this oxide layer is followed between this semiconductor silicon base material at this silicon layer; One memory areas is arranged on this depressed area, comprise at least one first metal-oxide semiconductor element on this depressed area, and at least one capacitance structure contacts the hole with at least one first; One logic circuit area is arranged in this convex silicon island district, comprises that at least one second metal-oxide semiconductor element contacts the hole in this convex silicon island district with at least one second.
Further, this oxide layer is a silicon dioxide layer; The first metal-oxide semiconductor element be the transistor of P type metal-oxide semiconductor or N type metal-oxide semiconductor transistor one of them; The second metal-oxide semiconductor element be the transistor of P type metal-oxide semiconductor or N type metal-oxide semiconductor transistor one of them; This first contact hole contacts hole filled conductive metal material with second.
Advantage of the present invention is: because memory and logical circuit are respectively formed at depressed area and convex region, therefore, in embedded semiconductor storage, reduce the difference in height between two zones (memory and logic element), reduced the depth-to-width ratio of connector contact hole.
For above-mentioned purpose of the present invention, feature and advantage can be become apparent, a preferred embodiment cited below particularly, and cooperation institute accompanying drawing are described in detail below:
Description of drawings
Fig. 1 to Fig. 5 is the flow process generalized section that the embodiment of the invention forms the three dimensions element that is applied to embedded memory logic circuit.
Fig. 6 is the overall structure schematic diagram that the embodiment of the invention forms the three dimensions element that is applied to embedded memory logic circuit.
Embodiment
The present invention discloses a kind of manufacture method that is applied to the three dimensions element of embedded memory logic circuit, its step comprises, as shown in Figure 1, on semiconductor silicon base material 10, define at least one first depressed area 12 and at least one convex silicon island district 14, wherein this semiconductor silicon base material 10 surfaces are exposed in these 12 bottoms, first depressed area, and this convex silicon island district 14 comprises a silicon layer 16 and oxide layer 18, wherein this silicon layer 16 is the top layer, this oxide layer 18 is followed between this semiconductor silicon base material 10 at this silicon layer 16, wherein this oxide layer 18 is a silicon dioxide layer, is used as isolated insulation.
As shown in Figure 2, form at least one first metal-oxide semiconductor element 20 on this depressed area 12, wherein the transistor of this first metal-oxide semiconductor element 20 transistor that is P type metal-oxide semiconductor or N type metal-oxide semiconductor one of them.It is last 14 in this convex silicon island district to form at least one second metal-oxide semiconductor element 22, wherein the transistor of this second metal-oxide semiconductor element 22 transistor that is P type metal-oxide semiconductor or N type metal-oxide semiconductor one of them.
As shown in Figure 3, comprehensive formation one first sedimentary deposit 24, implement a planarisation step subsequently in this first sedimentary deposit 24, wherein this first sedimentary deposit 24 be silicon dioxide, silicon nitride and silicon oxynitride one of them, and this planarisation step is the chemical-mechanical polishing method.
As shown in Figure 4, define one second depressed area 26 in these 12 tops, first depressed area (this first depressed area 12 is filled up by this first sedimentary deposit 24, so be not shown among this figure) in this first sedimentary deposit 24 in this figure.
As shown in Figure 5, (this first depressed area 12 is filled up by this first sedimentary deposit 24 in Fig. 4 in this second depressed area 26 to form at least one capacitance structure 28, so be not shown among this figure), and this capacitance structure 28 is according to helping one first contact hole 30 to be connected in this semiconductor silicon base material 10 surfaces, comprehensive formation one second sedimentary deposit 32, define one second contact hole 34 in these 14 tops, convex silicon island district, wherein this silicon layer 16 on these 14 surfaces, convex silicon island district is exposed in these second contact, 34 bottoms, hole, and these second contact hole 34 openings are positioned at the surface of this second sedimentary deposit 32, and wherein contact hole 34 with second be the filled conductive metal material in this first contact hole 30.
According to above-mentioned manufacture method, the three dimensions element that is applied to embedded memory logic circuit of making and getting, its primary structure as shown in Figure 6, include, semiconductor silicon base material 10, on this semiconductor silicon base material 10, define at least one first depressed area 12 and at least one convex silicon island district 14, wherein this semiconductor silicon base material 10 surfaces are exposed in these 12 bottoms, first depressed area, and this convex silicon island district 14 comprises a silicon layer 16 and oxide layer 18, wherein this silicon layer 16 is the top layer, with between this semiconductor silicon base material 10, wherein this oxide layer 18 is a silicon dioxide layer to this oxide layer 18, is used as isolated insulation at this silicon layer 16.
One memory areas 36, be arranged on this depressed area 12, comprise that at least one first metal-oxide semiconductor element 20 is on this depressed area 12, and at least one capacitance structure 28 contacts hole 30 with at least one first, wherein the transistor of this first metal-oxide semiconductor element 20 transistor that is P type metal-oxide semiconductor or N type metal-oxide semiconductor one of them.
One logic circuit area 38, be arranged in this convex silicon island district 14, comprise that at least one second metal-oxide semiconductor element 22 contacts hole 34 in this convex silicon island district 14 with at least one second, wherein the transistor of this second metal-oxide semiconductor element 22 transistor that is P type metal-oxide semiconductor or N type metal-oxide semiconductor one of them.
Utilize the formed three dimensions element that is applied to embedded memory logic circuit of method of the present invention, wherein, can increase the transistorized performance of logic circuit area because logic circuit area is to be arranged in the district of convex silicon island with SOI (Silicon On Insulator) technology.And utilize method of the present invention can solve memory areas and logic circuit area because of on the manufacture craft flow process with the structural different problems that produce the height fall value, the depth-to-width ratio (aspect ratio) of reduction connector contact hole.
Though the present invention with preferred embodiment openly as above; but it is not to be used for limiting scope of the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention should be looked being as the criterion that the claim scope of present patent application defined.
Claims (13)
1. manufacture method that is applied in the three dimensions element of embedded memory logic circuit, its step comprises:
On semiconductor silicon base material, define one first depressed area and convex silicon island district, wherein this semiconductor silicon base material surface is exposed in this bottom, first depressed area, and this convex silicon island district comprises a silicon layer and oxide layer, wherein this silicon layer is the top layer, and follow between this semiconductor silicon base material at this silicon layer this oxide layer position;
Form one first metal-oxide semiconductor element on this depressed area;
Form one second metal-oxide semiconductor element in this convex silicon island district;
Comprehensive formation one first sedimentary deposit;
Implement a planarisation step at this first sedimentary deposit;
Define one second depressed area above this first depressed area at this first sedimentary deposit;
Form a capacitance structure in this second depressed area, and this capacitance structure is connected this semiconductor silicon base material surface according to mat one first contact hole;
Comprehensive formation one second sedimentary deposit;
Define one second contact hole above this convex silicon island district, wherein this surface, district, convex silicon island is exposed in this bottom, second contact hole, and this wide open mouthful of position of second contact is on this second sedimentary deposit surface.
2. the manufacture method that is applied in the three dimensions element of embedded memory logic circuit as claimed in claim 1 is characterized in that described oxide layer is a silicon dioxide layer.
3. the manufacture method that is applied in the three dimensions element of embedded memory logic circuit as claimed in claim 1 is characterized in that, described first sedimentary deposit be silicon dioxide, silicon nitride and silicon oxynitride one of them.
4. the manufacture method that is applied in the three dimensions element of embedded memory logic circuit as claimed in claim 1 is characterized in that, described second sedimentary deposit be silicon dioxide, silicon nitride and silicon oxynitride one of them.
5. the manufacture method that is applied in the three dimensions element of embedded memory logic circuit as claimed in claim 1 is characterized in that described planarisation step is the chemical-mechanical polishing method.
6. the manufacture method that is applied in the three dimensions element of embedded memory logic circuit as claimed in claim 1 is characterized in that, the described first contact hole contacts the hole with second be the filled conductive metal material.
7. the manufacture method that is applied in the three dimensions element of embedded memory logic circuit as claimed in claim 1, it is characterized in that the transistor that the described first metal-oxide semiconductor element is a P type metal-oxide semiconductor or the transistor of N type metal-oxide semiconductor.
8. the manufacture method that is applied in the three dimensions element of embedded memory logic circuit as claimed in claim 1, it is characterized in that the transistor that the described second metal-oxide semiconductor element is a P type metal-oxide semiconductor or the transistor of N type metal-oxide semiconductor.
9. three dimensions component structure that is applied in embedded memory logic circuit comprises: semiconductor silicon base material, and a memory areas, a logic circuit area is characterized in that,
On this semiconductor silicon base material, define one first depressed area and convex silicon island district, wherein this semiconductor silicon base material surface is exposed in this bottom, first depressed area, and this convex silicon island district comprises a silicon layer and oxide layer, wherein this silicon layer is the top layer, and follow between this semiconductor silicon base material at this silicon layer this oxide layer position;
This memory areas is arranged on this depressed area, comprises one first metal-oxide semiconductor element on this depressed area, and a capacitance structure contacts the hole with one first;
This logic circuit area is arranged in this convex silicon island district, comprises that one second metal-oxide semiconductor element contacts the hole in this convex silicon island district with one second.
10. the three dimensions component structure that is applied in embedded memory logic circuit as claimed in claim 9 is characterized in that described oxide layer is a silicon dioxide layer.
11. the three dimensions component structure that is applied in embedded memory logic circuit as claimed in claim 9, it is characterized in that the transistor that the described first metal-oxide semiconductor element is a P type metal-oxide semiconductor or the transistor of N type metal-oxide semiconductor.
12. the three dimensions component structure that is applied in embedded memory logic circuit as claimed in claim 9, it is characterized in that the transistor that the described second metal-oxide semiconductor element is a P type metal-oxide semiconductor or the transistor of N type metal-oxide semiconductor.
13. the three dimensions component structure that is applied in embedded memory logic circuit as claimed in claim 9 is characterized in that, the described first contact hole contacts hole filled conductive metal material with second.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105011 CN1209810C (en) | 2002-02-10 | 2002-02-10 | 3-D space element structure for internal-inlaid storage logical circuitand making method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 02105011 CN1209810C (en) | 2002-02-10 | 2002-02-10 | 3-D space element structure for internal-inlaid storage logical circuitand making method thereof |
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| Publication Number | Publication Date |
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| CN1438695A CN1438695A (en) | 2003-08-27 |
| CN1209810C true CN1209810C (en) | 2005-07-06 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN 02105011 Expired - Lifetime CN1209810C (en) | 2002-02-10 | 2002-02-10 | 3-D space element structure for internal-inlaid storage logical circuitand making method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR100702016B1 (en) * | 2005-02-02 | 2007-03-30 | 삼성전자주식회사 | Printed Circuit Board of Dual In-line Memory Module and Dual In-line Memory Module using the same |
| US7544992B2 (en) | 2007-05-16 | 2009-06-09 | United Microelectronics Corp. | Illuminating efficiency-increasable and light-erasable embedded memory structure |
| CN101315934B (en) * | 2007-05-31 | 2012-06-27 | 联华电子股份有限公司 | Embedded optical erasing memory capable of improving illumination efficiency and manufacturing method thereof |
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