CN1209228A - Voltage controlled crystal oscillator and loop filter - Google Patents

Voltage controlled crystal oscillator and loop filter Download PDF

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Publication number
CN1209228A
CN1209228A CN96180017A CN96180017A CN1209228A CN 1209228 A CN1209228 A CN 1209228A CN 96180017 A CN96180017 A CN 96180017A CN 96180017 A CN96180017 A CN 96180017A CN 1209228 A CN1209228 A CN 1209228A
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China
Prior art keywords
signal
coupled
frequency
duty cycle
controlled oscillator
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R·A·皮特施
P·K·瓦格纳
J·S·斯图尔特
K·拉马斯瓦迈
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Technicolor USA Inc
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Thomson Consumer Electronics Inc
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Priority claimed from GBGB9600002.1A external-priority patent/GB9600002D0/en
Priority claimed from GBGB9613608.0A external-priority patent/GB9613608D0/en
Application filed by Thomson Consumer Electronics Inc filed Critical Thomson Consumer Electronics Inc
Publication of CN1209228A publication Critical patent/CN1209228A/en
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K3/00—Circuits for generating electric pulses; Monostable, bistable or multistable circuits
    • H03K3/01—Details
    • H03K3/017—Adjustment of width or dutycycle of pulses
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K19/00—Record carriers for use with machines and with at least a part designed to carry digital markings
    • G06K19/06—Record carriers for use with machines and with at least a part designed to carry digital markings characterised by the kind of the digital marking, e.g. shape, nature, code
    • G06K19/067—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components
    • G06K19/07—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips
    • G06K19/0701—Record carriers with conductive marks, printed circuits or semiconductor circuit elements, e.g. credit or identity cards also with resonating or responding marks without active components with integrated circuit chips at least one of the integrated circuit chips comprising an arrangement for power management
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06K—GRAPHICAL DATA READING; PRESENTATION OF DATA; RECORD CARRIERS; HANDLING RECORD CARRIERS
    • G06K7/00—Methods or arrangements for sensing record carriers, e.g. for reading patterns
    • G06K7/0013—Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers
    • G06K7/0086—Methods or arrangements for sensing record carriers, e.g. for reading patterns by galvanic contacts, e.g. card connectors for ISO-7816 compliant smart cards or memory cards, e.g. SD card readers the connector comprising a circuit for steering the operations of the card connector
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03B—GENERATION OF OSCILLATIONS, DIRECTLY OR BY FREQUENCY-CHANGING, BY CIRCUITS EMPLOYING ACTIVE ELEMENTS WHICH OPERATE IN A NON-SWITCHING MANNER; GENERATION OF NOISE BY SUCH CIRCUITS
    • H03B5/00—Generation of oscillations using amplifier with regenerative feedback from output to input
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03J—TUNING RESONANT CIRCUITS; SELECTING RESONANT CIRCUITS
    • H03J9/00—Remote-control of tuned circuits; Combined remote-control of tuning and other functions, e.g. brightness, amplification
    • H03J9/06—Remote-control of tuned circuits; Combined remote-control of tuning and other functions, e.g. brightness, amplification using electromagnetic waves other than radio waves, e.g. light
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
    • H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
    • H03K17/78—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled
    • H03K17/795—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling bipolar transistors
    • H03K17/7955—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used using opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled controlling bipolar transistors using phototransistors
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/08—Details of the phase-locked loop
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/738—Interface circuits for coupling substations to external telephone lines
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/738—Interface circuits for coupling substations to external telephone lines
    • H04M1/74—Interface circuits for coupling substations to external telephone lines with means for reducing interference; with means for reducing effects due to line faults
    • H04M1/745—Protection devices or circuits for voltages surges on the line
    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04M—TELEPHONIC COMMUNICATION
    • H04M1/00—Substation equipment, e.g. for use by subscribers
    • H04M1/82—Line monitoring circuits for call progress or status discrimination

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Signal Processing (AREA)
  • General Physics & Mathematics (AREA)
  • Theoretical Computer Science (AREA)
  • Electromagnetism (AREA)
  • Artificial Intelligence (AREA)
  • Computer Vision & Pattern Recognition (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

A controllable crystal oscillator, producing a clock signal at a desired frequency, includes a voltage controlled crystal oscillator (110) producing a signal at a subharmonic of the desired frequency. The voltage controlled crystal oscillator is coupled to a first duty cycle corrector (120), which produces a signal having substantially a desired duty cycle. The first duty cycle corrector is coupled to a frequency multiplier (130), which produces a signal at substantially the desired frequency. The frequency multiplier, in turn, is coupled to a second duty cycle corrector (140). The second duty cycle corrector produces the clock signal at the desired frequency and having the desired duty cycle.

Description

VCXO and loop filter
The application relates to VCXO (VCXO) and the loop filter that is used to produce suitable high-frequency dagital clock signal.
In current high-speed modem applications, for example in digital broadcasting satellite system, its duty ratio that needs about 40MHz remains essentially in 50% controlled clock signal.Fundamental mode crystal in this frequency range does not have enough capture ranges that the appropriate signal locking ability is provided and the crystal parameter in changing is compensated.Like this, the VCXO of prior art uses third overtone crystal always.But the suitable VCXO operating characteristic that need not effectively regulate use three overtone crystals that just can not obtain in this frequency range.
Another kind method uses the suitable subharmonic of desirable clock frequency as first-harmonic always, and uses frequency doubling technology to come clocking.This frequency multiplier is phase-locked loop (PLL) normally., PLL introduces phase jitter in clock signal, and the problem of locking can be arranged in frequency scanning for example operating period.
In addition, the output signal from typical integrated circuit (IC) oscillator does not have 50% duty ratio.And the forward position of the clock signal that is produced by this oscillator and back be along being oblique, and this is owing to cause as the rising of the IC door of oscillator amplifier and the change of fall time.
For at speeder, for example application in the digital satellite system high speed modem wishes to have a kind of so simple controllable crystal oscillator, and it has quite high frequency range, stable duty ratio is arranged and quite low phase jitter is arranged.
According to principle of the present invention, a kind of controllable crystal oscillator with desirable frequency clocking comprises VCXO, and it produces the rd harmonic signal of desirable frequency.This VCXO is coupled to first duty cycle corrector, and it is the signal of desirable duty ratio basically that latter's generation has.First duty cycle corrector is coupled to frequency multiplier, and it is the signal of desirable frequency basically that the latter produces.And then, frequency multiplier is coupled to second duty cycle corrector.Second duty cycle corrector produces the clock signal with desirable duty ratio with desirable frequency.
In the accompanying drawings:
Fig. 1 is the block diagram of a part that comprises the high speed modem of digital satellite system of the present invention;
Fig. 2 is the more detailed block diagram according to controlled xtal osc of the present invention;
Fig. 3 is the more detailed block diagram according to loop filter of the present invention; With
Fig. 4 is the schematic diagram of controlled oscillator illustrated in fig. 2.
Fig. 1 is the block diagram that comprises the part of digital satellite system high speed modem of the present invention.Only represented that in the accompanying drawings those are necessary and useful element understanding the present invention.The professional and technical personnel will understand needs other what element in this system, know how to design and realize these other elements and how element illustrated in these other elements and the accompanying drawing is coupled together.
In the ground station of digital satellite system, data-signal (for example, representing the data-signal of TV programme) is become symbol sebolic addressing in known manner.Represent the signal of this symbol sebolic addressing to be modulated onto on the carrier wave, and be sent to satellite, the latter is broadcast to ground receiver to the symbol sebolic addressing after modulating.These receivers demodulation are in known manner represented the signal of this symbol sebolic addressing, recover to become symbol sebolic addressing, data reconstruction signal.The section processes that receiver carried out is to recover symbol regularly, so that can extract symbol exactly.Though the symbol that is sent out is regularly normally stable, but (for example representing different data-signals, from different satellites or ground station) symbol sebolic addressing between can have slightly timing difference, perhaps because propagation effect or component parameters variation, perhaps because exchange (switching) transponder in the satellite, regularly have moving a little.Like this, being used in receiver recovers symbol clock regularly and must stablize, and controlled, so that the slight variations of compensation symbol in regularly.
Among Fig. 1, input is coupled to the sampled signal source (not shown) of the received signals of conventional letter sequence.The sampled data input is coupled to the first input end of symbol timing recovery circuit 300.Second input of symbol timing recovery circuit 300 is coupled to the output of controlled oscillator 100, and this controlled oscillator provides and recovers the required timing clock signal of symbol sebolic addressing.
First output of symbol timing recovery circuit 300 produces the signal of representing this symbol sebolic addressing.The symbol data output is coupled to further application circuit (not shown), and the latter handles the symbol sebolic addressing that is resumed in known manner and restores the data that are sent out, and moves (pictures and sounds that for example, produces TV programme) based on these data.Symbol timing recovery circuit 300 produces signal of timing error e with the form (below will describe in more detail) of binary rate multiplier (BRM) signal, and second output of symbol timing recovery circuit 300 is coupled to the input of BRM filter 200.The output of BRM filter 200 is coupled to the control input end of controlled oscillator 100.
In the work, symbol timing recovery circuit 300 recovers the symbol sebolic addressing that is sent out in known manner according to the timing of the clock signal of being sent here by controlled oscillator 100 from the sample value of sending here.As mentioned above, in current digital satellite system, the nominal frequency of clock signal is 40MHz.In addition, in order correctly to recover symbol sebolic addressing, this clock signal must have roughly 50% duty ratio.Because the timing of the symbol sebolic addressing that is sent out is a quite stable, so the clock signal of controlled oscillator 100 is based on crystal oscillator.
Symbol timing recovery circuit 300 is also analyzed the sample value that is received, and produces error signal e, the symbol sebolic addressing that latter's representative is sent out and from the timing error between the present clock signal of controlled oscillator 100.In the illustrated embodiment of symbol timing recovery circuit 300, error signal e has the binary rate multiplier signal form, and this signal is the pulse train that its averaging analog value equals the timing error value.Signal of timing error e is in known manner by 200 filtering of BRM filter, and filtered error signal is used to control the output frequency of controlled oscillator 100 in known manner, is zero in the hope of making this error signal.
Fig. 2 is the more detailed block diagram according to controlled xtal osc of the present invention.Among Fig. 2, be coupled to the control input end of VCXO (VCXO) 110 from the control signal of (Fig. 1's) BRM filter 200.The output of VCXO 110 is coupled to the input of first duty cycle corrector 120.The output of first duty cycle corrector 120 is coupled to the input of frequency multiplier circuit 130.The output of frequency multiplier circuit 130 is coupled to the input of second duty cycle corrector 140.The output clocking of second duty cycle corrector 140, and be coupled to the clock signal input terminal of (Fig. 1's) symbol timing recovery circuit 300.
During work, VCXO 110 is operated on the 20MHz, and this frequency is half of desirable frequency 40MHz.In most preferred embodiment, VCXO 110 is manufactured into the IC oscillator., as mentioned above, the IC oscillator can not provide the clock signal of stable 50% duty ratio.If a such signal by two frequencys multiplication, just can not produce phase place and duty ratio stable clock signal.First duty cycle corrector 120 is used for proofreading and correct the variation of duty ratio, and produces that to have be the clock signal of 50% duty ratio basically.This signal can be minimum phase jitter by frequency multiplication.Frequency multiplier circuit 130 produces the clock signal of 40MHz in known manner.Second duty cycle corrector 140 is proofreaied and correct any phase jitter that is caused by the frequency multiplication operation, and produces minimum phase jitter and the clock signal of the 40MHz of 50% duty ratio are roughly arranged.
Fig. 3 is the more detailed block diagram according to loop filter of the present invention.Among Fig. 3, those are represented with identical label with element components identical illustrated in fig. 1, and will be not described in detail below.Among Fig. 3, BRM filter 200 comprises discrete low pass filter (LPF) 210 and the DC amplifier 220 that is connected in series, and they are connected between the control input end of the error in label signal output part of symbol timing recovery circuit 300 and controlled oscillator 100.
As mentioned above, the circuit (not shown) in the symbol timing recovery circuit 300 extracts symbol sebolic addressing in known manner from the sample value of delivering to its input, and produces those symbols at its output in known manner.In addition, symbol timing recovery circuit 300 produces binary rate multiplier (BRM) output signal, and the latter's simulation mean value is represented error signal e.For this purpose, symbol timing recovery circuit comprises symbol timing recovery (STR) error estimator 310, STR loop filter 320 and the BRM signal generator 330 that is connected in series.These elements are realized with Digital Logical Circuits, and are worked in known manner.
Must be filtered from the BRM error signal e of BRM signal generator 330, to eliminate BRM pulse frequency component, only stay the error signal component, i.e. the mean value of BRM pulse signal.Need a low pass filter to realize this function.In the circuit of prior art, the low-cost operational amplifier that is configured to active low-pass filter has been used to carry out low-pass filtering., have been found that active low-pass filter can send to some part in the input signal its output signal, thereby make output signal distortion, promptly a kind of state that is called feedthrough.In order to overcome this problem, have been found that the discrete low pass filter before the amplifier that is made of passive element, be arranged on dc voltage conversion/amplification has been eliminated this problem.
During work, discrete LPE 210 constitutes (following will the description in more detail) by the RC low-pass filter stage of a RC low pass filter or a plurality of cascades.This network provides the low-frequency filter characteristics identical with active filter, but does not have feedthrough.Handled by DC amplifier 220 from the output signal of discrete LPE 210, and generation is to the control signal of controlled oscillator 100.DC amplifier 220 provides voltage level to move (shifting) in known manner and error signal is amplified, and the latter is that the appropriate control signals of generation controlled oscillator 100 is required.
Fig. 4 is the schematic diagram of symbol timing recovery loop illustrated in fig. 3.Among Fig. 4, first electrode of crystal X1 is coupled to the input of integrated circuit (IC) door 10, and first electrode separately of first resistance R 1 and first capacitor C 1.Second electrode of crystal X1 is coupled to first electrode separately of second resistance R 2 and second capacitor C 2.The output of the one IC door 10 is coupled to second electrode separately of first resistance R 1 and second resistance R 2 and first electrode of the 3rd resistance R 3.Second electrode of first capacitor C 2 is coupled to first electrode of the first variable capacitance diode V1.Second electrode of second capacitor C 2 is coupled to first electrode of the second variable capacitance diode V2.Second electrode separately of the first variable capacitance diode V1 and the second variable capacitance diode V2 be coupled to reference potential () source point.
The combination of gate 10, crystal X1, first and second resistance R 1 and R2, first and second capacitor C 1 and C2 and the first and second variable capacitance diode V1 and V2 is the isolation Pierce oscillator of gate type, and constitutes (Fig. 2's) VCXO 110.Crystal X1 is the fundamental mode crystal that the 20MHz centre frequency is arranged.In most preferred embodiment, crystal X1 has the nominal load electric capacity of 8pf, and in the load capacitance scope from 5pf to 14pf, the scope of minimum ± 100/1000000ths (100ppm) is arranged.
Gate 10 is IC gates of standard, and in most preferred embodiment, and it is one that is manufactured in four exclusive-OR gates of (for example industrial standard 74AC86) in the single IC encapsulation.Door 30,50 and 60 (below will describe in more detail) illustrated in fig. 4 are that three exclusive-OR gates of the remainder in being encapsulated by this IC form.In such embodiments, have only an input receiving inputted signal in the exclusive-OR gate 10,50 and 60, and these second input separately all is coupled to the source (not shown) of logical one signal in known manner.
Resistance R 1 makes it enter active region for the input biasing of gate 10.Resistance R 2 limits crystal currents, and considers phase shift and frequency response decline (roll off) under the control of the second variable capacitance diode V2.Among Fig. 4, the capacitance range of the 6pf when the first and second variable capacitance diode V1 and V2 have the 25.5pf to 10.5 when 1 volt of dc voltage to lie prostrate dc voltage respectively.In most preferred embodiment, variable capacitance diode is made by Sony company, and Thomson ConsumerElectronic is arranged, Inc. Part No. 445-480.
Comprise that the 3rd capacitor C 3 that is connected in parallel of connecting with the 4th capacitor C 4 and first tuning circuit of first inductance L 1 are coupling between second electrode and ground of the 3rd resistance R 3.The 3rd resistance R 3 is isolated and current limliting for first tuning circuit provides.First tuning circuit is scheduled to have the roughly resonance frequency of 20MHz, the i.e. output frequency of VCXO 110.First tuning circuit has high impedance under resonance frequency, and under other frequency Low ESR is arranged.Like this, be bypassed to ground, only stay the output signal component of the VCXO 110 the resonance frequency of 20MHz of first tuning circuit near from all other frequency components of the clock signal of the output of VCXO 110.Therefore, the signal at the second electrode place of the 3rd resistance R 3 is the sine wave under VCXO 110 frequencies.
The 5th capacitor C 5 is connected to the input of second gate 30 from second electrode of the 3rd resistance R 3 and the tie point of first tuning circuit, and is connected to first electrode separately of the 4th resistance R 4 and the 5th resistance R 5.Second electrode of the 4th resistance R 4 is connected to the source of operating potential VCC, and second electrode of the 5th resistance R 5 is connected to ground.The output of second gate 30 is coupled to the input of gate 30 by the 6th resistance R 6.The combination of the 4th and the 5th resistance R 4 and R5 provides the discharge path of the 5th capacitor C 5 and to the thick DC biasing of the input of second gate, and the 6th resistance R 6 makes it enter active region for second gate, 30 biasings.The 5th capacitor C 5 exchanges the input that (AC) is coupled to second gate 30 to the sine wave of nominal 20MHz from first tuning circuit.
The gate of Lian Jieing plays the high-gain amplifier effect by this way.When the input that sine wave signal AC is coupled to gate, its normalizationization is to middle bias point.Therefore, sinusoidal wave input signal will produce the roughly clock signal of 50% duty ratio at the output of second gate 30.First tuning circuit (C3, L1, C4) with have its biasing element (R4, R5, second gate 30 R6) constitute (Fig. 1's) duty-cycle correction circuit 120.
The output of second gate 30 is coupled to the first input end of exclusive-OR gate 50, and the input of delay circuit 40.The output of delay circuit 40 is coupled to second input of exclusive-OR gate 50.For example, delay circuit 40 can be discrete low pass RC filter, and it has input and the resistance between the output and output that is connected it and the electric capacity between the ground that is connected it.The combination of exclusive-OR gate 50 and delay circuit 40 is created in a series of pulses of each transformation place of 20MHz input signal or a series of pulses of 40MHz frequency in known manner.Like this, it forms (Fig. 1's) frequency multiplier 130.
The output of exclusive-OR gate 50 also is coupled to first electrode of the 7th resistance R 7.Second tuning circuit that comprises the 7th capacitor C 7 of the 6th capacitor C 6 that is connected in parallel and second inductance L 2 and series connection with it is connected between second electrode and ground of the 7th resistance R 7.7 pairs second tuning circuits of the 7th resistance R provide isolates and current limliting.Second tuning circuit has resonance frequency twice or 40MHz of the frequency of VCXO 110.Second tuning circuit also has high impedance and under other frequency Low ESR is arranged at the resonance frequency place.Like this, other frequency is bypassed to ground, only stays in the second tuning circuit resonance frequency, i.e. near the output signal component of the exclusive-OR gate 50 the 40MHz.Signal at the tie point place of second electrode of the 7th resistance R 7 and second tuning circuit is the sine wave of the twice of VCXO 110 frequencies.
The 8th capacitor C 8 is connected to the input of the 3rd gate 60 from second electrode of the 7th resistance R 7 and the tie point of second tuning circuit, and is connected to first electrode separately of the 8th resistance R 8 and the 9th resistance R9.Second electrode of the 8th resistance R 8 is connected to the source of operating potential VCC, and second electrode of the 9th resistance R 9 is connected to ground.The output of the 3rd gate 60 is coupled to the input of the 3rd gate 60 by the tenth resistance R 10.With with second gate, 30 similar modes, the the 8th and the 9th resistance R 8 and R9 are respectively that the 8th capacitor C 8 provides discharge path and to the thick DC biasing of the input of the 3rd gate, and the tenth resistance R 10 makes it enter active region for the 3rd gate 60 biasings.The 8th capacitor C 8 is coupled to the sine wave signal of nominal 40Mhz the input of the 3rd gate 60 from second tuning circuit.Because AC is coupled to the sine wave normalization of input) to middle bias point, so, the 3rd gate produce have twice VCXO 110 frequencies, the clock signal of 50% duty ratio roughly.Second tuning circuit (C6, L2, C7) with have its biasing element (R8, R9, the 3rd gate 60 R10) constitute (Fig. 1's) duty-cycle correction circuit 140.
The output of the 3rd gate 60 is coupled to first electrode of the 11 resistance R 11.Second electrode of the 11 resistance R 11 produces has controlled clock signal roughly 50% duty ratio, desirable 40MHz, and is coupled to first electrode of the 9th capacitor C 9 and the input of (Fig. 1's) symbol timing recovery (STR) circuit 300.The RC network that the 11 resistance R 11 and the 9th capacitor C 9 are formed for making the frequency response of the high order harmonic component composition of the clock signal that is produced by the 3rd gate 60 to descend.
The output of symbol timing recovery (STR) circuit 300 is coupled to first electrode of the 12 resistance R 12.Second electrode of the 12 resistance R 12 is coupled to first electrode separately of the tenth capacitor C 10 and the 13 resistance R 13.Second electrode of the 13 resistance R 13 is coupled to first electrode separately of the 11 capacitor C 11 and the 14 resistance R 14.Second electrode of the 14 resistance R 14 is coupled to first electrode separately of the 12 capacitor C 12 and the 15 resistance R 15.Second electrode of the 15 resistance R 15 is coupled to first electrode separately of the 13 capacitor C 13 and the 16 resistance R 16.Second electrode of the 16 resistance R 16 is coupled to the input of DC amplifier 220.
As mentioned above, the symbol that symbol timing recovery circuit 300 has used the clock of the 40MHz that is produced by controlled oscillator 100 to recover to be sent out, and the generation error signal e, the representative of this error signal is from the error between the clock signal of controlled oscillator 100 and the symbol timing that received.In most preferred embodiment, this error signal has the form of binary rate multiplier (BRM) signal, and its mean value is the value of error.This BRM signal comes filtering with discrete filters 210, so that extract mean value.The 12 resistance R 12 and the tenth capacitor C 10 form the first low pass RC filter stage; The 13 resistance R 13 and the 11 capacitor C 11 form the second low pass RC filter stage; The 14 resistance R 14 and the 12 capacitor C 12 form the 3rd low pass RC filter stage; And the 15 resistance R 15 and the 13 capacitor C 13 form the 4th low pass RC filter stage.First, second, third, fourth low-pass filter stage combines the discrete low pass filter of formation (Fig. 3's) (LPF) 210.Discrete low pass filter 210 produces the signal of representative from the mean value of the BRM error signal e of symbol timing recovery circuit 300.
Discrete low pass filter 210 is coupled to the input of DC amplifier 220 by the 16 resistance R 16.The output of DC amplifier 220 is coupled to first electrode of the 14 capacitor C 14, and first electrode separately that is coupled to the first variable capacitance diode V1 and the second variable capacitance diode V2 by the 17 resistance R 17 and the 18 resistance R 18.Second electrode grounding of the 14 capacitor C 14.DC amplifier 220 produces the DC control signal that is used for controlling respectively the first and second variable capacitance diode V1 and V2.The the 17 and the 18 resistance R 17 and R18 play a part DC amplifier 220 respectively with the first and second variable capacitance diode V1 and V2 in each keep apart, and the first and second transfiguration second tube sheet V1 and V2 are isolated from each other.The 14 capacitor C 14 provides additional filter action for the variable capacitance diode control signal.
Following table I is given in the optimum value of the illustrated element of Fig. 4.
Though with the formal specification in digital satellite system, implemented the present invention, but the professional and technical personnel understands: can be used in any place that needs the controlled xtal osc of suitable high-frequency and the strict duty ratio of controlling according to controlled oscillator of the present invention.
Table I component value
Element Value Q
????R1 ????100k
????R2 ????1k
????R3 ????1k
????R4 ????1k
????R5 ????1k
????R6 ????100k
????R7 ????1k
????R8 ????1k
????R9 ????1k
????R10 ????100k
????R11 ????100
????R12 ????1k
????R13 ????1k
????R14 ????1k
????R15 ????1k
????R16 ????100k
????R17 ????270k
????R18 ????270k
Element Value f.
????C1 ?270p
????C2 ?270p
????C3 ?100p
????C4 ??.1u
????C5 ??27p
????C6 ??10p
????C7 ??.1u
????C8 ??27p
????C9 ??27p
????C10 ??.033u
????C11 ??.033u
????C12 ??.033u
????C13 ??.033u
????C14 ???470p
Element Value h.
????L1 ??.60u
????L2 ??.60u

Claims (15)

1. controllable crystal oscillator that is used for desirable frequency clocking is characterized in that comprising:
VCXO, it produces oscillator signal with the subfrequency of desirable frequency;
First duty cycle corrector, it is coupled to described VCXO;
Frequency multiplier, it is coupled to described first duty cycle corrector, is used for producing oscillator signal with desirable frequency; And
Second duty cycle corrector, it is coupled to described frequency multiplier, is used for desirable frequency clocking.
2. the controlled oscillator of claim 1 is characterized in that described VCXO comprises the Pierce oscillator of isolation.
3. the controlled oscillator of claim 2 is characterized in that described VCXO comprises the Pierce oscillator of the isolation of gate.
4. the controlled oscillator of claim 2 is characterized in that described VCXO comprises the basic mode crystal.
5. the controlled oscillator of claim 2 is characterized in that described desirable frequency is 40MHz roughly, and the subharmonic of described desirable frequency is 20MHz roughly.
6. the controlled oscillator of claim 1 is characterized in that described first duty cycle corrector is roughly 50% to duty cycle correction, and comprises:
Tuning circuit, it has the resonance frequency of the subharmonic that roughly is desirable frequency, and it is coupled to described VCXO;
High-gain amplifier, its input are biased to its middle bias point, and its output generation is used for proofreading and correct the oscillator signal of duty ratio; And
Be used for described tuning circuit AC is coupled to the circuit of the described input of described high-gain amplifier.
7. the controlled oscillator of claim 6 is characterized in that described high-gain amplifier comprises the gate that is entered active region by biasing.
8. the controlled oscillator of claim 6 is characterized in that:
The output of described voltage controlled oscillator is coupled to first duty cycle corrector; And
Described tuning circuit is connected between the source point of the output of described voltage controlled oscillator and reference potential, and, under its resonance frequency, present high impedance, and under disresonance frequence, present Low ESR.
9. the controlled oscillator of claim 1 is characterized in that described frequency multiplier comprises:
Exclusive-OR gate, it has the first input end and second input that is coupled to first duty cycle corrector, and produces oscillator signal with desirable frequency; And
Delay circuit, it is connected between described second input of described first duty cycle corrector and described exclusive-OR gate.
10. the controlled oscillator of claim 1 is characterized in that described second duty cycle corrector comprises:
Tuning circuit, it has is the resonance frequency of desirable frequency basically;
High-gain amplifier, its input are biased to the input of its middle bias point, and, its output clocking; And
Be used for described tuning circuit AC is coupled to the circuit of the described input of described high-gain amplifier.
11. the controlled oscillator of claim 10 is characterized in that carrying high-gain amplifier to comprise the gate that is entered active region by biasing.
12. the controlled oscillator of claim 10 is characterized in that:
The output of described frequency multiplier is coupled to second duty cycle corrector; And
Described tuning circuit is connected between the source point of the described output of described frequency multiplier and described reference potential, and presents high impedance under its resonance frequency, and presents Low ESR under disresonance frequence.
13. a signal processing system is characterized in that comprising:
Controlled oscillator is used for desirable frequency clocking, and it comprises:
VCXO, produces oscillator signal with the subharmonic of desirable frequency at its responsive control signal;
First duty cycle corrector, it is coupled to described VCXO;
Frequency multiplier, it is coupled to described first duty cycle corrector, is used for producing oscillator signal with desirable frequency;
Second duty cycle corrector, it is coupled to described frequency multiplier, is used for desirable frequency clocking;
Signal processing circuit, it responds, is used to handle input data signal and produce outputting data signals and the clock timing error signal described clock signal;
Discrete filters, it responds to described clock timing error signal;
Be connected between described discrete filters and the described voltage controlled oscillator, be used to produce control signal so that described clock timing error signal is reduced to minimum circuit.
14. the system of claim 13 is characterized in that:
Described signal processing circuit comprises the circuit that is used for producing with the form of binary rate multiplier signal the clock timing error signal;
Described discrete filters comprises discrete low pass filter; And
Described control signal generation circuit comprises the DC amplifier.
15. the system of claim 14 is characterized in that described discrete filters comprises the RC low pass filter.
CN96180017A 1995-12-22 1996-12-11 Voltage controlled crystal oscillator and loop filter Pending CN1209228A (en)

Applications Claiming Priority (8)

Application Number Priority Date Filing Date Title
US917895P 1995-12-22 1995-12-22
US60/009,178 1995-12-22
GB9600002.1 1996-01-02
GBGB9600002.1A GB9600002D0 (en) 1996-01-02 1996-01-02 Receiver for compressed television information
GBGB9613608.0A GB9613608D0 (en) 1996-06-28 1996-06-28 40mhz VCXO and loop filter for digital symbol lock timing for high speed modems
GB9613608.0 1996-06-28
US73455596A 1996-10-21 1996-10-21
US08/734,555 1996-10-21

Publications (1)

Publication Number Publication Date
CN1209228A true CN1209228A (en) 1999-02-24

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CN96180017A Pending CN1209228A (en) 1995-12-22 1996-12-11 Voltage controlled crystal oscillator and loop filter

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EP (1) EP0868782A1 (en)
JP (1) JP2000505962A (en)
KR (1) KR19990072222A (en)
CN (1) CN1209228A (en)
AU (1) AU1417497A (en)
BR (1) BR9612205A (en)
WO (1) WO1997023955A1 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102035508A (en) * 2010-05-28 2011-04-27 上海宏力半导体制造有限公司 Clock generation circuit

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20020027493A1 (en) * 2000-08-23 2002-03-07 Brian Morrison Remote signal transmission control including compensation for variations in transmitter components
KR100714586B1 (en) * 2005-08-03 2007-05-07 삼성전기주식회사 Voltage controlled oscillator with duty correction

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Publication number Priority date Publication date Assignee Title
FR2497427A1 (en) * 1980-12-29 1982-07-02 Chazenfus Henri CIRCUIT FOR ADJUSTING THE CYCLIC RATIO OF AN IMPULSE PERIODIC SIGNAL AND FREQUENCY MULTIPLIER DEVICE BY 2, INCLUDING THE ADJUSTING CIRCUIT
GB2196808B (en) * 1986-10-31 1990-12-05 Stc Plc Oscillation generation
DE3730773A1 (en) * 1987-09-12 1989-03-23 Philips Patentverwaltung Radio-frequency generator
KR940001862B1 (en) * 1991-03-21 1994-03-09 삼성전자 주식회사 Bias stable circuit of paging receiver
JPH04329710A (en) * 1991-04-30 1992-11-18 Nec Corp Two-multiple circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102035508A (en) * 2010-05-28 2011-04-27 上海宏力半导体制造有限公司 Clock generation circuit

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KR19990072222A (en) 1999-09-27
EP0868782A1 (en) 1998-10-07
BR9612205A (en) 1999-07-13
JP2000505962A (en) 2000-05-16
WO1997023955A1 (en) 1997-07-03
AU1417497A (en) 1997-07-17

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