CN1197547A - 光电二极管及其制造方法 - Google Patents
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Abstract
在一个SOI－基片中,一个有源区(6)完全由一个用绝缘材料填满的沟槽(4)所环绕。与此沟槽相邻设置一个第一掺杂区(8),它尤其通过由一个在沟槽(4)的槽壁所设置的掺杂层向外扩散而形成。该第一掺杂区(8)和一个第二掺杂区(12)形成一个光电二极管的pn－结。
Description
在不同的集成电路装置中，例如在光电耦合器和电子继电器中，光电二极管用作集成的能源和信号源。为此应用，光电二极管应该有高的开路电压、高的短路电流和最大功率输出。其中由光电二极管所提供的功率取决于在此光电二极管的内电阻。内电阻通过串联电阻形成，串联电阻是由光电二极管扩散区的薄层电阻、光电二极管金属化的接触电阻、金属化的线路电阻所组成。(见例如S.M.Sze“Physics ofSemiconductor Devices”，Wiley，NewYork，Kap.14.3.2)。
光电二极管，它作为分立元件被制造时，为减小串联电阻和提高光电效率，设置有背面接触和用于光反射的特殊几何结构，例如V-沟槽结构(见例如S.M.Sze“Physics of Semiconductor Device”，Wiley，New York，Kap.14.3.4)。
在基片上被集成制造的光电二极管，不可能设有背面接触或反射结构。在基片上被集成的光电二极管，在元件上侧附近有一个pn-结，通过它，在硅里借助光子产生的电子和空穴彼此相互被分开。p-和n-掺杂区，在此通过狭长的、高掺杂n-和p-掺杂带电学连接。高掺杂带有一个高的内电阻。通过一个金属化层，该层在高掺杂带在整个长度有接触，故而薄膜电阻被减小。同时光电二极管的光电敏面的一部分被覆盖，因此光电效率被减小。
本发明以这个问题为基础，即光电二极管，它在一个集成电路中是可制造的，并且有减小的串联电阻。此外应该给出用于制造它的方法。
这个问题依照发明通过根据权利要求1的光电二极管以及根据权利要求5的制造它的方法得以解决。发明的进一步改进由其余的权力要求给出。
依据发明的电光二极管在基片里被集成，并且通过介电绝缘与基片隔离。为此，基片具有一个载体薄片，一个在其上设置的绝缘层和一个在其上设置的单晶硅层。例如一种称为SOI的基片适合做基片，它包括在硅片上的一个绝缘层和其上的单晶硅层。在单晶硅层里设有一个沟槽，它从硅层的主面延伸到绝缘层。该沟槽用绝缘材料填充。该沟槽例如用SiO2填充，或者用SiO2做衬并用多晶硅填充。沟槽在硅层完整地环绕一个有源区。该有源区向下经绝缘层和载体薄片绝缘。
在有源区设置一个第一掺杂区，它直接和沟槽相邻。第一掺杂区从硅层的主面延伸至绝缘层。第一掺杂区由第一导电类型，例如p型，掺杂。第一掺杂区在和沟槽的交界面上，在进入深度例如3μm的情况下，有一个在1018cm-3和1020cm-3的范围里的掺杂物浓度。
此外，在有源区设有一个第二掺杂区，它由一个第二，和第一导电类型相反，例如n型进行掺杂。第二掺杂区和第一掺杂区形成一个pn-结，它形成光电二极管。
在硅层的主面上，第一掺杂区和第二掺杂区上分别设置接触区。考虑到一个尽可能低的连接电阻，优先在提高掺杂浓度的连接区设置这种接触区。
由于，第一掺杂区从主面延伸到绝缘层，故而对于光电二极管有效的pn-结的面积相对于光电二极管主面所需要的面积增大了。此外，由入射光子产生的载流子到最近的一个pn-结最大所需的扩散自由程被减小。最后第一掺杂区为载流子提供一个低欧姆的路径。除了到掺杂区域的接触区外，在主面上没有由金属接触或者金属布线所形成的覆盖层。也就是说实际上有源区整个表面供光入射使用。
首先沟槽用SiO2填充。由于SiO2比硅有较小的折射率，故而入射到沟槽内绝缘材料的光可以通过折射进入较高光密度的硅并且同样对载流子产生作贡献。硅/SiO2全反射的临界角为23°。因此这里很少产生由硅进入SiO2的折射。
光电二极管进一步的改进通过下面实现，即在有源区设置至少一个附加的沟槽，它从主面延伸至绝缘层，并且用绝缘材料填充。此外在有源区设置一个第三掺杂区，它由第一导电类型，例如p，进行掺杂，并且和附加沟槽直接相邻。第三掺杂区从硅层的主面延伸至绝缘层。第三掺杂区导致pn-结的面积进一步的变大。除此之外，按照这种方式，最大所需扩散路径可以进一步减小。附加沟槽的数目几乎可以随意选择。一个上限仅仅通过工艺，亦即例如通过沟槽宽度、第三掺杂区的扩散深度、光刻或者类似的工艺给出。
设计带有斜侧壁的沟槽是有利的，因为在这种情况下，此后来自SiO2沟槽的光折射进入硅的有源区得到进一步改善。
第一掺杂区和第三掺杂区优先通过由一个在沟槽内存在的掺杂源向外扩散而产生。为此在腐蚀沟槽后，制造一个掺杂层，它至少覆盖沟槽的侧壁。例如掺杂玻璃或者掺杂多晶硅或者非晶硅适合做这种掺杂层。第一掺杂区和第三掺杂区通过在一个热处理工艺中由掺杂层向外扩散而产生。
在使用一个掺杂硅层作为掺杂源时，在本发明所涉及的范围内，热处理工艺是如此进行的，即掺杂物向外扩散的同时，掺杂硅层进行氧化，在此过程中沟槽被SiO2填满。
借助于围绕沟槽和绝缘层，本发明的光电二极管完全与基片介电隔离。基片由此可以包括大量毗邻的光电二极管，它在电学上彼此完全独立。如果这些光电二极管以串联电路设置，则串联电路所提供的电压相当于各个光电二极管各自的电压的总和。由此，本发明的光电二极管适于，在有多个光电二极管的串联电路中提供控制一个高电压-MOSFET所必需的电压。根据本发明的光电二极管不出现到基片的漏电流问题。此外，绝缘所需要的位置是最小的，绝缘通过由绝缘材料填充的沟槽而实现。
接下来借助实施例和附图进一步阐述本发明。
图1显示在有源区有两个附加沟槽的光电二极管的俯视图。
图2显示在图1中用II-II标出的通过光电二极管的剖面。
一个SOI-基片包括一个硅片1，在它的上面设有一个绝缘层2和一个单晶硅层3(见图2)。绝缘层2由例如SiO2组成，并且有一个例如1μm的厚度。单晶硅3有一个例如20μm的厚度，并且是例如有掺杂物浓度为6×1014cm-3的n-掺杂。
在单晶硅层3设有一个沟槽4，它从单晶硅层的一个主面5延伸至绝缘层2(见图1和图2)。沟槽4完整地环绕着一个有源区6。沟槽4由绝缘材料例如SiO2填充。沟槽4有一个例如3μm的宽度。有源区6，它由沟槽4环绕，有一个规格例如200μm×200μm。
在有源区6设有两个附加沟槽7，它们分别由主面5延伸至绝缘层2。附加沟槽7是条形的，并且和沟槽4没有接通。附加沟槽7同样由绝缘材料例如SiO2填充。
在有源区6，设置一个第一掺杂区8与沟槽4相邻。第一掺杂区8为例如p+-掺杂，并且在到沟槽4的界面上有一个例如1019cm-2的掺杂物浓度。扩散深度为例如3μm。第一掺杂区8由主面5延伸至绝缘层2。第一掺杂区8在此和沟槽4直接相邻。第一掺杂区8环状地环绕着有源区6。
此外两个第三掺杂区9设置在有源区域6，它们分别和附加沟槽7中的一个相邻设置。各个第三掺杂区9在此分别环状环绕附加沟槽7。第三掺杂区9从主面5延伸至绝缘层6。第三掺杂区9为例如p+-掺杂，并且在到各个附加沟槽7界面上，有一个范围从1018cm-3到1020cm-3的掺杂物浓度。
此外在主面5上设有几个p-掺杂槽10，它们分别与沟槽4或者一个附加沟槽7相邻。p-掺杂槽10有一个范围在1016cm-3和1019cm-3之间的掺杂物浓度并且有一个例如2μm的深度。
在主面5上，设置一个n+-掺杂的连接区11，它完全由一个第二掺杂区12所环绕，它由基质材料n-掺杂的单晶硅层3形成。n+-掺杂连接区11包括多个条形单元，它们分别在附加沟槽7之间或者在附加沟槽7之一和沟槽4之间设置并且它们通过一个宽的、垂直于所设置的条形的连接单元相互连接。
此外在主面5上，设有p+-掺杂连接区13，它们分别在有源区6的边缘设置，并且它部分重叠一个第三掺杂区9和第一掺杂区8。p+-掺杂连接区13在第一掺杂区8和有关的第三掺杂区9之间建立一个导电连接。p+-掺杂连接区13有例如1019cm-3的掺杂物浓度。
n+掺杂连接区11和p+-掺杂连接区13分别有大约0.8μm的深度。
至少有源区6在主面5上设有钝化层14。钝化层14在厚度和材料方面要与被探测光波长进行调整，从而使它对此光是透明的。SiO2或Si3N4特别适合作钝化层。钝化层14有一个例如1μm的厚度。
在p+-掺杂连接区13的上面，在钝化层14上设置例如铝的接触15，它通过在钝化层上的接触孔和有关p+-掺杂连接区相连接。在n+-掺杂连接区11的条形连接单元的范围里，例如设置两个铝的接触16，它们分别通过接触孔和n+-掺杂连接区11相连。到p+-掺杂连接区的接触点15和到n+-掺杂连接区11的接触16优先为对称设置，因为这种设置对在光电二极管中的电流分布产生良好作用。
第二掺杂区12，它由基质材料单晶硅层3形成，和临界的第一掺杂区8、第三掺杂区9及p-掺杂槽10形成一个pn-结，它形成光电二极管。在第一掺杂区8和第三掺杂区9中的p+-掺杂，在此保证有一个良好的导电率。p掺杂槽10的p-掺杂保证在表面范围内的禁带宽度有微小改变，并且从而保证只微小改变硅的吸收特性。
为制造根据发明的光电二极管，在单晶硅层3里，通过光刻的工艺步骤形成一个掩膜后，沟槽4和附加沟槽7通过用例如HBr和He、O2各向异性腐蚀而形成。通过控制在各向异性腐蚀中的参量，可形成沟槽4、7的侧壁垂直或倾斜于主面。接下来淀积一个掺杂层例如硼硅玻璃或者p+-掺杂硅，它至少覆盖沟槽4、7的侧壁。在一个热处理工艺中例如1000℃，通过掺杂物由掺杂层向沟槽4和附加沟槽7的侧壁向外扩散，形成第一掺杂区8和第三掺杂区9。接下来沟槽4和附加沟槽7用绝缘材料填充。这在腐蚀步骤中去掉掺杂层后通过一个SiO2-层的沉积完成。在主面5的范围里所设置的SiO2层的部分，通过平面化的腐蚀工艺被除去。
假如掺杂层由掺杂硅组成，则热处理工艺可以如此进行，即在掺杂物向外扩散形成第一掺杂区8和第三掺杂区9时，掺杂层被全部氧化，并且以这种方式沟槽4和附加沟槽7用SiO2填满。
p-掺杂槽10、n+-掺杂连接区和p+-掺杂连接区13接下来通过掩蔽离子注入而形成。
在钝化层14淀积后，用公知的方法打开到n+-掺杂连接区11和p+-掺杂连接区13的接触孔。最后接触15、16通过淀积例如由铝组成的金属化层并且通过金属化层结构化来制造。
Claims (8)
1.光电二极管，
-其中，设置一个基片，它包括一个载体薄片(1)、一个在其上设置的绝缘层(2)和一个在其上设置的单晶硅层(3)，
-其中，在硅层(3)中至少设置一个沟槽(4)，它从硅层(3)的主面(5)延伸至绝缘层(2)，它由绝缘材料填充并且完全环绕有源区(6)，
-其中，在有源区(6)设置一个掺杂区(8)，它由一个第一导电类型掺杂，它和沟槽(4)直接相邻，并且从硅层(3)的主面(5)延伸至绝缘层(2)，
-其中，在有源区(6)设置一个第二掺杂区(3)，它由一个和第一导电类型相反的第二导电类型掺杂，并且它和第一掺杂区(8)形成一个pn-结，
-其中，在硅层(3)的主面(5)上，为第一掺杂区和第二掺杂区(12)各设置一个接触(15、16)。
2.根据权利要求1的光电二极管，
-其中，在有源区(6)设置至少一个由第一导电型掺杂的槽(10)，它毗邻主面(5)，并且它配备有一个接触(15)。
3.根据权利要求1或2的光电二极管，
-其中，在有源区(6)设置至少一个附加沟槽(7)，它从主面(5)延伸至绝缘层(2)并且用绝缘材料填充，
-其中，在有源区(6)设置一个第三掺杂区(9)，它被第一导电型掺杂，它和附加沟槽(7)直接相邻，并且它从硅层(3)的主面(5)延伸至绝缘层(2)。
4.根据权利要求1至3之一的光电二极管，
-其中，一个或几个沟槽(4，7)有斜的侧壁，故而在主面(5)的沟槽横截面比在沟槽底部大。
5.制造光电二极管的方法，
-其中，在一个基片里，它包括一个载传薄片(1)，一个在其上设置的绝缘层(2)和一个在其上设置的单晶硅层(3)，在硅层(3)上制造一个沟槽(4)，它从硅层的主面(5)延伸至绝缘层(2)并且完全环绕一个有源区(6)。
-其中，沟槽(4)的侧壁被掺杂，故而形成一个第一掺杂区(8)，它被一个第一掺杂类型所掺杂，它和沟槽直接相邻并且由硅层(3)的主面(5)延伸至绝缘层(2)，
-其中，沟槽(4)用绝缘材料填充，
-其中，在有源区(6)，形成一个第二掺杂区(12)，它由一个和第一相反的第二导电类型掺杂，并且和第一掺杂区(8)形成一个pn-结，
-其中，在硅层(3)的主面(5)上，各为第一掺杂区(8)和第二掺杂区(12)制造一个接触(15，16)。
6.根据权利要求5的方法，
-其中，为形成第一掺杂区(8)，制造一个掺杂层，它覆盖沟槽(4)的侧壁，
-其中，第一掺杂区(8)在一个热处理工艺中由掺杂层向外扩散而产生。
7.根据权利要求5或6的方法，
-其中，在有源区制造沟槽(4)时，至少形成一个附加沟槽(7)，
-其中，附加沟槽(7)的侧壁被掺杂，故而形成一个第三掺杂区(9)，它被第一导电类型掺杂，该掺杂区和沟槽(7)直接相邻，并且它从硅层(3)的主面(5)延伸至绝缘层(2)上，
-其中，附加沟槽(7)由绝缘材料填充，
-其中，在硅层(3)的主面(5)上制造一个到第三掺杂区(9)的接触。
8.根据权利要求5至7之一的方法，
-其中，制造这个或这些带有斜侧壁的沟槽(4，7)，故而在主面(5)的沟槽横剖面比在沟槽底部的要大。
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19528573.5 | 1995-08-03 | ||
| DE19528573A DE19528573A1 (de) | 1995-08-03 | 1995-08-03 | Photodiode und Verfahren zu deren Herstellung |
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| Publication Number | Publication Date |
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| CN1197547A true CN1197547A (zh) | 1998-10-28 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN96197152A Pending CN1197547A (zh) | 1995-08-03 | 1996-07-05 | 光电二极管及其制造方法 |
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| Country | Link |
|---|---|
| US (1) | US5994751A (zh) |
| EP (1) | EP0842544B1 (zh) |
| JP (1) | JPH11510318A (zh) |
| KR (1) | KR19990036096A (zh) |
| CN (1) | CN1197547A (zh) |
| CA (1) | CA2228408A1 (zh) |
| DE (2) | DE19528573A1 (zh) |
| TW (1) | TW354430B (zh) |
| WO (1) | WO1997006566A1 (zh) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034876A (zh) * | 2009-09-30 | 2011-04-27 | 株式会社电装 | 具有soi衬底的半导体装置及其制造方法 |
| CN106206629A (zh) * | 2015-05-28 | 2016-12-07 | 台湾积体电路制造股份有限公司 | 无注入损伤的图像传感器及其方法 |
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| DE19728282A1 (de) * | 1997-07-02 | 1999-01-07 | Siemens Ag | Herstellverfahren für einen Isolationsgraben in einem SOI-Substrat |
| US6611037B1 (en) * | 2000-08-28 | 2003-08-26 | Micron Technology, Inc. | Multi-trench region for accumulation of photo-generated charge in a CMOS imager |
| KR100562667B1 (ko) * | 2000-08-31 | 2006-03-20 | 매그나칩 반도체 유한회사 | 이미지센서 및 그 제조방법 |
| US6538299B1 (en) | 2000-10-03 | 2003-03-25 | International Business Machines Corporation | Silicon-on-insulator (SOI) trench photodiode |
| US6451702B1 (en) * | 2001-02-16 | 2002-09-17 | International Business Machines Corporation | Methods for forming lateral trench optical detectors |
| JP2005045125A (ja) * | 2003-07-24 | 2005-02-17 | Hamamatsu Photonics Kk | 光検出素子の製造方法 |
| JP4046069B2 (ja) | 2003-11-17 | 2008-02-13 | ソニー株式会社 | 固体撮像素子及び固体撮像素子の製造方法 |
| US6969899B2 (en) * | 2003-12-08 | 2005-11-29 | Taiwan Semiconductor Manufacturing Co., Ltd. | Image sensor with light guides |
| DE102004060365B4 (de) * | 2004-12-15 | 2009-03-19 | Austriamicrosystems Ag | Bauelement mit Halbleiterübergang und Verfahren zur Herstellung |
| US20060249789A1 (en) * | 2005-04-13 | 2006-11-09 | Shrenik Deliwala | Inter-digitated silicon photodiode based optical receiver on SOI |
| DE102005026242B4 (de) * | 2005-06-07 | 2007-05-03 | Austriamicrosystems Ag | Photodiode mit integrierter Halbleiterschaltung und Verfahren zur Herstellung |
| US7446018B2 (en) * | 2005-08-22 | 2008-11-04 | Icemos Technology Corporation | Bonded-wafer superjunction semiconductor device |
| US7576404B2 (en) * | 2005-12-16 | 2009-08-18 | Icemos Technology Ltd. | Backlit photodiode and method of manufacturing a backlit photodiode |
| JP2009206356A (ja) * | 2008-02-28 | 2009-09-10 | Toshiba Corp | 固体撮像装置およびその製造方法 |
| US8030133B2 (en) * | 2008-03-28 | 2011-10-04 | Icemos Technology Ltd. | Method of fabricating a bonded wafer substrate for use in MEMS structures |
| CN101714591B (zh) * | 2009-11-10 | 2012-03-14 | 大连理工大学 | 一种硅光电二极管的制作方法 |
| US8063424B2 (en) * | 2009-11-16 | 2011-11-22 | International Business Machines Corporation | Embedded photodetector apparatus in a 3D CMOS chip stack |
| JP5880839B2 (ja) * | 2012-02-17 | 2016-03-09 | 国立大学法人九州工業大学 | トレンチダイオードの製造方法 |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| US4157926A (en) * | 1977-02-24 | 1979-06-12 | The United States Of America As Represented By The Secretary Of The Navy | Method of fabricating a high electrical frequency infrared detector by vacuum deposition |
| GB2095905B (en) * | 1981-03-27 | 1985-01-16 | Philips Electronic Associated | Infra-red radiation imaging devices and methods for their manufacture |
| JPS60140752A (ja) * | 1983-12-28 | 1985-07-25 | Olympus Optical Co Ltd | 半導体光電変換装置 |
| US5360987A (en) * | 1993-11-17 | 1994-11-01 | At&T Bell Laboratories | Semiconductor photodiode device with isolation region |
-
1995
- 1995-08-03 DE DE19528573A patent/DE19528573A1/de not_active Withdrawn
-
1996
- 1996-07-05 EP EP96921897A patent/EP0842544B1/de not_active Expired - Lifetime
- 1996-07-05 WO PCT/DE1996/001210 patent/WO1997006566A1/de not_active Application Discontinuation
- 1996-07-05 DE DE59608456T patent/DE59608456D1/de not_active Expired - Fee Related
- 1996-07-05 KR KR1019980700763A patent/KR19990036096A/ko not_active Application Discontinuation
- 1996-07-05 US US09/000,380 patent/US5994751A/en not_active Expired - Fee Related
- 1996-07-05 CN CN96197152A patent/CN1197547A/zh active Pending
- 1996-07-05 CA CA002228408A patent/CA2228408A1/en not_active Abandoned
- 1996-07-05 JP JP9508001A patent/JPH11510318A/ja active Pending
- 1996-07-09 TW TW085108276A patent/TW354430B/zh active
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102034876A (zh) * | 2009-09-30 | 2011-04-27 | 株式会社电装 | 具有soi衬底的半导体装置及其制造方法 |
| CN102034876B (zh) * | 2009-09-30 | 2013-02-13 | 株式会社电装 | 具有soi衬底的半导体装置及其制造方法 |
| CN106206629A (zh) * | 2015-05-28 | 2016-12-07 | 台湾积体电路制造股份有限公司 | 无注入损伤的图像传感器及其方法 |
| US10177187B2 (en) | 2015-05-28 | 2019-01-08 | Taiwan Semiconductor Manufacturing Company Ltd. | Implant damage free image sensor and method of the same |
| CN106206629B (zh) * | 2015-05-28 | 2019-09-27 | 台湾积体电路制造股份有限公司 | 无注入损伤的图像传感器及其方法 |
Also Published As
| Publication number | Publication date |
|---|---|
| DE19528573A1 (de) | 1997-02-06 |
| KR19990036096A (ko) | 1999-05-25 |
| WO1997006566A1 (de) | 1997-02-20 |
| CA2228408A1 (en) | 1997-02-20 |
| EP0842544A1 (de) | 1998-05-20 |
| JPH11510318A (ja) | 1999-09-07 |
| US5994751A (en) | 1999-11-30 |
| DE59608456D1 (de) | 2002-01-24 |
| TW354430B (en) | 1999-03-11 |
| EP0842544B1 (de) | 2001-12-12 |
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