CN1188913C - High-performance grid nitride ROM structure - Google Patents
High-performance grid nitride ROM structure Download PDFInfo
- Publication number
- CN1188913C CN1188913C CNB011358254A CN01135825A CN1188913C CN 1188913 C CN1188913 C CN 1188913C CN B011358254 A CNB011358254 A CN B011358254A CN 01135825 A CN01135825 A CN 01135825A CN 1188913 C CN1188913 C CN 1188913C
- Authority
- CN
- China
- Prior art keywords
- layer
- polysilicon
- amorphous silicon
- grid structure
- germanium
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Semiconductor Memories (AREA)
Abstract
The present invention discloses a structure of a high-performance grid nitride read only memory. The structure is formed in the following way: firstly, a tunnel oxidizing layer is arranged on a substrate; secondly, an amorphous silicon layer is arranged on the tunnel oxidizing layer; thirdly, a polycrystalline silicon germanium layer is arranged on the amorphous silicon layer; fourthly, an inner polycrystalline silicon dielectric layer is arranged on the polycrystalline silicon germanium layer; finally, a polycrystalline silicon layer is arranged on the inner polycrystalline silicon dielectric layer.
Description
Invention field:
The invention relates to a kind of structure of semiconductor element, particularly relevant for a kind of structure of high-performance grid nitride ROM.
Background of invention:
Semiconductor element comprises most individual independently assemblies usually and is formed on the ground, or is formed in the ground.For instance, similarly be shown in existing Figure 1A, memory component for example flash memory 100 comprises one or more memory arrays 102 and peripheral region 104 on a ground 106.Typically memory array 102 is made up of an independent MXN array at least, typically same substantially floating grid form memory cell and peripheral region 104 comprise input/output circuitry and are used in selectivity designating unit address circuit and (for example are used in the source electrode, grid and the drain electrode that link the selectivity element address, with the running that the voltage set or impedance go to influence designating unit, for example sequencing, read or remove).
The memory cell that memory array is 102 li is attached at and not b gate (NAND) pattern circuit structure, for example, and existing Figure 1B structure.Each memory cell 108 has drain electrode 108a, source electrode 108b and piled grids 108c.Most memory cell 108 link together at selected continuous drain transistor one end and the source transistor other end, to form a succession of and not b gate shown in existing Figure 1B.Each piled grids 108c binding character line (WLO, WL1 ... WLn), when the drain electrode of each selected drain transistor link the bit line (BLO, BL1 ... BLn).At last, the source electrode of selected source transistor is linked to common source line Vss.Decoding and control circuit around using, make each memory cell 108 can be by sequencing, read or remove.
Existing Fig. 1 C represents the memory array 102 of memory cell 108 at existing Figure 1A and Figure 1B.Usually memory cell 108 comprises source electrode 108b, drain electrode 108a and passage 110 in ground, or in the P-well 112; Be covered on the passage 110 with stacked gate architectures 108c.Piled grids 108c more comprises thin gate dielectric 114a (as tunnel oxidation layer) and is formed on the ground of P-well.Stacked gate architectures 108c also comprises polysilicon floating gate 114b, and polysilicon floating gate 114b is formed on the tunnel oxidation layer 114a and is formed on the polysilicon floating gate 114b with interior polysilicon dielectric layer 114c.Interior polysilicon dielectric layer 114c is generally most insulating barriers, similarly is to have oxide layer-silicon nitride layer-oxide layer (ONO) structure that two-layer oxide layer is clipped in the middle silicon nitride layer.At last, polysilicon control grid utmost point 114d is formed on the interior polysilicon dielectric layer 114c.The control grid 114d of individual memory cell 108 is formed at horizontal row (for example, referring to existing Figure 1B).In addition, the drain region 108a of individual memory cell links together vertical row by conduction bit line (BL).Consistent with the electric field development in passage 110 by stacked gate architectures 108, the passage 110 of memory cell 108C is conduction current between source electrode 108b and drain electrode 108a.
Manufacturing comprises a plurality of respective process steps as the processing procedure of and not b gate pattern flash memory component.Provide usefulness relevant most of flash memory component combinations with the unanimity of reliability.For instance, the non-probably expectation of thicker floating grid quick (cracking) betides metal silication tungsten, is because high depth-width ratio rate (high aspect ratios) and high just rise and fall (hightopographies) with etch issues takes place probably.Yet thicker floating grid is released on the tunnel oxidation layer with higher stress, to improve tunnel oxidation layer reliability, conductibility and preferred circuit execution result.The non-probably expectation between via the etching emergence period of thin floating grid penetrates (punch-through), particularly is used in the ground floor polysilicon layer contact etch of selected grid, also non-ly desirably is increased in little hole defect.In addition, when ground floor polysilicon layer thickness is too thin, soak cleaning step (existing formation ONO sandwich multilayer dielectric layer) with hydrogen fluoride (HF) and can stripping separate ground floor polysilicon and infringement tunnel oxidation layer.
If it is highly too low to mix in the control grid, character line resistance and contact resistance become undesirably not high, become undesirably not high with the resistivity that particularly is used in selected grid.Yet the low-doped meeting of floating grid makes tunnel oxidation layer--it is comparatively smooth that floating grid connects face.If it is highly too high to mix in floating grid, non-desirably generation is mixed and is partitioned to tunnel oxidation layer, so that undermine the tunnel oxidation layer integration.The highly doped height of non-expectation causes rugged surface between floating grid and tunnel oxidation layer, causes high internal field, suboxides dielectric strength, with sequencing/removing endurance circulatory problems.
The shortcoming of prior art is that polysilicon gate has shortage effect and low-doped active region, between polysilicon layer/oxide layer or the low reliability of polysilicon germanium layer/silicon dioxide layer interface, with low gate oxidation integration.
And based on these above-mentioned reasons, the utmost point desires to seek a kind of structure of high-performance grid nitride ROM.
Summary of the invention:
In above-mentioned background of invention, many shortcomings that traditional semiconductor element processing procedure is produced provide a kind of structure of high-performance grid nitride ROM in the present invention.Emphasis of the present invention is that the floating grid of memory array and peripheral region and control grid are replaced traditional polysilicon with polycrystalline silicon germanium.The generation type of polysilicon germanium layer is to deposit an amorphous silicon layer earlier on one silica layer, on this amorphous silicon layer, deposit a polysilicon germanium layer then, it is characterized in that the generation type of polysilicon germanium layer is to form a polysilicon layer in a conventional manner earlier, and then doped germanium.After hot processing procedure in, the germanium in the polysilicon germanium layer can diffuse to amorphous silicon layer, to avoid diffusing to silicon oxide layer, therefore, the quality of silica, for example breakdown voltage is improved.
In above-mentioned background of invention, traditional many shortcomings that semiconductor component structure produced, a kind of structure of high-performance grid nitride ROM is provided in the present invention, can be reduced in effect of polysilicon shortage and reduction equivalent oxide thickness in the conventional process simultaneously.
The present invention's main purpose system provides a kind of structure of high-performance grid nitride ROM, in order to improve the grid oxic horizon integration in zone around.
Another object of the present invention system provides a kind of structure of high-performance grid nitride ROM, in order to reduce the effect of polysilicon shortage and to reduce equivalent oxide thickness.
The present invention's the 3rd purpose system provides a kind of structure of high-performance grid nitride ROM, to improve active area doping content and yield.
According to above-mentioned purpose, the present invention has disclosed a kind of structure of high-performance grid nitride ROM.This structure comprises tunnel (tunnel) oxide layer on ground.The thickness of tunnel oxidation layer is approximately between 120 to 180 dusts.Then, amorphous silicon layer is on tunnel oxidation layer.The amorphous silicon series of strata form by Low Pressure Chemical Vapor Deposition.The thickness of amorphous silicon layer is approximately between 30 to 60 dusts.Moreover polysilicon germanium layer (polysilicon layer doped germanium) is on amorphous silicon layer.The thickness of polysilicon germanium layer is approximately between 90 to 100 dusts.Then, interior polysilicon dielectric layer is on polysilicon germanium layer.Interior polysilicon dielectric layer comprise at least first oxide layer, silicon nitride layer on first oxide layer with second oxide layer on this silicon nitride layer.At last, polysilicon layer is on interior polysilicon dielectric layer.
The present invention's purpose and plurality of advantages be by the detailed description of following preferred embodiment, and with reference to institute's accompanying drawing, will be tending towards clear.
Description of drawings:
The present invention's above-mentioned purpose and advantage will be described below in detail with following embodiment and diagram:
Figure 1A is the layout plane graph of existing flash memory;
Figure 1B is existing and not b gate pattern flash memory circuit structural representation;
Fig. 1 C is the cross-sectional view of the structure of existing piled grids flash memory cell;
Fig. 2 A shows is most preferred embodiment according to the present invention, about a kind of cross-sectional view of structure of high-performance grid nitride ROM; And
Fig. 2 B shows is another most preferred embodiment according to the present invention, about a kind of cross-sectional view of structure of high-performance grid nitride ROM.
Embodiment:
The present invention can be widely applied in many semiconductor devices, and can utilize many different semi-conducting material manufacturings, when the present invention illustrates structure of the present invention with a preferred embodiment, the due cognition of the personage in existing this field is that many step and materials can be replaced, and these general replacements also do not break away from spirit of the present invention and claim scope far and away.
Secondly, the present invention is described in detail as follows with schematic diagram, and when the detailed description embodiment of the invention, the profile of expression semiconductor structure can be disobeyed general ratio and be done local the amplification in order to explanation in manufacture of semiconductor, so should be with this as the cognition that qualification is arranged.In addition, in the making of reality, should comprise the three dimensions size of length, width and the degree of depth.
Shown in Fig. 2 A, provide to form to have regions and source 202 in ground 200.Passage area (not being shown among the figure) is between regions and source 202.Form tunnel oxidation layer 204 on the passage area of ground 200.The thickness of tunnel oxidation layer 204 is approximately between 120 to 180 dusts.Then, form first amorphous silicon layer 206 on tunnel oxidation layer 204.First amorphous silicon layer 206 is to form by Low Pressure Chemical Vapor Deposition.The thickness of first amorphous silicon layer 206 is approximately between 30 to 60 dusts.Then, form first polysilicon germanium layer 208 (polysilicon layer doped germanium) on first amorphous silicon layer 206.Providing first doped polysilicon layer to cover above first amorphous silicon layer 206 is to utilize homogeneous (in-situ) dopping process.In the present embodiment, doped germanium to polysilicon layer is to utilize the low-pressure chemical vapor deposition mode to form first polysilicon germanium layer 208, in temperature approximately between 450 ℃ to 620 ℃, and temperature is preferably 530 ℃, pressure approximately under 150 to 350mTorr condition in this implementation column, and pressure is preferably 200mTorr in this implementation column.The thickness of first polysilicon germanium layer 208 is approximately between 90 to 100 dusts.Moreover polysilicon dielectric layer 210 is on first polysilicon germanium layer 208 in forming.Interior polysilicon dielectric layer 210 comprises three layers for ONO plural number dielectric layer; Comprise the first oxide layer 210a, silicon nitride layer 210b, with the second oxide layer 210c.Interior polysilicon dielectric layer 210 thickness are approximately 130 dusts.Deposit the first oxide layer 210a in first polysilicon germanium layer 208 by the long-pending mode in low pressure chemical Shen, temperature is approximately 750 ℃, and pressure is approximately 600mTorr.Then depositing nitride is approximately 760 ℃ to form silicon nitride layer 210b in temperature, and pressure is approximately under the 330mTorr condition.Having wet type dioxygen oxidation silicon nitride layer 210b is approximately under 950 ℃ of conditions in temperature to form the second oxide layer 210c.At last, form polysilicon layer 212 on interior polysilicon dielectric layer 210.This structure also can be applicable to the grid structure of conventional metals oxide-semiconductor.
Shown in Fig. 2 B, this figure deposits ground through part among continuity Fig. 2 A, it is characterized in that, forms second amorphous silicon layer 214 and second polysilicon germanium layer 216 in regular turn thereon.The present invention can use polysilicon germanium layer and amorphous silicon layer in polysilicon control grid extremely in.Form second amorphous silicon layer 214 on polysilicon layer 212.Second amorphous silicon layer 214 forms by Low Pressure Chemical Vapor Deposition.Second amorphous silicon layer, 214 thickness are approximately between 30 dust to 60 dusts.Form second polysilicon germanium layer 216 (polysilicon layer doped germanium) on second amorphous silicon layer 214.Providing second doped polysilicon layer to cover above first amorphous silicon layer 214, is to utilize homogeneous (in-situ) dopping process.In the present embodiment, doped germanium to polysilicon layer is to utilize the low-pressure chemical vapor deposition mode to form second polysilicon germanium layer 216, in temperature approximately between 450 ℃ to 620 ℃, and temperature approximately is preferably 530 ℃, pressure approximately under 150 to 350mTorr condition in the present embodiment between 450 ℃ to 620 ℃, and pressure is preferably 200mTorr in this implementation column.The thickness of second polysilicon germanium layer 216 is approximately between 90 to 100 dusts.
According to the structure of a kind of high-performance grid nitride ROM provided by the present invention, have following advantage:
1, provides a kind of structure of high-performance grid nitride ROM, in order to improve regional around grid oxic horizon integration.
2, provide a kind of structure of high-performance grid nitride ROM, in order to reduce the effect of polysilicon layer shortage and to reduce equivalent oxide thickness.
3, provide a kind of structure of high-performance grid nitride ROM, in order to improve active area doping content and yield.
The above only is the present invention's embodiment, is not in order to limit claim scope of the present invention; All other do not break away from following equivalence of finishing of disclosed spirit and changes or modification, all should be included in the claim.
Claims (10)
1, a kind of grid structure on ground, this grid structure comprises:
One tunnel oxidation layer is on this ground;
One amorphous silicon layer is on this tunnel oxidation layer;
One polysilicon germanium layer is on this amorphous silicon layer;
Polysilicon dielectric layer in one is on this polysilicon germanium layer; And
One polysilicon layer is in this on polysilicon dielectric layer.
2, grid structure according to claim 1 is characterized in that, above-mentioned amorphous silicon layer is to form by the Low Pressure Chemical Vapor Deposition mode.
3, grid structure according to claim 1 is characterized in that, the thickness of above-mentioned amorphous silicon layer is between 30 to 60 dusts.
4, grid structure according to claim 1 is characterized in that, the thickness of above-mentioned polysilicon germanium layer is between 90 to 100 dusts.
5, grid structure according to claim 1 is characterized in that, above-mentioned interior polysilicon dielectric layer comprises first oxide layer, silicon nitride layer and second oxide layer at least, and this silicon nitride layer is on first oxide layer, and this second oxide layer is on this silicon nitride layer.
6, a kind of grid structure on ground, this grid structure comprises:
One tunnel oxidation layer is on this ground;
One first amorphous silicon layer is on this tunnel oxidation layer;
One polysilicon germanium layer is on this first amorphous silicon layer;
Polysilicon dielectric layer in one on this polysilicon germanium layer, should interior polysilicon dielectric layer be to comprise first oxide layer, silicon nitride layer and second oxide layer wherein, and wherein this silicon nitride layer is on this first oxide layer, and this second oxide layer is on this silicon nitride layer;
One polysilicon layer is in this on polysilicon dielectric layer;
One second amorphous silicon layer is on this polysilicon layer; And
One second polysilicon germanium layer is on this second amorphous silicon layer.
7, grid structure according to claim 6 is characterized in that, above-mentioned first amorphous silicon layer is to form by the Low Pressure Chemical Vapor Deposition mode.
8, grid structure according to claim 6 is characterized in that, the thickness of above-mentioned first amorphous silicon layer is between 30 to 60 dusts.
9, grid structure according to claim 6 is characterized in that, the thickness of above-mentioned first polysilicon germanium layer is between 90 to 100 dusts.
10, grid structure according to claim 6 is characterized in that, the thickness of above-mentioned second polysilicon germanium layer is between 90 to 100 dusts.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011358254A CN1188913C (en) | 2001-10-18 | 2001-10-18 | High-performance grid nitride ROM structure |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB011358254A CN1188913C (en) | 2001-10-18 | 2001-10-18 | High-performance grid nitride ROM structure |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1412858A CN1412858A (en) | 2003-04-23 |
| CN1188913C true CN1188913C (en) | 2005-02-09 |
Family
ID=4673297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB011358254A Expired - Fee Related CN1188913C (en) | 2001-10-18 | 2001-10-18 | High-performance grid nitride ROM structure |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN1188913C (en) |
Families Citing this family (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100334740C (en) * | 2003-08-26 | 2007-08-29 | 茂德科技股份有限公司 | Power MOSFET and its mfg. method |
| CN100353566C (en) * | 2003-10-20 | 2007-12-05 | 旺宏电子股份有限公司 | Silicon layer structure with transformation particle size and method for forming the same structure by thermal technology |
| US7482651B2 (en) * | 2005-12-09 | 2009-01-27 | Micron Technology, Inc. | Enhanced multi-bit non-volatile memory device with resonant tunnel barrier |
-
2001
- 2001-10-18 CN CNB011358254A patent/CN1188913C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1412858A (en) | 2003-04-23 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR100727617B1 (en) | Nand type flash memory device | |
| US8349686B2 (en) | Nonvolatile semiconductor memory device and method of manufacturing the same | |
| US20050087892A1 (en) | [nand flash memory cell row, nand flash memory cell array, operation and fabrication method thereof] | |
| US5933729A (en) | Reduction of ONO fence during self-aligned etch to eliminate poly stringers | |
| US20080305596A1 (en) | Method of fabricating non-volatile memory | |
| EP0699345A1 (en) | A fast access amg eprom with segment select transistors which have an increased width and method of manufacture | |
| JP5361335B2 (en) | Nonvolatile semiconductor memory device and manufacturing method thereof | |
| CN1087501C (en) | Method for making nonvolatile memory | |
| US6455890B1 (en) | Structure of fabricating high gate performance for NROM technology | |
| US6046085A (en) | Elimination of poly stringers with straight poly profile | |
| CN1188913C (en) | High-performance grid nitride ROM structure | |
| US7592271B2 (en) | Method of fabricating a flash memory device | |
| JPH09213911A (en) | Semiconductor device and manufacturing method thereof | |
| US7400010B2 (en) | Semiconductor device and method of manufacturing the same | |
| CN1198322C (en) | Single tunnel gate oxidation process for fabricating NAND flash memory | |
| KR100417029B1 (en) | Method for manufacturing nonvolatile semiconductor memory with narrow variation in threshold voltages of memory cells | |
| KR100639460B1 (en) | Method for forming gate of flash memory device | |
| US6710381B1 (en) | Memory device structure with composite buried and raised bit line | |
| JPH0637326A (en) | Nonvolatile semiconductor storage device and manufacture thereof | |
| KR100289814B1 (en) | Non-volatile memory device and method for manufacturing the same | |
| KR19990012155A (en) | Nonvolatile Memory Device and Manufacturing Method Thereof | |
| EP1069620A1 (en) | A flash memory array | |
| US20110059585A1 (en) | Nonvolatile memory device and fabrication method | |
| JPH01298770A (en) | Semiconductor device and manufacture thereof | |
| JPH05218440A (en) | Manufacture of nonvolatile semiconductor storage device |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20050209 Termination date: 20191018 |