CN1188553A - Generator for delay-matched clock and data signals - Google Patents
Generator for delay-matched clock and data signals Download PDFInfo
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- CN1188553A CN1188553A CN 96194849 CN96194849A CN1188553A CN 1188553 A CN1188553 A CN 1188553A CN 96194849 CN96194849 CN 96194849 CN 96194849 A CN96194849 A CN 96194849A CN 1188553 A CN1188553 A CN 1188553A
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Abstract
A delay matched clock and data generator utilizes a re-timing element having the functionality of a two-input multiplexer, connected and operated such that the level on the output(s) is controlled from level control inputs, and the timing of transitions on the output(s) is controlled from timing control inputs. The level control inputs on the re-timing element correspond to the data input(s) on an equivalent multiplexer. The generator further has control inputs for stopping the clock low or stopping the clock high, and the generator may be operated for polarity independent clock gating or clock synthesis.
Description
Technical field
The invention relates to the data transmission from data source to the data destination, or rather, data transmission means data source and provides two signals to the destination: data-signal and clock signal, clock signal are used for the timing that destination data receives trigger.
Background of invention
Synchro system has many superior parts in design with in using.By timing restricting signal boundary, the pacing system with global clock has improved robustness and has simplified logical design.Owing to there is clock system, the lower bound delay issue has obtained concern.Along with the raising of system speed, because clock signal can't make the delay of clock buffer become problem connecting simultaneously Anywhere of system.This problem can obtain in various degree solution with three types innovative approach:
1) under the high clock frequency of appropriateness, it is main cushioning delay associated with clock on the monolithic.This means that the clock signal that other clock elements on trigger and/or the circuit are carried out timing obviously lags behind overall reference clock.Use monolithic clock buffer system PLL, relevant with clock distribution on clock buffering and sheet delay can be offset relatively.
2) even when higher speed, the transmission of data-signal surpasses certain distance usually, particularly passes to another circuit from a circuit, and the delay of signal makes the application of global synchronization clock become impossible.The electricity and the limited velocity of propagation of light frequency signal make the same period or synchronization concept meaningless.Usually, this limitation can use the synchronizing circuit of adjusting the phase relation between clock and the digital signal in destination self-adaptation in the receiver phase territory to be overcome.But synchronizing circuit increases the cost and the power consumption of system.
3) for high frequency, the distance that signal sends in controlled signalling environment is quite short, and a simpler solution can be used.Problem at suitable moment gating or instrumentation data-signal can solve with laxative remedy: both sent data-signal, sent again from data source by the clock signal of fine delay match circuit to the destination.This clock signal is used for only gated data when the effective logic level of data of receiver.
Use typical case's application of clock and data transmission to be shown in Fig. 1 in the prior art, there is shown the operational process of unlike signal.
The modern integrated circuits technology allows to use more and more higher clock frequency when data transmission.This postpones the higher requirement of coupling proposition to all of clock and data signal path.Because it is difficult that clock has different character that there are the clock of matched well and data-signal in generation porch position with data-signal.The position, edge that has subject clock signal control through flip-flop data signal self.The clock signal that generation has coupling position, edge is difficult.In any case, it is possible finishing matching delay with identical circuit component.But the also output clocking of slave flipflop, this requires the frequency of signal source clock signal will take advantage of 2, because trigger output changes only in response to a limit that connects the signal on the trigger input end of clock.In the high-speed applications field, clock frequency has been subject to processing the restriction of technology.By a kind of performance shown in Figure 1, above-mentioned speed can not realize, because reception trigger RF can not be in the optimum timing near data pattern.
Figure 2 shows that the signal mode sequential when running status A specifically is set.At this, use clock C
5Rising edge to entering the data-signal D of trigger RF
5Carry out timing, look very safe seemingly, but when considering t Time Created
SuThe time, C
5Marginal edge can not produce stable result.Yet above-mentioned saying is only based on individual other observation.
Handle Fig. 3, suppose that voltage and/or temperature change, so that gate delay and t in the present circuit
SuAll can double to change.Very clear, clock C
5Marginal edge pressure-gradient control valve is gone up chronometric data D for receiving trigger RF
5The forward edge, this is the situation of Fig. 2.In order to obtain maximum operation frequency, consider owing to the different operating condition causes the variation of gate delay it is very important.
For high speed signal under multiple condition of work can send reliably, the variation of the gating point relevant with receiving data-signal must be reduced to minimum.Owing to transmit and receive circuit and can under different voltage and temperature conditions, work together, only the transmitter time-delay in radiating circuit by compensation and receive delay in receiving circuit during by compensation tracking just can reach.Transmitter clock and output are not only zero with the delay difference between the data of operation conditions change.
There is delay poor between the output of clock and data in Fig. 1 circuit.It equals clock C
1Delay to the Q of trigger FT output.For delay compensation, clock signal must be through the delay of equal number.The reproducer that designs the element of the clock that formation postpones Q in trigger FT just can achieve the above object carefully, as long as be right after trigger by adorning same circuit, so condition of work is identical.Yet the tangible characteristic of trigger makes that it is difficult reaching the coupling of moment not with the clock signal two divided-frequency time.
Handle in the synchronous file in some prior aries, the global clock signal frequency is enhanced the notion that causes the same period, and no longer meaning is profound.The clock signal on various objectives ground is (frequency is accurate, but phase place is any) but asynchronous simultaneously.Some files, for example EP-B1-0 356 042, and DE-A1-4 132 325, and US-A-5 022 056, and US-A-5 115455 and US-A-5 359 630 have narrated the distinct methods of handling this phase place uncertainty.All these methods are all utilized multiplexer but are no longer retimed.The selected control input end is used to select one of input data to give multiplexer, makes on output terminal it is the input control timing with described conversion.
Particularly latter two can not accomplish matching delay with reference to can be used as main foundation of the present invention although clock signal sends from same place with data-signal.For this reason, receiving the synchronizing function that the limit is provided with complexity.
Abstract of invention
By primary goal of the present invention is to utilize a kind of time-delay coupling clock and the number generator of the timing element again of the function performance with two input multiplexer that connect and turn round.Make its output terminal level be controlled by the control input end level, saltus step regularly is controlled by the timing controlled input end on the output terminal, and the level control input end of timing element is equivalent to the data input pin on the equivalent multiplexer again.
The present invention further target is stated by independent claims.
The cutline of accompanying drawing
Will be by the preferred embodiment that thought over and the present invention will be described in conjunction with the accompanying drawings, wherein to identical part with identical witness marker.Among the figure:
Fig. 1 is clock and the data transmission that does not have compensation of delay;
Figure 2 shows that the situation of Fig. 1 circuit at condition of work A;
Figure 3 shows that the situation of Fig. 1 circuit at condition of work B;
Fig. 4 a, 4b are depicted as the single-ended example of timing circuit again;
Fig. 5 is the example explanation of matching delay clock and number generator;
Fig. 6 is 1NV=1 among Fig. 5, the sequential of matching delay generator during NON1=0;
Fig. 7 a, 7b are the example explanation with timing circuit again of width distortion in the arteries and veins;
Fig. 8 is 1NN=0 among Fig. 5, the sequential of time-delay matched generator during NONI=1;
Clock gating 1NV and the NONI that aligns clock shown in Figure 9;
Clock gating 1NV and NONI to negative clock shown in Figure 10;
Figure 11 is synthetic for clock;
Figure 12 is for being provided with the principle of time bias to the reception trigger according to existing invention;
Figure 13 a is depicted as the NAND door that master-slave flip-flop constitutes;
Figure 13 b be depicted as the NAND door trigger that is used for Figure 13 a Time Created corrective network an example;
Figure 14 a is the formation of master-slave flip-flop transmission gate;
Figure 14 b be used for Figure 14 a transmission gate trigger Time Created corrective network an example.
Figure 15 shows that and use the detailed example of the differential logic circuit of timing element again;
An illustrative is executed the description of example
Delay that the present invention expected coupling is by means of not only clock being realized signal not only by the timing circuit again of can processing clock but also can process data signal.This circuit is worked like this, the logic level of one group of control output end of feasible input, and the saltus step of another group control output signal of input is regularly.
Such circuit can be realized with plurality of proposals: logic gate, and by transistor or the like.Such scheme has some something in commons.The most important thing is that these circuit all can be used as multiplexer when working with other mode.Any multiplexer can be as postponing matched generator.The multiplexer of some types (not every) can realize the maximum utility of timing function again, and this function is illustrated in Fig. 4 a, 4b and Figure 15.
Figure 5 shows that use two again timing element RTE-D and RTE-C one postpone coupling clock and number generator.The data-storing that sends is in trigger FT.This trigger FT need not become the part of generator.This is that expression guarantees that again timing element RTE-D input end INO goes up the device example that signal has suitable timing.Latch LT is used for postponing being input to the data that RTE-D goes up IN1, makes at output level D
2Be controlled by on the 1N1 of RET-D in whole duration of 1N1 on the RTE-D stable level is arranged.As shown in Figure 6, at the output terminal D of RTE-D
2Last reproduction D
1Data.D
2The position at signal edge is subjected to C
1The control of clock signal.Its timing relationship equals from the CLK input end to timing element D again
2The delay of end.The output that postpones the coupling clock is by producing with timing element RTE-D is identical again RTE-C.Control signal 1NV and NONI have stable level, output level C in the whole time cycle
2Be controlled by each input end.Fig. 6 is illustrated in C when constant logical one being arranged on the 1NV end and on the NONI end constant logical zero being arranged
2Characteristic.Produce C like this
2Rising edge and D
2On data saltus step simultaneously.To C
1Negative edge, both have identical delay relation.1NV and NONI signal are motor-driven in the practical application, and the device similar to number generator can be used to guarantee 1NV and the suitable timing of NONI signal.The 1NV signal can be by C
1Produce in the trigger of signal timing.The NONI signal can produce from the latch of anti-phase timing.TD and TC representative is used to break away from the driver of the signal of chip.
If one is used for multiplexer regularly again the rising of clock selection signal and decline is had different propagation delays from the input end of clock/selection to output terminal.Then must two again timing block be connected to clock signal in a like fashion to obtain correct coupling.Fig. 5 describes by the difference equivalence principle the principle of Fig. 4 a and 4b.But use such multiplexer will cause the width distortion of clock signal.This will constitute the unnecessary restriction that obtains maximum operation frequency, at the timing circuit again that has the pulse width distortion shown in Fig. 7 a and the 7b.
1NV shown in Fig. 5 and NONI signal can be used for controlling and gated clock output when still keeping the location at coupling edge, when 1NV and NON1 are low level simultaneously clock are parked on low level.Clock will be parked on high level when 1NV and NON1 are high level simultaneously.Put 1NT=1 and NON1=0 and obtain timing figure shown in Figure 6, present C
1Anti-phase clock C
3By shown in Figure 8, put 1NT=0 and will produce C among a relative Fig. 6 with NONI=1
1Noninverting clock C
3
For the gated clock signal, should insert an additional gating stage usually, this will introduce additional delay.It is exactly that clock signal can and be blocked and do not damage meticulous delay coupling by gating that delay of the present invention coupling clock generator has a key property.Fig. 9 and Figure 10 are explained.
Putting 1NV and NONI two signals is that low level will make output terminal C
2On be output as low level, putting 1NV then is that high level causes by the anti-phase output C of gating
2, as shown in Figure 9.To make C when on the other hand, keeping 1NT and NON1 to be high level
2The constant high output of last generation, putting NON1 then is that low level is then at C
2Last generation is shown in Figure 10 by the anti-phase output of gating.
Suitably use control signal 1NV and NON1 can set up synthetic clock by the present invention, brief description is seen Figure 11.C
1First positive pulse be transferred to C
2, pass through signal C through a complete cycle then
1Be reversed in C
2On can obtain another positive pulse, again through other half period output C
2It is constant high level.So synthetic clock signal has the waveform of arbitrary shape, it mainly limits to is only when being subjected to input clock control the clock output hopping could take place.
Is can guarantee that data are deposited into trigger reliably in condition of work and circuitry processes parameter during for wide region on the receiver limit for the critical condition that obtains top speed.This comprises the time bias of often mentioning that is provided with.In Figure 12, it is compared with the prior art of Fig. 1 and describe.
D flip-flop uses a clock signal, to store by the determined logic level of the signal that is connected to input end D.More precisely, the level that is stored during the existing strobe window of determining with the edge by clock signal is exactly an existing level on the input end D.This strobe window by two numeral-Times Created and the retention time-characterize, its determines now to use the time migration between clock edge and the strobe window.Determine the starting point of strobe window Time Created, the retention time is determined the end of strobe window.The data that trigger stored only are that the signal that is transfused in gate interval on the end D is packed into.
The notion of Time Created and retention time is also inconsistent in commercial Application.Usually, foundation and retention time are used for being expressed in the position of the strobe window of trigger specific under the special operating conditions.But sometimes by the definition of front as the scope of trigger and condition of work and opinion is appointed as maximal value Time Created, then just in time opposite to the retention time.The notion of following Time Created and retention time is still used initial definition.
For making trigger reach maximum data rate, strobe window or data edge will be adjusted, so that the variation of data just appears at outside the strobe window.This can finish by the duplicate circuit in the receiving circuit.When having identical condition of work and processing procedure, the delay of corrective network will be followed the tracks of the delay of introducing Time Created Time Created.Give one example, Figure 13 a is illustrated in the NAND door gear of master-slave flip-flop, is approximately the propagation delay sum of two NAND door G1 and G2 its Time Created.Can constitute single order compensation Time Created with two NAND doors (seeing Figure 13 b) that are equivalent to a G1 and G2.
Two phase inverter I1 and I2 be as the transmission gate assembly of master-slave flip-flop in the circuit of Figure 14 a, can constitute single order with two phase inverters (seeing Figure 14 b) that are equivalent to phase inverter I1 and I2 and compensate Time Created.
Last Figure 15 is a specific example, and the differential logic circuit that is made of again timing element the integrated CMOS transistor is shown.The running of circuit is apparent and visible for the expert, must not be further explained, and only makes embodiment of circuit.So far, the present invention has been perfectly clear for the expert, and such circuit diagram also need not to be described in further detail from element or semiconductor foundation.By the above, the professional and technical personnel can recognize that the present invention can implement with many specific forms under the prerequisite that does not break away from its spirit and basic characteristic.Existing disclosed embodiment has all been done consideration in all respects, so that it has is exemplary and unrestricted.Scope involved in the present invention points out and not narration in front that in additional claim the variation in all equivalent meanings and the scope all is comprised in wherein.
Claims (12)
1. utilize a kind of delay coupling clock and the number generator of the timing element again of function performance with two input multiplexer that connect and turn round, make the level of its output terminal be controlled by the control input end, the saltus step of its output terminal regularly is controlled by the timing controlled input end, wherein, data input pin on the corresponding equivalent multiplexer in the control input end of described timing element again, and the selection input end of the corresponding described equivalent multiplexer of timing controlled input end on the timing element again.
2. delay coupling clock and the number generator according to claim 1 comprises that (1NV NONI), is used to make clock to be parked on low level in the control input end.
3. delay coupling clock and the number generator according to claim 1 comprises that (INV NONI), is used to make clock to be parked on high level in the control input end.
4. delay coupling clock and the number generator according to claim 1 comprises that (1NV NONI), mates inversion signal in order to produce a time-delay in the control input end.
5. according to claim 2,3, or described delay coupling clock and the wherein said generator of data signal generator one of in 4 are used for the clock gating.
6. according to claim 2,3, or the delay coupling clock one of in 4 and data signal generator is used for the irrelevant clock gating of polarity and clock is synthetic.
7. wherein only there is a clock signal to be sent to the receiver region according to coupling clock of the delay one of in the claim 2,3 or 4 and number generator from transmitter.
8. (1NV NONI), is used to make clock to be parked on low level to comprise the control input end according to the delay of claim 7 coupling clock and number generator.
9. (1NV NONI), is used to make clock to be parked on high level to comprise the control input end according to the delay of claim 7 coupling clock and number generator.
10. (1NV NONI), produces and postpones the coupling inversion signal to comprise the control input end according to the delay of claim 7 coupling clock and number generator.
11. according to Claim 8, one time-delay coupling clock and the wherein said generator of number generator are used for the clock gating in 9 or 10.
12. the time-delay coupling clock one of in 9 or 10 and number generator is used for the irrelevant clock gating of polarity or clock is synthetic according to Claim 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 96194849 CN1188553A (en) | 1995-05-02 | 1996-04-15 | Generator for delay-matched clock and data signals |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| SE9501608-5 | 1995-05-02 | ||
| CN 96194849 CN1188553A (en) | 1995-05-02 | 1996-04-15 | Generator for delay-matched clock and data signals |
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| Publication Number | Publication Date |
|---|---|
| CN1188553A true CN1188553A (en) | 1998-07-22 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 96194849 Pending CN1188553A (en) | 1995-05-02 | 1996-04-15 | Generator for delay-matched clock and data signals |
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Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1321361C (en) * | 2002-01-19 | 2007-06-13 | 国家半导体公司 | System for adjusting a power supply level of a digital processing component and method of operating the same |
| CN100339793C (en) * | 2002-07-08 | 2007-09-26 | 威盛电子股份有限公司 | Gate signal and parallel data signal output circuit |
| CN101171788B (en) * | 2005-05-06 | 2011-04-13 | 英特尔公司 | Regulating the timing between a strobe signal and a data signal |
-
1996
- 1996-04-15 CN CN 96194849 patent/CN1188553A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1321361C (en) * | 2002-01-19 | 2007-06-13 | 国家半导体公司 | System for adjusting a power supply level of a digital processing component and method of operating the same |
| CN100339793C (en) * | 2002-07-08 | 2007-09-26 | 威盛电子股份有限公司 | Gate signal and parallel data signal output circuit |
| CN101171788B (en) * | 2005-05-06 | 2011-04-13 | 英特尔公司 | Regulating the timing between a strobe signal and a data signal |
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