CN1188359A - Method for synchronizing transmissions at constant bit rate in ATM networks and circuit arrangement for carrying out the method - Google Patents
Method for synchronizing transmissions at constant bit rate in ATM networks and circuit arrangement for carrying out the method Download PDFInfo
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- CN1188359A CN1188359A CN97121213A CN97121213A CN1188359A CN 1188359 A CN1188359 A CN 1188359A CN 97121213 A CN97121213 A CN 97121213A CN 97121213 A CN97121213 A CN 97121213A CN 1188359 A CN1188359 A CN 1188359A
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Abstract
The synchronisation method involves converting a data stream with constant bit rate on the transmission side from an interworking unit (2) into an asynchronous transfer mode (ATM) cell stream. After transmission to the receiver side, the ATM cells are stored in the input buffer (6). A time stamp is associated with each ATM cell in the buffer which correlates with the time of reception of that cell. The data stored in the ATM cells are output through the interworking unit (9) as a data stream with a constant bit rate. The output starts delayed from the reception time by a time TA. For the delay time, a target value tv is provided, which is greater than the variation of the transmission time of the ATM cells from the transmitter to the receiver. The current delay time is determined by taking the difference between the delay time Ta and the transmission time. An error signal is determined and transmitted to the regulator (13). A control signal is transmitted to the time base (14) and is used to adjust the clock frequency.
Description
The present invention relates in atm network to carry out the method for synchronous transmission and realize the circuit structure of this method with constant bit rate.
In CBR (constant bit rate) transmission, need a unified system clock in the whole net.For this purpose, based on the generation of a center system clock, a hierarchy is established, and by this way, that communicates by letter with the opposing party plays master control (master) effect side's clock, and the opposing party then plays subordinate (slave) effect.In the transmission of STM system, the receiver of subordinate side can be from the signal that receives recovered clock, and make to the received signal processing and the transmitter of itself and this clock synchronization.In telecommunication system, corresponding is master control side with regard to the network layer of hanging down some for higher network layer usually respectively.In the user field, network is master control side and the user is subordinate side basically.
CBR transmission in ATM (asynchronous communication mode) net need be measured especially to obtain synchronously between the information source and the stay of two nights.For example this situation just takes place when transferring voice and image in the ATM net.In the transmission of ATM, can not from the signal that receives, recover a clock.More multiple faults do not make the equipment that is defined as subordinate side reach synchronous specific measuring under the situation, owing to will appear in the inevitable frequency departure of autonomous system.Under the situation of the low excessively clock frequency in subordinate side, in its receiver data congestion will take place and " cavity in the data (hole) " will occur in the receiver in master control side.Under the situation of the too high clock frequency in subordinate side, its receiver " cavities in the data " will occur and " data congestion " will occur in the receiver of master control side.The various methods that guarantee zero defect CBR transmission in ATM net are arranged, they in " I-ETS 300 353 broadband integrated services digital networks (B-ISDN) asynchronous communication modes (ATM) adaptation layers (AAL) standard Class1 " by standardization.
All known methods all have an intercommunication (interworking) unit, and it has an input that is used for the CBR data flow, and this unit is placed on the transmission equipment side (segmentation) of master control side.Interworking unit carries out segmentation according to AAL1 to the CBR data flow and produces ATM cell according to I-ETS 300 353 B-ISDN.The ATM cell that produces is output to the transmission channel of a reality by an output of interworking unit.The actual transmissions path is considered to the summation of all communication link parts, transducer, multiplexer, switching equipment, interconnection etc., and it must be complementary with the transmission channel to the receiver of subordinate side.Because asynchronous communication mode, be unfixed time of delay on the actual transmissions path, but about fluctuation average time (DTV-time of delay be offset (Variation)).Just relevant at the accurate constant cell rate of the output of the interworking unit of master control side like this with the bigger or smaller fluctuation of actual transmissions path end.Therefore, receiving equipment always has an input buffer.The big young pathbreaker of input buffer decides according to the expectation DTV of actual transmissions path, by this way, even when between the arrival cell minimum interval being arranged, buffer can not overflow, and when the time with information source clock synchronization continuous-query, arrive when between cell largest interval being arranged, do not have the clear operation of input buffer to occur in the output of input buffer.The recipient of interworking unit (re-assemblying) is connected to the output of input buffer.According to the corresponding to AAL1 of I-ETS 300 353 B-ISDN, the CBR data flow is re-assemblied from ATM cell by interworking unit.The clock that is produced by time base is input to recipient's interworking unit by an additional input end.This clock has determined to make the data rate of the CBR data flow that can use at the interworking unit output.
In known SRTS (synchronously residual time stamp) method, be transfused to a SRTS generator of system clock by input, be installed in master control side.The SRTS generator produces a time mark from system clock, the residue RTS of system clock (residual time stamp) is imported into an additional input end of master control side's interworking unit by an output.The interworking unit of master control side is inserted into RTS in the AAL1 expense of the ATM cell that is generated.The generation of RTS and being inserted among I-ETS 300 353 B-ISDN by standardization.RTS is a skew with desired value, and this desired value is clearly described this side-play amount with 4 bits (1 bit symbol, 3 bit value).Be received device and think " prior information " because prerequisite is a desired value, so latter's generation time mark again again.From with receiver itself the time base comparison, the adjustment variable of base in the time of can obtaining receiver.For this reason, for example, the SRTS generator of a clock of base when being transfused to by input is installed in the recipient.Similar with the SRTS generator of master control side, this SRTS generator according to the time base the corresponding RTS of free clock generating, it is imported into the input of a required/actual value comparator.Second input of required/actual value comparator is connected to an additional output of recipient's interworking unit.Recipient's interworking unit is extracted the RTS of master control side out from the ATM cell that receives, and this RTS is transported to second input of the value comparator of required/reality.Required/actual value comparator obtains one and is sent to an error variance in the controller from the comparison of two input signals.Controller produces a school and ends variable from this error variance, the base when latter is sent to so that the time base adjust its clock according to this correcting variable.Detailed description can be at " atm network, the third edition, 179 pages of etseq; Othmar Kyas, DATACOM publishing house " in see.The shortcoming of this known method is that master control side and recipient must make amendment aspect hardware and software, and this just makes described method very expensive.
In addition, can know ACR (adaptive clock recovery) method from I-ETS 300 353 B-ISDN, it need not revised in master control side.For this reason, the input buffer in receiver side has an additional output.One shows whether this input buffer has surpassed the control signal that partly is full of and appeared on this additional output.This control signal is sent to the input of a controller.This controller produces a correcting variable, base when this correcting variable is sent to according to this control signal.Base is adjusted clock according to correcting variable in the time of then.It is occupied that the shortcoming of this method is that many cells of input buffer are had to, and sort buffer can influence transmission in the mode of time of delay.Under situation, this means that each cell has the extra delay of 6ms with the 64kbit/s transmission.
Therefore the target that the present invention is based on is, is provided in atm network carrying out the method for synchronous transmission with constant bit rate and realizes the circuit structure of this method, wherein just can obtain short and small time of delay with the less modification of hardware or software aspect.
The solution of this problem utilizes the feature of two aspects of the present invention to obtain.
One aspect of the present invention is, a method that is used in the ATM net, carrying out synchronous transmission with constant bit rate, wherein utilize one comprise input buffer, interworking unit, the time base and controller receiving equipment, make the data flow of constant bit rate cross interworking unit and be converted into atm cell stream, wherein at the transmitter square tube
A) ATM cell is being stored in the input buffer the recipient after the transmission,
B) each in each ATM cell in the input buffer all is endowed a time mark T relevant with its time of reception
S,
C) be stored in output that the data in the ATM cell are carried out as data flow with constant bit rate by interworking unit and start from the time T that postpones with respect to time of reception
A,
D) for this time of delay, a required value t
VBe prescribed the value t that this is required
VGreater than the transmission time skew DTV of the ATM cell from the transmitter to the receiver,
E) the actual delay time is by producing T
A-T
SDifference and determine,
F) error variance t
R=t
V(T
A-T
S) produced, and be sent to controller,
G) controller is according to error variance t
RProduce a correcting variable,
Base when h) correcting variable is sent to, and
I) clock frequency of base oppositely is adjusted with skew mutually according to correcting variable the time.
Another aspect of the present invention is, a receiver station of atm network, comprise an input buffer, an interworking unit, base in the time of one, a required/actual value comparator and a controller, input buffer output is connected to an input of interworking unit in this station, an input of the value comparator of required/reality that an output of interworking unit is connected to, an output of required/actual value comparator is connected to an input of controller, an input of base when an output of controller is connected to, and the time base an output be connected to an input of interworking unit
Base additional output is connected to an input of input buffer in the time of wherein, and the time base an additional output be connected to an input of required/actual value comparator.
Other favourable exquisiteness designs of the present invention obtain from following feature:
Method according to the aspect of the invention described above is characterized in that controller wherein is designed to an integral controller.Its feature is that also controller is according to error variance t
RObtain value of symbol, and according to Δ f=k ∑ (SIG
TA (i)) clock frequency of base when adjusting.
Receiver station according to another aspect of the invention described above is characterized in that its middle controller is designed to an integral controller.
Explain the present invention in more detail below with reference to a preferred example embodiment.In each figure:
Fig. 1 represents the concise and to the point frame circuit diagram of an atm network,
Fig. 2 represents the sequential chart of an initial situation,
Fig. 3 represents a sequential chart under the operating state, and
Fig. 4 represents the sequential chart controlled.
Fig. 2 has illustrated initial situation, i.e. the reception of first ATM cell and output.The sequential chart of the input 7 of time shaft 20 expression input buffers 6.The sequential chart of the output of time shaft 21 expression interworking units 9.The ATM cell 22 of at first coming in is coupled with time mark T
S23.Interworking unit 9 receives this first ATM cell 22, and by t time of delay
V24 up to time t
A25 will export begin postpone.Error variance t like this
R=t
V-(T
A-T
S)=0 is that this initial situation has been determined by required/actual value comparator 12 just.This value is sent to controller 13, the corresponding any correcting variable base 14 then of not exporting of the latter.The data of first ATM cell 22 that is output like this, by the data output end 10 of interworking unit 9 with the time base 14 also uncontrolled clock export as data stream segment 26.The data of the ATM cell 27 that is transfused to subsequently are added to the data stream segment of first ATM cell 22 without interruption as data stream segment 28.
Operative scenario promptly begins the reception and the output of ATM cell after the situation, and relevant controlling mechanism, is illustrated in Fig. 3.Time shaft 29 is illustrated in the sequential chart of the input 7 of input buffer 6.Time shaft 30 is illustrated in the sequential chart of the output of interworking unit 9.Interworking unit 9 is in time T
A (i)32 stop the output of the data 31 of cell (i-1) (not being illustrated), and the output of the data 33 of the next ATM cell (i) 34 that enters of beginning, and this cell has been ready in input buffer 6 and free mark T
S (i)35.Time mark T
S (i)35/actual value comparators 12 required by being sent to from interworking unit 9.Required/actual value comparator 12 comparison time mark T
S (i)35 with current time T
A (i)Difference between 32 (its difference is obtained by connecting 16 continuously by time base 14) and t time of delay that is forever stipulated
V24.t
R=t
V-(T
A-T
SThe error variance of) ≠ 0 is determined thus.Error variance t
RBe sent to controller 13 by connecting 18, controller obtains a correcting variable in view of the above, and this variable is by connecting 19 bases when being sent to, and the time base 14 clock frequency also be corrected.The situation of Fig. 3 explanation is, as the input of the ATM cell 34 that is delayed or the time base 14 at the result of the too high clock rate of its output, (T at interval
A-T
S) become≤t
V, error variance t like this
RJust become one on the occasion of.Therefore described control procedure just is set to a kind of like this mode, and in this case, base 14 was in the reduction of its output clock frequency when it caused.If the data of the ATM position 34 of ATM cell 34 will be subjected to this control as the data segment 33 in the data flow of the data output end 10 of interworking unit and export, then output will be terminated in the time 36.Result as control action is to have taken place to time T
A (i+1)37 displacement.Now for the output as the next ATM cell 38 of the data segment 39 of the data output end 10 of interworking unit 9, whole process is constantly repeated in the same way, time mark T
S (i+1)40 are assigned to new ATM cell 38.
Fig. 4 has illustrated an embodiment based on the control circuit of integral controller.Sequential Figure 41 of the input of input buffer 6 is illustrated.The ATM cell 42 of coming in is illustrated, and is omitted owing to the explanation of the different interval of 42 of each ATM cell of DTV.Sequential Figure 43 represents error variance t
R44, it is the time T separately
A (i)Determined by required/actual value comparator 12 and be sent to controller 13.Sequential Figure 45 is illustrated in the controller by error variance t
RThe symbol curve 46 that sequential Figure 43 of 44 obtains.The clock frequency of the output of base 14 when sequential Figure 47 represents.What also be illustrated is the size of required frequency, and it is equal to the time shaft of sequential Figure 47, the maximum 48 of permission, the minimum value 49 that allows and the actual value profile 50 of controlled influence.The integration of actual value profile 50 is-symbol curves 46, wherein the if symbol curve has one-1 value, then uses a correction signal with every time T by controller 13 by connecting 19
A (i)Be increased a step journey, or if symbol curve 46 there is one 1 value, then is reduced one at every turn and goes on foot journey.The size of the used step journey of the clock frequency of base 14 change during selection, making has enough the step journey of quantity greatly in the maximum 48 of clock frequency and the scope between the minimum value 49.Error variance be by the time frequency shift (FS) of clock of base 14 and this method of stack of DTV obtain.Owing to use the high stable oscillator of Δ f≤200ppm to make the frequency shift (FS) of clock very low, the single value of error variance utilizes DTV to determine basically.But,, utilize the relational expression ∑ DTV on the long-time relatively section because the ATM cell of transmitter side is carried with constant cell rate
iThe influence of=0 this error variance just has been eliminated.The size that the clock frequency of base 14 changes used step journey in the time of like this is not with regard to possible the frequency shift (FS) that is directed to clock and at compensating error variable t in an ATM cell is exported
RTo 0.Therefore, just produced will good control performance than the proportional controller of proofreading and correct DTV for the integral controller of evaluation symbol curve.
If ATM cell is to utilize UTOPIA (universal test of ATM and operating physical interface) to take place to the transmission of input buffer 6, then time t
SJust can be resultant from SOC (cell) signal.Time of delay t
VCan be set as very lowly, and can not cause that a large amount of cells are received as the ACR mode.Condition is t time of delay
VDetermine to be greater than the variation (propagation delay time migration) at the interval between two cells that are received that appear in the physics atm network.All be not used in the atm network of limiting value in an exchange and transmittability, this variation is little.Under the situation of practical application, condition is that for example, skew is less than the output time of an ATM cell, just exports so just in time to begin before second ATM cell is transfused to.
An acceptable shortcoming of this method is, the time mark T that is generated the recipient
SSequence the DTV that is added to above it is arranged.But, the control circuit clock frequency of just removing timing base 14 like this according to DTV.Therefore, actual frequency curve 50 has a fluctuation owing to DTV.Contrast therewith, the SRTS mode is not subjected to the influence of DTV.But, fluctuation relevant with control in the actual frequency curve here also can appear, because digital remainder error easily takes place RTS.As an instantaneous value, this also causes a trimming process and only just obtains average in the transmission of some.
The reference number table
1) atm network
2) interworking unit
3) input
4) output
5) transmission channel
6) input buffer
7) input
8) output
9) interworking unit
10) interworking unit output
11) signal output
12) required/actual value comparator
13) controller
14) the base time
15) connect
16) connect
17) connect
18) connect
19) connect
20) time shaft
21) time shaft
22) ATM cell
23) time mark T
S
24) time of delay T
V
25) time T
A
26) data stream segment
27) ATM cell
28) data stream segment
29) time shaft
30) time shaft
31) data
32)T
A(i)
33) data segment
34) ATM cell (i)
35) time mark T
S (i)
36) time
37) time T
A (i+1)
38) ATM cell
39) data segment
40) time mark T
S (i+1)
41) sequential chart
42) ATM cell
43) sequential chart
44) error variance t
R
45) sequential chart
46) symbol curve
47) sequential chart
48) maximum
49) minimum value
50) actual value profile diagram
Claims (5)
1. method that is used in ATM net (1), carrying out synchronous transmission with constant bit rate, wherein utilize one to comprise input buffer (6), interworking unit (9), the receiving equipment of Shi Ji (14) and controller (13), make the data flow of constant bit rate cross interworking unit (2) and be converted into atm cell stream, wherein at the transmitter square tube
A) ATM cell is being stored in the input buffer (6) the recipient after the transmission,
B) each in each ATM cell in the input buffer (6) all is endowed a time mark TS relevant with its time of reception,
C) be stored in output that the data in the ATM cell are carried out as data flow with constant bit rate by interworking unit (9) and start from the time T that postpones with respect to time of reception
A,
D) for this time of delay, a required value t
VBe prescribed the value t that this is required
VGreater than the transmission time skew DTV of the ATM cell from the transmitter to the receiver,
E) the actual delay time is by producing T
A-T
SDifference and determine,
F) error variance t
R=t
V-(T
A-T
S) produced, and be sent to controller (13),
G) controller (13) is according to error variance t
RProduce a correcting variable,
Base when h) correcting variable is sent to (14), and
The clock frequency of base in the time of i) (14) oppositely is adjusted with skew mutually according to correcting variable.
2. desired method in the claim 1 is characterized in that, controller 13 wherein is designed to an integral controller.
3. desired method in the claim 2 is characterized in that, controller 13 wherein is according to error variance t
RObtain value of symbol, and according to Δ f=-k ∑ (SIG
TA (i)) clock frequency of base (14) when adjusting.
A 4.ATM receiver station of network, comprise an input buffer, an interworking unit, base in the time of one, a required/actual value comparator and a controller, input buffer output is connected to an input of interworking unit in this station, an input of the value comparator of required/reality that an output of interworking unit is connected to, an output of required/actual value comparator is connected to an input of controller, an input of base when an output of controller is connected to, and the time base an output be connected to an input of interworking unit
An additional output of base in the time of wherein (14) is connected to an input of input buffer (6), and the time base (14) an additional output be connected to an input of required/actual value comparator (12).
5. desired receiver station in the claim (4) is characterized in that, its middle controller (13) is designed to an integral controller.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN97121213A CN1188359A (en) | 1996-10-24 | 1997-10-23 | Method for synchronizing transmissions at constant bit rate in ATM networks and circuit arrangement for carrying out the method |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| DE19644238.9 | 1996-10-24 | ||
| CN97121213A CN1188359A (en) | 1996-10-24 | 1997-10-23 | Method for synchronizing transmissions at constant bit rate in ATM networks and circuit arrangement for carrying out the method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1188359A true CN1188359A (en) | 1998-07-22 |
Family
ID=5176227
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN97121213A Pending CN1188359A (en) | 1996-10-24 | 1997-10-23 | Method for synchronizing transmissions at constant bit rate in ATM networks and circuit arrangement for carrying out the method |
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| Country | Link |
|---|---|
| CN (1) | CN1188359A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100401655C (en) * | 2002-03-25 | 2008-07-09 | 因芬尼昂技术股份公司 | Device and method for regulating a transmission moment of a continuous transmission signal |
| CN101820324A (en) * | 2010-04-30 | 2010-09-01 | 中兴通讯股份有限公司 | Synchronous transmission method and system for asynchronous data |
| CN108693821A (en) * | 2017-03-31 | 2018-10-23 | 欧姆龙株式会社 | control device, storage medium, control method and control system |
-
1997
- 1997-10-23 CN CN97121213A patent/CN1188359A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN100401655C (en) * | 2002-03-25 | 2008-07-09 | 因芬尼昂技术股份公司 | Device and method for regulating a transmission moment of a continuous transmission signal |
| CN101820324A (en) * | 2010-04-30 | 2010-09-01 | 中兴通讯股份有限公司 | Synchronous transmission method and system for asynchronous data |
| WO2011134251A1 (en) * | 2010-04-30 | 2011-11-03 | 中兴通讯股份有限公司 | Method and system for synchronously transmitting asynchronous data |
| US8675742B2 (en) | 2010-04-30 | 2014-03-18 | Zte Corporation | Method and system for synchronously transmitting asynchronous data |
| CN101820324B (en) * | 2010-04-30 | 2014-04-09 | 中兴通讯股份有限公司 | Synchronous transmission method and system for asynchronous data |
| CN108693821A (en) * | 2017-03-31 | 2018-10-23 | 欧姆龙株式会社 | control device, storage medium, control method and control system |
| US10908579B2 (en) | 2017-03-31 | 2021-02-02 | Omron Corporation | Controller, control program, and control system |
| CN108693821B (en) * | 2017-03-31 | 2021-11-05 | 欧姆龙株式会社 | Control device, storage medium, control method, and control system |
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