CN1186971A - Counter clock correcting method for plate video frenquency display - Google Patents
Counter clock correcting method for plate video frenquency display Download PDFInfo
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- CN1186971A CN1186971A CN96121319A CN96121319A CN1186971A CN 1186971 A CN1186971 A CN 1186971A CN 96121319 A CN96121319 A CN 96121319A CN 96121319 A CN96121319 A CN 96121319A CN 1186971 A CN1186971 A CN 1186971A
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Abstract
The driving circuit of the invented method is simple, which lowers the crowded degree of the driving circuit, thus the reliability of the circuit is improved and the quality of image displaying is heightened. For implementing the above mentioned object, the present invention adopts a kind of method for correcting the periodic nonuniform counter clock, i. e. the periodic non uniform clock producer produces n pulses in T. period, their spaces are nonuniform and coincide with the gama inverse correcting function. n counting values according with the n grade of gradation of the reverse correcting function are feteched as the clock input of pulse width counter of perodic nonuniform pulse series. The video frequency plate display is conducted by partitioned row by row scanning. The method adopted by said invention brings forth new ideas of the column driving method.
Description
The present invention relates to a kind of dull and stereotyped video display circuit Driving technique.
The width modulation method of one of circuit drive method that dull and stereotyped video shows is to obtain display gray scale by the time of controlling the constant current lead-through.Because this method is applicable to the design and the realization of digital circuit, uses comparatively extensively.
The width modulation method also is being divided into several schemes in concrete the application: scanning adds the scheme that latchs, pulsewidth counting modulation scheme etc. as timeslice.Wherein the know-why of pulsewidth counting modulator approach can be summarized as follows:
In general, the image that dull and stereotyped video shows is made up of the cell array with different grey-scale, and when showing each frame image, the detailed process of demonstration is lined by line scan by subregion and carried out., suppose that every domain scanning line number is N herein, the displaying time of every frame is T
S, the displaying time of every row is T
L, comprising complete black gray scale, number of greyscale levels is n, the data value of pixel gray level is m.The demonstration time of so every row is T
L=T
S/ N.Like this, the brightest this pixel ON time that is meant of pixel is T
L, the gray level m of certain pixel between 0 and n-1 between (0≤m≤n-1), its ON time is mT
L/ (n-1) (0≤mT
L/ (n-1)≤T
L).At each T
LBefore, the display message data of this journey are latched into gray level width modulation counter by the serial-shift device, and the maximum count value of this counter is n-1, and actual loaded value is m, from T
LRise the zero hour, to the cycle be T
L/ (n-1) even clock is counted, and finishes when counting m, and formed pulsewidth is the needed ON time mT of this pixel during this
L/ (n-1).By that analogy, the pixel on 1～N is capable all correctly shows this video image according to the pictorial data of this frame local area, and other district is identical therewith, and the video of so just finishing a frame image shows; At next T
SThen the pictorial data with next frame shows on panel video display, and such process constantly repeats, and just can realize correctly that dull and stereotyped video shows.In said process, the video image that flat-panel monitor has been finished the even gray-level difference of n level shows, but this drive system faces following problem in actual applications:
The practical video eikongen is at the system design that is display device with CRT, has carried out γ and has proofreaied and correct, and therefore has the display device of linear characteristic to carry out system that image shows for apparatus and need carry out that γ is counter proofreaies and correct.Now general way is to insert before giving drive circuit grey scale signal that γ is counter to be proofreaied and correct.In fact, the anti-correction of γ is a funtcional relationship f, and it is used for driving circuit after with the grey scale signal conversion goes to show, i.e. m '=f (m); The problem of bringing simultaneously is the minimizing of display gray scale level, because what driving circuit adopted is the modulation of digitized pulsewidth counting, it has the even gray scale of n level, and do not possess original homogeneity through the m ' after the f conversion, therefore can't keep original corresponding relation, thereby the consequence of bringing is in the m ' value after the digitizing many identical values to be arranged, although their initial value m are different.Like this, the different grey-scale in the image forms same display brightness at screen.For guaranteeing not reduce number of greyscale levels, the solution that prior art adopts is non-one by one corresponding (value of taking out) look-up table, this method is overlapping for fear of m ' value, improved the number of greyscale levels that drive circuit can produce, just increase the count enable scope n value of the modulation counter of unit pixel, the number of greyscale levels that makes it to show is than original greatly increasing, be made as n ' (need to prove here since the counter that adopts with binary mode work, so the n value of speaking of previously is generally 2 power side, i.e. n=2
i, i is positive integer) if the original n value that adopts is 2
j(j is positive integer) is 2 and increase later number of greyscale levels n '
k(k is positive integer), that is to say and change original j digit counter into k digit counter (k＞j), so original gray scale value m can find respective value through the later functional value m ' digital value of f conversion in 0～n '-1, its Duplication reduces with the increase of k, even can reach 0, through calculating, its Duplication reaches 0 k=2j when namely keeping the correct gray level of n level of image, that is to say that the pulsewidth modulation number of counter bits doubles, make like this m ' but span is expanded as n '=n from n
2Table look-up by the value of taking out, drive circuit may be from n according to the n kind of the data of input
2But in the individual value, take out assurance and meet n count value of the anti-correction function of γ as the pulse width modulation values of this n level gray scale, thereby improved the quality of visual demonstration.It more than is exactly the basal conditions of present dull and stereotyped video display driver technology.
The dull and stereotyped video image display packing of prior art realizes that the image of n level gray scale shows that having adopted count range is n
2Digit counter (2j digit counter) and tabling look-up and the logical operation device of addressing at a high speed, caused like this display driver circuit too intensive, the hardware speed of the processing of Visual Display Data is very high, has strengthened the difficulty and the cost that manufacture and design.
The purpose of this invention is to provide the counter clock correcting method that a kind of dull and stereotyped video shows, the driving circuit of this method is simple, has reduced the dense degree of driving circuit, and the reliability of circuit is improved, the quality height that image shows.
For achieving the above object, the present invention adopts the non-homogeneous counter clock correcting method of a kind of periodicity, namely uses periodicity non-uniform clock generator at a T
LProduce n pulse in cycle, their interval is non-homogeneous and meets the anti-correction function of γ, that is to say in said n
2But in the individual value, take out the count value of n n level gray scale that guarantees to meet the anti-correction function of γ as the clock input of periodicity non-uniform impulse train as the pulsewidth counter.
Because dull and stereotyped video requires the gray-scale displayed number of stages to be still n after being presented at the anti-correction of γ, gray scale value m ' is from n after the not overcorrect
2But extract in the value.At a T
LThe counter that is 0～n-1 with original maximum count scope in cycle produces n the m ' gray value after the correction, namely at a T
LWith non-uniform impulse train control pulsewidth modulation counter, make it can produce corresponding n the accurate pulse width after the correction to n m count value in cycle, finishing prior art employing maximum count scope is 0～n
2The demonstration n level that-1 counter just can be finished meets the anti-function of proofreading and correct gray level of γ.Sequential chart when Fig. 1 is n=8 level gray scale.A is T among Fig. 1
L8 equally spaced pulse trains in cycle expand most n by the anti-alignment requirements of γ
2=64 uniformly-spaced pulse train b extracts n (8) and meets the pulse train c of the anti-correction function of γ as the input clock of pulsewidth modulation counter from b.The present invention has only finished the work that prior art 2j=6 digit counter just can be finished with the j=3 digit counter like this.Figure 2 shows that periodically non-uniform clock generator.Wherein 1 is the 2j digit counter, and it is made up of 2j d type flip flop, output terminal Qi of each d type flip flop control, and such 1 has 2j output terminal Q
2jQ
2j-1Q
2Q
1For the m ' value after guaranteeing to proofread and correct does not overlap, at T
LGive this 2j digit counter 1 input n in cycle
2Individual uniformly-spaced pulse all produces one group of output Q for each pulse 2j digit counter 1
2jQ
2j-1Q
2Q
1, these are exported through code translator 2-1,2-2,2-3 ... 2-n produces n pulse of m ' value, and warp or door 3 form the periodically sequence of a n heterogeneous pulse, and the recurrent interval of this sequence meets the anti-correction function of γ.The concrete production process of this pulse train is as follows: in Fig. 1, set n=8, thus j=3,2j=6,1 of the 2j digit counter among Fig. 2 is 6 digit counters, it is output as Q
6Q
5Q
4Q
3Q
2Q
1, decoder is 8, is respectively 2-1,2-2 ... 2-8; As among Fig. 1 shown in the b, at T
LGive 6 digit counters 1 input n in cycle
2=64 uniformly-spaced pulses, the output Q of generation
6Q
5Q
4Q
3Q
2Q
1Enter decoder, each decoder produces corresponding pulse output to the input that meets the anti-corrected value of its γ respectively, such as 2-1 to Q
6Q
5Q
4Q
3Q
2Q
1The input of=000000 (B) produces an output pulse, and 2-2 is to Q
6Q
5Q
4Q
3Q
2Q
1The input of=000001 (B) produces an output pulse, and 2-3 is to Q
6Q
5Q
4Q
3Q
2Q
1The input of=000100 (B) produces an output pulse ... 2-8 is to Q
6Q
5Q
4Q
3Q
2Q
1The input of=111111 (B) produces an output pulse, and warp or door 3 form the periodically sequence of a n=8 heterogeneous pulse, and the pulse spacing of this sequence is 0,1,4,10,18,30,45,63 shown in c among Fig. 1.The front is mentioned, and γ is anti-when proofreading and correct gray level m ' and not overlapping guaranteeing to meet, m ' but span must be expanded as n '=n from n
2, pulse number is at least n therefore to import uniformly-spaced for counter 1
2Certainly, import uniformly-spaced pulse number greater than n
2The time, also can guarantee to meet anti-n the gray level m ' that proofreaies and correct of γ and not overlap.
The front is spoken of dull and stereotyped video and is shown generally to line by line scan by subregion and carry out, and the method that the present invention adopts mainly is that the driving method at column direction has carried out a kind of innovation.In addition, method set forth in the present invention can also be used for the driving of line direction; Because showing also, dull and stereotyped video can be undertaken by column scan by subregion, identical with the said principle in front, suppose that every domain scanning columns is M, and the demonstration time of every frame is T
S, the demonstration time of every row is T
C, comprising complete black gray scale, number of greyscale levels is n, the data value of pixel gray level is m.The demonstration time of so every row is T
C=T
S/ M.Like this, at each T
CBefore, the display message data of these row are latched into gray level width modulation counter by the serial-shift device, and the maximum count value of this counter is n-1, and actual loaded value is m, from T
CRise the zero hour, to the cycle be T
C/ (n-1) even clock is counted, and finishes when counting m, and formed pulsewidth is the needed ON time mT of this pixel during this
C/ (n-1).By that analogy, the pixel that 1～M lists all correctly shows this video image according to the pictorial data of this frame local area, and other district is identical therewith, and the video of so just finishing a frame image shows; So the present invention adopts and can the driving method of line direction be improved with quadrat method, guarantees the simplification with its line direction driving circuit.In sum, the present invention adopts the non-homogeneous counter clock of periodicity both to can be used for the FPD row and drives, and can be listed as driving again.
The invention will be further described now to provide embodiment and accompanying drawing.
Embodiment one: monochromatic dull and stereotyped video display screen
Fig. 3 is the synoptic diagram of embodiment one, and 4 is controller among the figure, and 5 is the non-homogeneous counting generator of periodicity, 6,7 is shift register, and 8,9 are the width modulation counter, and 10,11 is pulse width register, 12,13 is row driver, and 14 is line driver, and 15 is display screen.Its course of work is summarized as follows: at first controller 4 moves into shift register 6,7 by e with pictorial data d, after finishing displacement, controller 4 through f with shift register 6, the 7 gray-scale datas width modulation counter 8,9 of packing into, at a certain T
LCycle, controller 4 was imported pulse width register 10,11 start-up period non-uniform clock generator 5 simultaneously by g constantly with 0 of pulsewidth when beginning, and 4 pairs of line drivers 14 of controller are controlled, and make it to choose on display screen 15 a certain every trade of advancing to drive; Simultaneously under the control of controller 4, periodically non-uniform clock generator 5 is not to resemble to produce uniform T the existing mode in this
L/ (n-1) or T
L/ (n
2-1) uniform pulse clock control counter, input to width modulation counter 8,9 through h and carry out the width modulation counting but produce the non-homogeneous pulse train meet the anti-correction function of γ, when width modulation counter 8,9 reaches count value respectively, difference control register 10,11, the pulse width signal of register 10,11 outputs is listed as driving through 12,13 pairs of display screens 15 of row driver, reaches the purpose of gray-scale Control.
Embodiment two: the dull and stereotyped video display screen of dual base color
Fig. 4 is embodiment two synoptic diagram, 16 is controller among the figure, 17 is the periodicity non-uniform clock generator of wherein a kind of primary colours, 18 is the periodicity non-uniform clock generator of another kind of primary colours, 19,20 is a kind of data shift register of primary colours wherein, 21,22 is the data shift register of another kind of primary colours, 23,24 is the width modulation counter of wherein a kind of primary colours, 25,26 is the width modulation counter of another kind of primary colours, 27,28 is a kind of pulse width register of primary colours wherein, 29,30 is the pulse width register of another kind of primary colours, 31,32 is a kind of row driver of primary colours wherein, 33,34 is the row driver of another kind of primary colours, and 35 is line driver, and 36 is display screen.Its course of work is summarized as follows: at first controller 16 moves into a kind of primary colours data shift register 19,20 and another kind of primary colours data shift register 21,22 by k respectively with dual base color data i, the j of image, after finishing data shift, controller 16 is through 1 with pack into the width modulation counter 23,24 of these primary colours of these gradation level data in a kind of primary colours data shift register 19,20, with pack into the width modulation counter 25,26 of these primary colours of the gradation level data in the another kind of primary colours data shift register 21,22; At a certain T
LCycle is when beginning, controller 16 by p 0 of pulsewidth is imported a kind of pulse width register 27,28 of primary colours constantly and the pulse width register 29,30 of another kind of primary colours starts a kind of primary colours periodically non-uniform clock generator 17 and another kind of primary colours periodicity non-uniform clock generator 18 simultaneously, 16 pairs of line drivers 35 of controller are controlled, and make it to choose on display screen 36 a certain every trade of advancing to drive; Simultaneously under the control of controller 16, a kind of periodicity non-uniform clock generator 17 of primary colours is not to resemble to produce uniform T the existing mode in this
L/ (n-1) or T
L/ (n
2-1) uniform pulse clock control counter, input to Ben Jise width modulation counter 23,24 through p1 and carry out the width modulation counting but produce the non-homogeneous pulse train meet the anti-correction function of Ben Jise γ, when this primary colours width modulation counter 23,24 reaches count value, the Ben Jise pulse-width controlled that resets respectively register 27,28, the pulse width signal of Ben Jise pulse-width controlled register 27,28 outputs drives through the row that 31,32 pairs of display screens 36 of Ben Jise row driver carry out Ben Jise; The periodicity non-uniform clock generator 18 of another kind of primary colours is same to be produced the non-homogeneous pulse train that meets the anti-correction function of Ben Jise γ and inputs to Ben Jise width modulation counter 25,26 through p2 and carry out the width modulation counting, when this primary colours width modulation counter 25,26 reaches count value respectively, the primary colours pulse-width controlled that resets respectively register 29,30, the pulse width signal of Ben Jise pulse-width controlled register 29,30 outputs drives through the row that 33,34 pairs of display screens 36 of Ben Jise row driver carry out Ben Jise.
Embodiment three: the dull and stereotyped video display screen of three primary colours
Fig. 5 is embodiment three synoptic diagram, 37 is controller among the figure, 38 is red periodicity non-uniform clock generator, 39 is green periodicity non-uniform clock generator, 40 is blue periodicity non-uniform clock generator, 41,42 is red data shift register, 43,44 is green data shift register, 45,46 is blue data shift register, 47,48 is red width modulation counter, 49,50 is green width modulation counter, 51,52 is blue width modulation counter, 53,54 is red pulse width register, 55,56 is green pulse width register, 57,58 is blue pulse width register, 59,60 is red row driver, 61,62 is green row driver, 63,64 is the blue moving device of row, 65 is line driver, and 66 is display screen.Its course of work is summarized as follows: at first controller 37 moves into three primary colours data shift register 41,42 separately by t respectively with three primary colours data r, q, the s of image, 43,44 and 45,46, after finishing data shift, controller 37 through u with each primary colours data shift register 41,42,43, the width modulation counter 47,48,49,50 and 51,52 of corresponding primary colours of packing into of the corresponding base color shade level data in 44 and 45,46; At a certain T
LCycle is when beginning, the pulse width register 53,54 of each primary colours imported 0 of pulsewidth constantly by controller 37 by v, 55,56 and 57,58, start periodically non-uniform clock generator 38,39 and 40 of each primary colours simultaneously, 37 pairs of line drivers 65 of controller are controlled, and make it to choose on display screen 66 a certain every trade of advancing to drive; In this simultaneously under the control of controller 37, the periodicity non-uniform clock generator 38 of each primary colours, 39 and 40 produce the non-homogeneous pulse train that meets the anti-correction function of Ben Jise γ respectively, through w, x and y input to each primary colours width modulation counter 47,48,49,50 and 51,52 carry out the width modulation counting, at each primary colours width modulation counter 47,48,49,50 and 51,52 when reaching count value, the Ben Jise pulse-width controlled that resets respectively register 53,54,55,56 and 57,58, each primary colours pulse-width controlled register 53,54,55,56 and 57, the pulse width signal of 58 outputs is through Ben Jise row driver 59,60,61,62 and 63,64 pairs of display screens 66 carry out the row driving of each primary colours, reach the purpose of full color gray-scale Control.
Claims (2)
1. counter clock correcting method that dull and stereotyped video shows, it is characterized in that adopting the periodicity non-uniform impulse train as counter clock, periodically the non-uniform clock generator produces the counting input that the pulse train of a non-uniform spacing is the pulsewidth counter in one-period:
-in a time cycle, give a power uniformly-spaced pulse of 2 of counter input gray grade, all produce one group of output Qi for each pulse digit counter;
---these outputs become the input of decoder, and decoder produces corresponding pulse output according to the anti-correction function numerical value of γ for meeting the anti-input of proofreading and correct of γ;
---the output warp or the door 3 of code translator form the periodically sequence of a n heterogeneous pulse, and the recurrent interval of this sequence meets the anti-correction function of γ.
2, the counter clock correcting method of a kind of dull and stereotyped video demonstration according to claim 1, it is characterized in that adopting periodically, non-homogeneous counter clock carries out the driving of FPD row, row driving.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96121319A CN1186971A (en) | 1996-12-28 | 1996-12-28 | Counter clock correcting method for plate video frenquency display |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN96121319A CN1186971A (en) | 1996-12-28 | 1996-12-28 | Counter clock correcting method for plate video frenquency display |
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| Publication Number | Publication Date |
|---|---|
| CN1186971A true CN1186971A (en) | 1998-07-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN96121319A Pending CN1186971A (en) | 1996-12-28 | 1996-12-28 | Counter clock correcting method for plate video frenquency display |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7948079B2 (en) | 2006-12-06 | 2011-05-24 | Princo Corp. | Method of manufacturing hybrid structure of multi-layer substrates and hybrid structure thereof |
| US8014164B2 (en) | 2006-12-06 | 2011-09-06 | Princo Corp. | Hybrid structure of multi-layer substrates and manufacture method thereof |
-
1996
- 1996-12-28 CN CN96121319A patent/CN1186971A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7948079B2 (en) | 2006-12-06 | 2011-05-24 | Princo Corp. | Method of manufacturing hybrid structure of multi-layer substrates and hybrid structure thereof |
| US8014164B2 (en) | 2006-12-06 | 2011-09-06 | Princo Corp. | Hybrid structure of multi-layer substrates and manufacture method thereof |
| US8111519B2 (en) | 2006-12-06 | 2012-02-07 | Princo Corp. | Hybrid structure of multi-layer substrates and manufacture method thereof |
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