CN118358259A

CN118358259A - Ink jet head and ink jet printer

Info

Publication number: CN118358259A
Application number: CN202311354892.0A
Authority: CN
Inventors: 日吉光幸
Original assignee: Toshiba TEC Corp
Current assignee: Toshiba TEC Corp
Priority date: 2023-01-19
Filing date: 2023-10-18
Publication date: 2024-07-19
Also published as: JP2024102635A; EP4403364A1

Abstract

An object of the present disclosure is to provide an inkjet head and an inkjet printer with high safety. According to an embodiment, an inkjet head includes a driver IC, a logic power supply circuit, and a first diode. The driver IC includes a logic circuit and a level shifter. The logic power supply circuit supplies a voltage to the logic circuit after inputting a first voltage to the power supply input terminal. The first diode connects an anode to a second voltage input to the level shifter and connects a cathode to a power input terminal of the logic power circuit.

Description

Ink jet head and ink jet printer

Technical Field

Embodiments of the present invention relate to an inkjet head and an inkjet printer.

Background

An inkjet printer that forms an image on a print medium based on print data has been put to practical use. An inkjet printer includes, for example, an inkjet head and a head controller that controls the inkjet head.

The inkjet head includes an actuator for ejecting ink and a driver IC for driving the actuator based on control of a head controller.

The head controller supplies a plurality of power supply voltages to a driver IC of the inkjet head. The head controller performs switching-on and switching-off of a plurality of power supply voltages based on a predetermined sequence. Thus, the head controller prevents the through current from flowing in the driver IC.

However, even if the head controller performs switching on and off of the plurality of power supply voltages in a predetermined order, if there is a connection failure in the wiring connecting the head controller and the driver IC, the order of switching on the power supply voltages supplied to the driver IC does not correspond to the predetermined order.

In order to cope with such a phenomenon, a technique is provided in which a signal line for supplying a control signal to a driver IC is connected to supply electric power.

Conventionally, when the control signal is not at a high level, there is a case where a power supply voltage to the driver IC cannot be ensured.

Disclosure of Invention

Problems to be solved by the invention

In order to solve the above problems, an object is to provide an inkjet head and an inkjet printer having high safety.

Solution for solving the problem

According to an embodiment, an inkjet head includes a driver IC, a logic power supply circuit, and a first diode. The driver IC includes a logic circuit and a level shifter. The logic power supply circuit supplies a voltage to the logic circuit after inputting a first voltage to the power supply input terminal. The first diode connects the anode to the second voltage input to the level shifter and connects the cathode to the power input terminal of the logic power circuit.

Drawings

Fig. 1 is a block diagram showing an example of the structure of an inkjet printer according to the embodiment.

Fig. 2 is a circuit diagram conceptually illustrating a configuration example of an inkjet head and a head controller according to an embodiment.

Fig. 3 is a circuit diagram illustrating a configuration example of a recovery circuit according to the embodiment.

Fig. 4 is a diagram showing a configuration example of a driver IC according to the embodiment.

Fig. 5 is a timing chart for explaining the normal operation of the head controller and the inkjet head according to the embodiment.

Fig. 6 is a timing chart for explaining the normal operation of the head controller and the inkjet head according to the embodiment.

Fig. 7 is a timing chart for explaining an operation at the time of abnormality of the head controller and the inkjet head according to the embodiment.

Fig. 8 is a timing chart for explaining an operation at the time of abnormality of the head controller and the inkjet head according to the embodiment.

Symbol description

1. An inkjet printer; 11. a CPU; 12. a ROM; 13. a RAM; 14. a communication interface; 15. a display; 16. an operation unit; 17. a conveying motor; 18. a motor driving circuit; 19. a pump; 20. a pump driving circuit; 21. an ink jet head; 22. a head controller; 23. a power supply circuit; 31. transmitting the FPC; 32. a power supply voltage generator; 33. a power supply timing circuit; 34. a first communication interface; 35. a control IC; 36. a second communication interface; 41. a channel group; 42. a communication interface; 43. a buffer IC; 44. a logic supply voltage generator; 45. a driver IC; 46. a recovery circuit; 47. a head substrate; 50. an electrode group; 51. a logic circuit; 52. a level shifter; 53. a driver; 61. a first diode; 62. a resistor; 63. a zener diode; 64. a second diode; 70. the connection point.

Detailed Description

The embodiments are described below with reference to the drawings.

An inkjet printer and an inkjet head according to an embodiment are described below with reference to the drawings.

First, an inkjet printer 1 according to an embodiment will be described. Fig. 1 is an explanatory diagram showing an example of the structure of an inkjet printer 1 according to one embodiment.

The inkjet printer 1 is an example of an inkjet recording apparatus. The inkjet recording apparatus is not limited to this, and may be another apparatus such as a copier.

The inkjet printer 1 performs various processes such as image formation while conveying a printing medium as a recording medium, for example. The inkjet printer 1 includes a CPU (Central Processing Unit: central processing unit) 11, a ROM (Read Only Memory) 12, a RAM (Random Access Memory: random access Memory) 13, a communication interface 14, a display 15, an operation section 16, a conveyance motor 17, a motor drive circuit 18, a pump 19, a pump drive circuit 20, an inkjet head 21, a head controller 22, and a power supply circuit 23. The inkjet printer 1 further includes a paper feed cassette and a paper discharge tray, not shown.

The CPU11 is an arithmetic element (e.g., a processor) that performs arithmetic processing. The CPU11 performs various processes based on data such as programs stored in the ROM 12. The CPU11 functions as a control unit capable of executing various operations by executing a program stored in the ROM 12.

The ROM12 is a read-only nonvolatile memory. The ROM12 stores programs, data used by the programs, and the like.

The RAM13 is a volatile memory functioning as a working memory. The RAM13 temporarily stores data and the like being processed by the CPU 11. The RAM13 temporarily stores programs executed by the CPU 11.

The communication interface 14 is an interface for communicating with other devices. The communication interface 14 is used for communication with, for example, a host device that transmits a print instruction to the inkjet printer 1. The communication interface 14 may be an interface for performing wireless communication with other devices according to specifications such as Bluetooth (registered trademark) and Wi-fi (registered trademark).

The display 15 is a display device that displays a screen based on a video signal input from a display control unit such as the CPU11 or a graphic controller not shown. For example, a setting screen of the inkjet printer 1 is displayed on the display 15.

The operation unit 16 generates an operation signal based on the operation. The operation unit 16 is, for example, a touch sensor, a numeric key, a power key, a paper feed key, various function keys, a keyboard, or the like. The touch sensor is, for example, a resistive film type touch sensor, a capacitive touch sensor, or the like. The touch sensor acquires information indicating a specified position in a certain area. The touch sensor is integrally configured as a touch panel with the display 15, and generates a signal indicating a touched position on a screen displayed on the display 15.

The conveyance motor 17 rotates to operate a conveyance member of a conveyance path, not shown, for conveying the print medium. The conveying member is a belt, a roller, a guide, or the like that conveys the printing medium. The conveyance motor 17 drives a roller that operates in conjunction with a belt that holds the print medium, thereby conveying the print medium along the guide.

The motor drive circuit 18 is a circuit that drives the conveyance motor 17. The motor drive circuit 18 drives the conveyance motor 17 in accordance with a conveyance control signal input from the CPU11, thereby conveying the print medium of the paper feed cassette to the paper discharge tray via the inkjet head 21. The paper feed cassette is a cassette that accommodates a plurality of printing media. The discharge tray accommodates a printing medium discharged after an image is formed by the inkjet printer 1.

The pump 19 includes, for example, a tube that communicates an ink tank (not shown) holding ink with the inkjet head 21. Specifically, the tube communicates with a common ink chamber, not shown, of the inkjet head 21.

The pump driving circuit 20 drives the pump 19 in accordance with the ink supply control signal input from the CPU11, so that the ink in the ink tank is supplied to the common ink chamber of the inkjet head 21.

The inkjet head 21 is an image forming portion that forms an image on a printing medium. The inkjet head 21 forms an image by ejecting ink to a printing medium conveyed by the conveying motor 17 and a holding roller, not shown, based on a power supply voltage and a control signal supplied from the head controller 22. The inkjet printer 1 may include a plurality of inkjet heads 21 corresponding to respective colors such as cyan, magenta, yellow, and black, for example.

The head controller 22 is a circuit that controls the inkjet head 21. The head controller 22 causes the inkjet head 21 to operate, thereby ejecting ink from the inkjet head 21. The head controller 22 supplies a plurality of power supply voltages to the inkjet heads 21. In addition, the head controller 22 generates a control signal based on a print instruction input via the communication interface 14. The head controller 22 forms an image on the print medium with the inkjet head 21 by supplying a power supply voltage and a control signal.

The power supply circuit 23 converts ac power supplied from a commercial power supply into dc power. The power supply circuit 23 supplies dc power to each component in the inkjet printer 1.

Fig. 2 is an explanatory diagram for explaining detailed configurations of the inkjet head 21 and the head controller 22. The inkjet head 21 and the head controller 22 are connected via a Flexible Printed Circuit (FPC) board for transfer (hereinafter referred to as a transfer FPC 31). Thus, the head controller 22 can supply the power supply voltage and the control signal to the inkjet head 21.

First, the head controller 22 is explained.

The head controller 22 includes a power supply voltage generator 32, a power supply timing circuit 33, a first communication interface 34, a control IC35, and a second communication interface 36.

The power supply voltage generator 32 generates a plurality of power supply voltages necessary for the operation of the inkjet head 21 and a power supply voltage necessary for the operation of the control IC35 using the dc voltage DCV supplied from the power supply circuit 23. The dc voltage DCV is, for example, 39V.

For example, the power supply voltage generator 32 generates a power supply voltage VAA-IN, a power supply voltage VCC-IN, a power supply voltage VDD-IN, and a power supply voltage VDD-LOG using a DC voltage DCV. The power supply voltage VAA-IN is a power supply voltage for generating the power supply voltage VAA used IN the inkjet head 21. The supply voltage VAA-IN is, for example, 20V. The power supply voltage VCC-IN is a power supply voltage for generating the power supply voltage VCC used IN the inkjet head 21. The supply voltage VCC-IN is, for example, 39V. The power supply voltage VDD-IN is a power supply voltage for generating the power supply voltage VDD used IN the inkjet head 21. The power supply voltage VDD-IN is, for example, 5V. The power supply voltage VDD-LOG is a power supply voltage for operating the control IC 35. The power supply voltage VDD-LOG is, for example, 5V.

The power supply voltage generator 32 supplies the power supply voltage VAA-IN, the power supply voltage VCC-IN, and the power supply voltage VDD-IN to the power supply timing circuit 33. In addition, the power supply voltage generator 32 supplies the power supply voltage VDD-LOG to the control IC35.

The power supply timing circuit 33 switches on and off the respective power supply voltages to the inkjet heads 21. The power supply timing circuit 33 switches on and off the respective power supply voltages to the inkjet heads 21 in the case of the enabled state. In addition, in the case of the prohibition state, the power supply timing circuit 33 does not switch on or off the respective power supply voltages. The power supply timing circuit 33 switches the enable state and the disable state based on the control of the control IC 35.

The power supply timing circuit 33 outputs the power supply voltage VAA, the power supply voltage VCC (second voltage), and the power supply voltage VDD (first voltage) to the inkjet head 21 based on the power supply voltage VAA-IN, the power supply voltage VCC-IN, and the power supply voltage VDD-IN supplied from the power supply voltage generator 32.

The power supply timing circuit 33 starts (switches on) the output of each power supply voltage based on a predetermined sequence (timing). The power supply timing circuit 33 stops (cuts off) the output of each power supply voltage based on a predetermined sequence (timing). The power supply timing circuit 33 is connected to the power supply voltage in the order of the power supply voltage VDD, the power supply voltage VCC, and the power supply voltage VAA at the time of power supply connection. The power supply timing circuit 33 cuts off the power supply voltage in the order of the power supply voltage VAA, the power supply voltage VCC, and the power supply voltage VDD when the power supply is cut off.

The first communication interface 34 is an interface that connects the CPU11 or the communication interface 14 with the control IC. The print command input to the first communication interface 34 from the host device or the CPU11 connected via the communication interface 14 is supplied to the control IC35.

The control IC35 operates by the power supply voltage VDD-LOG. The control IC35 generates a control signal based on the print instruction input via the first communication interface 34. The control signals include a clock signal CK, a reset signal RST, an initialization signal INIT, print data SDI, and the like. The control IC35 outputs a control signal to the inkjet head 21 via the transmission FPC 31.

In addition, the control IC35 generates a switching signal VOL-SW for switching the operation of the power supply timing circuit 33 in the enabled state and the disabled state. The control IC35 inputs the switching signals VOL to SW to the power supply timing circuit 33, thereby switching the operation of the power supply timing circuit 33 between the enabled state and the disabled state. For example, when the control IC35 receives the supply of the power supply voltage VDD-LOG and starts the supply, the control IC switches the operation of the power supply timing circuit 33 to the enabled state. When receiving a predetermined signal from the CPU11, the control IC35 switches the operation of the power supply timing circuit 33 to the disabled state.

The second communication interface 36 is an interface connecting the inkjet head 21 and the head controller 22. The second communication interface 36 includes various terminals to which the transmission FPC31 is connected.

For example, the second communication interface 36 includes: 4 terminals connected to the output terminal of the power supply voltage VAA of the power supply timing circuit 33, 2 terminals connected to the output terminal of the power supply voltage VCC of the power supply timing circuit 33, and1 terminal connected to the output terminal of the power supply voltage VDD of the power supply timing circuit 33. The second communication interface 36 includes: 1 terminal connected to the output terminal of the clock signal CK of the control IC35, 1 terminal connected to the output terminal of the reset signal RST of the control IC35, 1 terminal connected to the output terminal of the initialization signal INIT of the control IC35, and1 terminal connected to the output terminal of the print data SDI of the control IC 35. In addition, the second communication interface 36 has 7 terminals that are grounded. The transmission FPC31 also includes a plurality of wirings connected to the respective terminals of the second communication interface 36.

The power supply voltage VAA, the power supply voltage VCC, and the power supply voltage VDD output from the power supply timing circuit 33, and the clock signal CK, the reset signal RST, the initialization signal INIT, and the print data SDI output from the control IC35 are supplied to the inkjet head 21 connected via the second communication interface 36 and the transfer FPC 31.

The number of terminals provided in the second communication interface 36 and the number of wires (the number of cores) for transmitting the FPC31 can be determined based on the current consumption in the inkjet head 21, and are not limited to the above number. That is, the number of terminals and wirings may be appropriately changed according to the specifications of the inkjet head 21 and the head controller 22.

Next, the inkjet head 21 is described.

The inkjet head 21 includes a channel group 41, a communication interface 42, a logic power supply voltage generator 44, a driver IC45, a recovery circuit 46, a head substrate 47, and an electrode group 50. The channel group 41, the communication interface 42, the logic power supply voltage generator 44, the driver IC45, the recovery circuit 46, and the electrode group 50 are mounted on the head substrate 47.

Fig. 3 is a circuit diagram showing an exemplary configuration of the recovery circuit 46. As shown in fig. 3, the recovery circuit 46 includes a buffer IC43, a first diode 61, a resistor 62, a zener diode 63, and a second diode 64.

The channel group 41 is a member that ejects ink. The channel group 41 is constituted by arranging a plurality of channels for ejecting ink in accordance with the applied voltage. The channel group 41 includes a first piezoelectric member bonded to the head substrate 47, a second piezoelectric member bonded to the first piezoelectric member, a plurality of electrodes, and a nozzle plate.

The first piezoelectric member and the second piezoelectric member are bonded in such a manner that polarization directions are opposite to each other. A plurality of parallel grooves are formed in the first piezoelectric member and the second piezoelectric member from the second piezoelectric member side to the first piezoelectric member. In addition, electrodes are formed for each groove. The first piezoelectric member and the second piezoelectric member sandwiched by 2 electrodes formed in 2 grooves are configured as actuators deformed by a potential difference of the 2 electrodes.

The nozzle plate is a member that seals the slot. The nozzle plate is formed with a plurality of ejection nozzles for communicating the grooves with the outside of the inkjet head 21 for each groove. The groove sealed by the nozzle plate functions as a pressure chamber filled with ink by the pump 19 and the wall is constituted by 1 pair of actuators.

When a driving waveform is input from the driver IC45 to the electrode of the actuator constituting the wall of the pressure chamber, the actuator is deformed, and the volume of the pressure chamber is changed. Thereby, the pressure in the pressure chamber changes, and the ink in the pressure chamber is ejected from the ejection nozzle. In this example, the combination of the pressure chamber and the discharge nozzle is referred to as a channel. That is, the channel group 41 includes channels corresponding to the number of grooves.

The communication interface 42 is an interface that connects the inkjet head 21 with the head controller 22. The communication interface 42 includes various terminals to which the transmission FPC31 is connected.

The communication interface 42 has a plurality of power supply voltage input terminals to which the power supply voltage is supplied from the head controller 22 and a plurality of control signal input terminals to which the control signal is supplied from the head controller 22. For example, the communication interface 42 is provided with 4 VAA input terminals connected to a plurality of wirings for transmitting the power supply voltage VAA in the transmission FPC31, respectively. The VAA input terminals are connected to the power supply input terminals of the power supply voltage VAA of the driver IC45, respectively. In addition, the communication interface 42 is provided with 2 VCC input terminals connected to a plurality of wirings for transmitting the power supply voltage VCC in the transmission FPC31, respectively. The VCC input terminals are connected to the power supply input terminals of the power supply voltage VCC of the driver IC45, respectively. In addition, at least 1 of the VCC input terminals is connected in parallel with the anode of the first diode 61 and the input terminal of the power supply voltage VCC of the driver IC45. With these configurations, the power supply voltage VAA and the power supply voltage VCC are supplied from the head controller 22 to the recovery circuit 46 and the driver IC45 via the transmission FPC31 and the communication interface 42.

In addition, the communication interface 42 is provided with 1 VDD input terminal connected to a wiring for transmitting the power supply voltage VDD in the transmission FPC 31. The VDD input terminal is connected in parallel with the anode of the second diode 64 and the power input terminal of the buffer IC43. The cathode of the second diode 64 is connected to the power input terminal of the logic power supply voltage generator 44 of the driver IC 45. With this configuration, the power supply voltage VDD is supplied from the head controller 22 to the logic power supply voltage generator 44 and the buffer IC43 via the transmission FPC31 and the communication interface 42.

In addition, the communication interface 42 is provided with 1 CK input terminal, and the 1 CK input terminal is connected to a wiring for transmitting the clock signal CK in the transmission FPC31, and is connected to a signal input terminal of the clock signal CK of the buffer IC43. The communication interface 42 includes 1 RST input terminal, and the 1 RST input terminal is connected to a wire for transmitting the reset signal RST in the transmission FPC31 and to a signal input terminal of the reset signal RST of the buffer IC43. In addition, the communication interface 42 is provided with 1 INIT input terminal, which is connected to a wiring for transmitting the initialization signal INIT in the transmission FPC31, and is connected to a signal input terminal of the initialization signal INIT of the buffer IC43. In addition, the communication interface 42 is provided with 1 SDI input terminal connected to the wiring for transferring the print data SDI in the transfer FPC31, and connected to the signal input terminal of the print data SDI of the buffer IC43. In addition, the communication interface 42 has 7 GND terminals that are grounded. With these configurations, the clock signal CK, the reset signal RST, the initialization signal INIT, and the print data SDI are supplied from the head controller 22 to the buffer IC43 via the transfer FPC31 and the communication interface 42.

The buffer IC43 is connected to the VDD input terminal of the communication interface 42, and operates by the power supply voltage VDD. The buffer IC43 has an input tolerance function. The buffer IC43 changes (normalizes) the voltage level of the control signal supplied from the head controller 22 via the transmission FPC31 and the communication interface 42, generates a control signal for controlling the driver IC45, and supplies the control signal to the driver IC45. For example, the buffer IC43 normalizes the clock signal CK input to the signal input terminal of the clock signal CK, and converts it into the clock signal CK-IC. The buffer IC43 normalizes the reset signal RST input to the signal input terminal of the reset signal RST, and converts the reset signal RST into a reset signal RST-IC. In addition, the buffer IC43 normalizes the initialization signal INIT input to the signal input terminal of the initialization signal INIT, and converts it into an initialization signal INIT-IC. In addition, the buffer IC43 normalizes the print data SDI input to the signal input terminal of the print data SDI, and converts it into print data SDI-IC. The buffer IC43 inputs the clock signal CK-IC, the reset signal RST-IC, the initialization signal INIT-IC, and the print data SDI-IC to the driver IC45.

The signal input terminals of the buffer IC43 are configured as input protection circuits. That is, the buffer IC43 is an IC having an input tolerance function in which the diode on the positive side (positive direction from the signal input terminal to the power supply input terminal) is not connected to the signal input terminal of the clock signal CK, the signal input terminal of the reset signal RST, the signal input terminal of the initialization signal INIT, and the signal input terminal of the print data SDI. Thus, even when the voltage of the signal input to the signal input terminal becomes higher than the power supply voltage VDD, the current can be prevented from flowing from the signal input terminal to the power supply input terminal.

The logic power supply voltage generator 44 (logic power supply circuit) converts the power supply voltage VDD into a power supply voltage VDD-IC corresponding to the specification of the driver IC45. The logic power supply voltage generator 44 inputs the power supply voltage VDD-IC to the driver IC45.

The driver IC45 is connected to the VAA input terminal, VCC input terminal, and the like of the communication interface 42, the logic power supply voltage generator 44, the buffer IC43, and the like. The driver IC45 drives the channel group 41 based on the control signal output from the buffer IC 43.

The driver IC45 receives the power supply voltage VAA, the power supply voltage VCC, and the power supply voltage VDD-IC as power supply inputs, and generates a driving waveform based on control signals such as the clock signal CK-IC, the reset signal RST-IC, the initialization signal INIT-IC, and the print data SDI-IC, which are input from the buffer IC 43. The driver IC45 deforms the actuator by inputting a driving waveform to the electrodes of the actuator of the channel group 41 via the electrode group 50, and changes the volume of the pressure chamber. Thereby, the driver IC45 ejects ink in the pressure chamber from the ejection nozzle.

Fig. 4 is an explanatory diagram for explaining a configuration example of the driver IC 45. The driver IC45 includes a logic circuit 51, a level shifter 52, and a driver 53.

The logic circuit 51 operates by the power supply voltage VDD-IC. The logic circuit 51 generates a drive signal for controlling the switching element of the driver 53 based on the clock signal CK-IC, the reset signal RST-IC, the initialization signal INIT-IC, and the print data SDI-IC, which are input as control signals. The logic circuit 51 inputs a drive signal to the level shifter 52. The logic circuit 51 includes a register for storing the print data SDI-IC at one time.

The terminal to which the control signal of the logic circuit 51 is input is also configured as an input protection circuit. That is, the signal input terminal of the clock signal CK-IC, the signal input terminal of the reset signal RST-IC, the signal input terminal of the initialization signal INIT-IC, and the signal input terminal of the print data SDI-IC are configured such that diodes on the positive side (positive direction from the signal input terminal to the power input terminal) are not connected, respectively. Thus, even when the voltage of the signal input to the signal input terminal becomes higher than the power supply voltage VDD-IC, the current can be prevented from flowing from the signal input terminal to the power supply input terminal.

The level shifter 52 converts the voltage level of the drive signal input from the logic circuit 51 using the power supply voltage VCC. The level shifter 52 inputs the drive signal converted in voltage level to the driver 53.

The driver 53 includes 2 switching elements each including a p-MOSFET and an n-MOSFET for each electrode included in the channel group 41, for example. The gate of the switching element is connected to the output terminal of the level shifter 52. The p-MOSFET source is connected to the supply voltage VAA and the n-MOSFET source is connected to GND. The drains of the connection points of the 2 switching elements are connected to the electrodes of the channel group 41. With this configuration, the driver 53 outputs the power supply voltage VAA or GND level at a timing corresponding to the drive signal input from the level shifter 52. Thereby, the driver 53 inputs a driving waveform to each electrode of the channel group 41. As a result, the driver 53 ejects ink from the ejection nozzles of the channel group 41.

The recovery circuit 46 prevents the voltage of the VCC input terminal of the communication interface 42 from being lowered and supplied to the power supply input terminal of the logic circuit 51 of the driver IC45, and the potential of the power supply input terminal of the logic circuit 51 of the driver IC45 (or the power supply input terminal of the logic power supply voltage generator 44) is supplied to the power supply input terminal of the buffer IC 43. In addition, the restoration circuit 46 supplies the power supply voltage VDD as a power supply voltage VDD-DI (first voltage) to the logic power supply voltage generator 44.

As described above, the recovery circuit 46 includes the buffer IC43, the first diode 61, the resistor 62, the zener diode 63, and the second diode 64.

The first diode 61 connects the anode to the VCC input terminal of the communication interface 42 as a power supply input terminal, and connects the cathode to the power supply input terminal of the logic power supply voltage generator 44 via the resistor 62. In addition, the first diode 61 is a schottky diode.

A connection point 70 is formed between the cathode of the first diode 61 and the power input terminal of the logic supply voltage generator 44. A resistor 62 is formed between the cathode of the first diode 61 and the connection point 70.

The resistor 62 drops the VCC power supply voltage from the VCC input terminal and supplies the dropped VCC power supply voltage to the logic power supply voltage generator 44. For example, resistor 62 is 10kΩ.

As described above, the second diode 64 connects the anode to the VDD input terminal of the communication interface 42 as the power supply voltage input terminal, and connects the cathode to the connection point 70. In addition, the second diode 64 is a schottky diode.

In addition, a zener diode 63 connects the anode to ground and the cathode to the connection point 70. The zener diode 63 sets an upper limit of the voltage supplied to the logic power supply voltage generator 44. For example, the zener voltage of the zener diode 63 is 4.8V.

In the above configuration, when no connection failure occurs in the path for transmitting the VDD power supply voltage, the power supply voltage VDD-DI becomes 4.6V. The logic power supply voltage generator 44 is mainly supplied with current from the VDD input terminal, but is supplied with 3.4mA from the VCC input terminal.

In addition, in the case where a connection failure occurs in a path through which the VDD power supply voltage is transmitted, the power supply voltage VDD-DI is supplied from the VCC input terminal to the logic power supply voltage generator 44 via the first diode 61 and the resistor 62. The supply voltage VDD-DI is similarly 4.6V. The logic power supply voltage generator 44 is supplied with 3.4mA from the VCC input terminal.

In this case, since the power supply to the buffer IC43 is stopped, the buffer IC does not send the control signal to the driver IC45. That is, the control signal is set to substantially GND level. Thus, the logic circuit 51 of the driver IC45 is not supplied with the clock signal CK-IC, and thus the driver IC45 does not consume power. Therefore, even if the current from the logic power supply voltage generator 44 to the logic circuit 51 decreases, the potential of the power supply voltage VDD-IC of the logic circuit can be maintained, and thus it is not a problem.

Next, an operation when there is no connection failure in the path for transmitting the power supply voltage VDD (at the time of normal operation) will be described.

Fig. 5 is a timing chart for explaining the normal operation of the head controller 22 and the inkjet head 21. In fig. 5, the horizontal axis represents time and the vertical axis represents voltage. Fig. 6 is a timing chart showing VCC (power supply voltage VCC), VDD (power supply voltage VDD), and VDD-DI (power supply voltage VDD-DI) of fig. 5. In fig. 6, the horizontal axis represents time and the vertical axis represents voltage.

At timing t1, when the power supply of the inkjet printer 1 is turned on, the direct-current voltage DCV is supplied from the power supply circuit 23 to the head controller 22.

When the dc voltage DCV is supplied, the power supply voltage generator 32 generates the power supply voltage VAA-IN, the power supply voltage VCC-IN, the power supply voltage VDD-IN, and the power supply voltage VDD-LOG at a timing t2. The power supply voltage generator 32 supplies the power supply voltage VAA-IN, the power supply voltage VCC-IN, and the power supply voltage VDD-IN to the power supply timing circuit 33, and supplies the power supply voltage VDD-LOG to the control IC35.

At timing t3, when the control IC35 is inputted with a print instruction, the control IC35 supplies the switching signal VOL-SW that sets the power supply timing circuit 33 to the enabled state to the power supply timing circuit 33. That is, the control IC35 sets the switching signal VOL-SW to the H level. When the power supply timing circuit 33 is in an enabled state by the switching signals VOL to SW, the output of the power supply voltage VDD, the power supply voltage VCC, and the power supply voltage VAA is started in this order.

At timing t4, the power supply timing circuit 33 starts output of the power supply voltage VDD. At this time, the restoration circuit 46 supplies the power supply voltage VDD as the power supply voltage vdd—di to the logic power supply voltage generator 44. In addition, at timing t4, the logic power supply voltage generator 44 of the inkjet head 21 supplies the power supply voltage VDD-IC to the driver IC45. In addition, at timing t4, the control IC35 starts outputting the clock signal CK and the initialization signal INIT to the buffer IC43 of the inkjet head 21. In addition, at timing t4, the buffer IC43 normalizes the clock signal CK and the initialization signal INIT, and supplies the clock signal CK-IC and the initialization signal INIT-IC to the driver IC45.

At timing t5, the control IC35 starts outputting the reset signal RST to the buffer IC43 of the inkjet head 21. Further, at timing t5, the buffer IC43 normalizes the reset signal RST and supplies the reset signal RST-IC to the driver IC45.

At timing t6, the power supply timing circuit 33 starts output of the power supply voltage VCC. Thereby, the driver IC45 is supplied with the power supply voltage VCC.

At timing t7, the power supply timing circuit 33 starts output of the power supply voltage VAA. Thereby, the driver IC45 is supplied with the power supply voltage VAA.

At timing t8, the control IC35 starts outputting the print data SDI to the buffer IC43 of the inkjet head 21. In addition, at timing t8, the buffer IC43 normalizes the print data SDI, and supplies the print data SDI-IC to the driver IC45.

At timing t9, the control IC35 causes the inkjet head 21 to start printing. For example, the control IC35 decreases the initialization signal INIT from the H level to the L level by a prescribed amount of clocks (for example, an amount of 1 clock) at a timing t9 when the output of the print data SDI of 1 line amount is completed. Thereby, the initialization signal INIT-IC input to the driver IC45 by the buffer IC43 is also lowered to the L level. The logic circuit 51 of the driver IC45 starts generation of the driving signal using the clock signal CK-IC, the print data SDI-IC, and the power supply voltage VDD-IC with the initialization signal INIT-IC lowered to the L level as a trigger event. Thus, the level shifter 52 and the driver 53 start to operate, and a driving waveform is input to the electrodes of the channel group 41. As a result, printing is performed.

When the control IC35 recognizes that printing is completed at the timing t10, the control IC35 supplies the switching signal VOL-SW for turning the power supply timing circuit 33 to the disabled state to the power supply timing circuit 33. That is, the control IC35 sets the switching signal VOL-SW to the L level. When the power supply timing circuit 33 is turned on by the switching signals VOL to SW, the output is stopped in the order of the power supply voltage VAA, the power supply voltage VCC, and the power supply voltage VDD.

At timing t11, the power supply timing circuit 33 stops the output of the power supply voltage VAA. Thereby, the supply of the power supply voltage VAA to the driver IC45 is stopped.

At timing t12, the power supply timing circuit 33 stops the output of the power supply voltage VCC. Thereby, the supply of the power supply voltage VCC to the driver IC45 is stopped.

At timing t13, the power supply timing circuit 33 stops the output of the power supply voltage VDD. Further, at timing t13, the control IC35 stops the output of the clock signal CK, the reset signal RST, and the initialization signal INIT. That is, at timing t13, the control IC35 lowers the clock signal CK, the reset signal RST, and the initialization signal INIT from the H level to the L level. Thereby, the clock signal CK-IC, the reset signal RST-IC, and the initialization signal INIT-IC supplied from the buffer IC43 to the driver IC45 are also lowered from the H level to the L level. In addition, the recovery circuit 46 stops the output of the power supply voltage VDD-DI. This causes the logic power supply voltage generator 44 to be in a state in which the power supply voltage is not supplied to the power supply input terminal. As a result, the supply of the power supply voltage VDD-IC to the driver IC45 is stopped.

Next, an operation when there is a connection failure (abnormal time) in the path for transmitting the power supply voltage VDD will be described.

Fig. 7 is a timing chart for explaining the operation at the time of abnormality of the head controller 22 and the inkjet head 21. In fig. 7, the horizontal axis represents time and the vertical axis represents voltage. In addition, fig. 8 is a timing chart showing VCC (power supply voltage VCC), VDD (power supply voltage VDD) and VDD-DI (power supply voltage VDD-DI) of fig. 7. In fig. 8, the horizontal axis represents time and the vertical axis represents voltage.

At timing t3, when the control IC35 is inputted with a print instruction, the control IC35 supplies the switching signal VOL-SW that sets the power supply timing circuit 33 to the enabled state to the power supply timing circuit 33. That is, the control IC35 sets the switching signal VOL-SW to the H level. When the power supply timing circuit 33 is in an enabled state by the switching signals VOL to SW, the power supply timing circuit starts outputting the power supply voltage VDD, the power supply voltage VCC, and the power supply voltage VAA in this order.

At timing t4, the power supply timing circuit 33 starts output of the power supply voltage VDD. However, if there is a connection failure in the path for transmitting the power supply voltage VDD, the power supply voltage VDD is not supplied to the logic power supply voltage generator 44 and the buffer IC43 of the inkjet head 21. In addition, at timing t4, the control IC35 starts outputting the clock signal CK and the initialization signal INIT to the buffer IC43 of the inkjet head 21. Since the power supply voltage VDD is not supplied, the buffer IC43 is in a state of holding the operation stopped. Therefore, the clock signal CK-IC and the initialization signal INIT-IC are not supplied from the buffer IC43 to the driver IC 45.

At timing t5, the control IC35 starts outputting the reset signal RST to the buffer IC43 of the inkjet head 21. However, since the buffer IC43 does not operate, the reset signal RST-IC is not supplied to the driver IC45.

At timing t6, the power supply timing circuit 33 starts output of the power supply voltage VCC. Thereby, the driver IC45 is supplied with the power supply voltage VCC. In addition, the power supply voltage VCC is input as a power supply voltage VDD-DI to the power supply input terminal of the logic power supply voltage generator 44 via the first diode 61 and the resistor 62. In addition, the power supply voltage VDD-DI is set to an upper limit by the zener diode 63. The logic power supply voltage generator 44 generates a power supply voltage VDD-IC using the power supply voltage VDD-DI, and starts supply of the power supply voltage VDD-IC to the driver IC 45.

At timing t8, the control IC35 starts outputting the print data SDI to the buffer IC43 of the inkjet head 21. However, since the buffer IC43 does not operate, the print data SDI-IC is not supplied to the driver IC45. In addition, in this case, printing is not performed.

At timing t9, the control IC35 causes the inkjet head 21 to start printing. For example, the control IC35 decreases the initialization signal INIT from the H level to the L level by a prescribed amount of clocks (for example, an amount of 1 clock) at a timing t9 when the output of the print data SDI of 1 line amount is completed. However, since the buffer IC43 does not operate, printing is not performed.

Further, at timing t10, the control IC35 supplies the switching signal VOL-SW for bringing the power supply timing circuit 33 into the disabled state to the power supply timing circuit 33. That is, the control IC35 sets the switching signal VOL-SW to the L level. When the power supply timing circuit 33 is turned on by the switching signals VOL to SW, the output is stopped in the order of the power supply voltage VAA, the power supply voltage VCC, and the power supply voltage VDD.

At timing t12, the power supply timing circuit 33 stops the output of the power supply voltage VCC. Thereby, the supply of the power supply voltage VCC to the driver IC45 is stopped. In addition, the recovery circuit 46 stops the output of the power supply voltage VDD-DI. Thereby, the power supply voltage VDD-DI supplied to the power supply input terminal of the logic power supply voltage generator 44 is stopped. As a result, the supply of the power supply voltage VDD-IC to the driver IC45 is stopped.

At timing t13, the power supply timing circuit 33 stops the output of the power supply voltage VDD. Further, at timing t13, the control IC35 stops the output of the clock signal CK, the reset signal RST, and the initialization signal INIT. That is, at timing t13, the control IC35 lowers the clock signal CK, the reset signal RST, and the initialization signal INIT from the H level to the L level.

For example, when the power supply voltage VAA and the power supply voltage VCC are supplied to the driver IC45 and the power supply voltage VDD-IC is not supplied to the driver IC45, the driving signal is not supplied from the logic circuit 51 to the level shifter 52. The level shifter 52 is in an indeterminate state when the power supply voltage VCC is supplied and the driving signal is not supplied from the logic circuit 51. In this case, it is possible for the level shifter 52 to turn on 2 switching elements of the driver 53 at the same time. When 2 switching elements of the driver 53 are simultaneously turned on, the power supply voltage VAA is applied to the conductive paths of the 2 switching elements, and a through current flows.

However, as described above, even when there is a connection failure in the path for transmitting the power supply voltage VDD and the power supply voltage VDD is not supplied to the buffer IC43 and the logic power supply voltage generator 44, the recovery circuit 46 can be supplied to the power supply input terminal of the logic power supply voltage generator 44 via the first diode 61 and the resistor 62. According to this configuration, the logic power supply voltage generator 44 can generate the power supply voltage VDD-IC using the power supply voltage VCC. That is, the logic power supply voltage generator 44 can ensure the potential of the power supply input terminal of the logic circuit 51 to which the power supply voltage vdd—ic is input by the power supply voltage VCC. As a result, the recovery circuit 46 can prevent the level shifter 52 from being in an uncertain state without the drive signal being supplied from the logic circuit 51 to the level shifter 52, and the through current flows through the driver 53. That is, the inkjet head and the inkjet printer of the present embodiment have high safety.

When the power supply voltage VDD is not supplied, the buffer IC43 is in a state in which no control signal is input to the driver IC 45. That is, the buffer IC43 is in a state in which the clock signal CK-IC, the reset signal RST-IC, the initialization signal INIT-IC, and the print data SDI-IC of the substantially GND level are input to the logic circuit 51 of the driver IC 45. In this case, the logic circuit 51 of the driver IC45 is not supplied with the clock signal CK-IC as the reference clock, and therefore is in a state of no operation and no power consumption. This ensures the potential of the power supply input terminal of the logic circuit 51 with a minimum current. As a result, the power load on the control IC35 of the head controller 22 can be reduced.

In addition, a second diode 64 is connected between the power input terminal of the buffer IC43 and the connection point 70, and the second diode 64 prevents the power supply voltage VDD-DI generated by the power supply voltage VCC from being input to the power input terminal of the buffer IC 43. In this way, when there is a connection failure in the transmission path of the power supply voltage VDD, the buffer IC43 can be prevented from operating. In addition, when there is a connection failure in the transmission path of the power supply voltage VDD, the buffer IC43 and the driver IC45 are deactivated, so that the head controller 22 can easily detect a defect caused by the control IC 35.

While several embodiments of the present invention have been described, these embodiments are presented by way of example only and are not intended to limit the scope of the invention. These novel embodiments can be implemented in various other modes, and various omissions, substitutions, and changes can be made without departing from the spirit of the invention. The present invention is not limited to the above embodiments and modifications, and is intended to be included in the scope and spirit of the invention.

Claims

1. An inkjet head includes:

a driver IC including a logic circuit and a level shifter;

A logic power supply circuit which supplies a voltage to the logic circuit after inputting a first voltage to a power supply input terminal; and

And a first diode having an anode connected to the second voltage inputted to the level shifter and a cathode connected to a power input terminal of the logic power circuit.

2. The inkjet printhead of claim 1, wherein,

The inkjet head further includes: a buffer IC for supplying a control signal to the logic circuit after the first voltage is input to the power supply input terminal; and

And a second diode having an anode connected to a power input terminal of the buffer IC and a cathode connected to a connection point between the cathode of the first diode and the power input terminal of the logic power circuit.

3. The inkjet head according to claim 2, wherein,

The inkjet head is further provided with a zener diode connecting the anode to GND and the cathode to the connection point.

4. The inkjet head according to claim 3, wherein,

The inkjet head further includes a resistor formed between the cathode of the first diode and the connection point.

5. The inkjet head according to any one of claims 2 to 4, wherein,

The buffer IC has an input tolerance function.

6. An inkjet printer includes:

An inkjet head that ejects ink onto a print medium; and

A head controller for supplying a first voltage and a second voltage to the inkjet head,

The inkjet head includes:

a driver IC including a logic circuit and a level shifter;

a logic power supply circuit that supplies a voltage to the logic circuit after the first voltage is input to a power supply input terminal; and

7. The inkjet printer of claim 6, wherein,

8. The inkjet printer of claim 7, wherein,

9. The inkjet printer of claim 8, wherein,

10. The inkjet printer according to any one of claims 7 to 9, wherein,

The buffer IC has an input tolerance function.