CN118315414A - Structure, method and application for improving off-state electrical characteristics of longitudinal power electronic device - Google Patents
Structure, method and application for improving off-state electrical characteristics of longitudinal power electronic device Download PDFInfo
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Abstract
The invention discloses a structure, a method and application for improving the off-state electrical characteristics of a longitudinal power electronic device. The structure comprises: the semiconductor device comprises a semiconductor substrate with a first area and a second area, a high-resistance area arranged in the first area, an electrode electrically combined with the surface of the second area, a field plate medium continuously covering at least part of the surface of the high-resistance area and part of the surface of the second area of the semiconductor substrate, and field plate metal continuously covering the surfaces of the field plate medium and the electrode, wherein part of the surface of the electrode is exposed from the field plate medium and is electrically combined with the field plate metal. According to the invention, the edge peak electric field of the longitudinal power electronic device is separated from the space position of the leakage channel, so that the effects of reducing off-state leakage and improving blocking voltage can be achieved at the same time, the forward electric property of the device is effectively ensured, and the reliability and long-term stability of the device are obviously improved.
Description
Technical Field
The invention relates to a vertical power electronic device, in particular to a structure and a method for improving the off-state electrical characteristics of a vertical III-nitride power electronic device and application thereof, and belongs to the field of semiconductor electronic devices.
Background
Due to the advantages of wide band gap, high critical breakdown field intensity, high electron saturation drift rate and the like, the third-generation semiconductor material such as gallium nitride (GaN) and other III-group nitrides have important application values in the fields of power supplies such as mobile phone fast charging and data centers and the like. Compared with a transverse power device based on AlGaN/GaN heterojunction, the vertical power device has the advantages that the peak electric field is located in the body, the dynamic characteristic of the device is good, the current transport area is large, the heat dissipation performance is good, and the reliability is high.
The switch is the basic function of the power device, namely on-state conduction and off-state blocking. The off-state leakage and blocking voltage are the basic off-state electrical properties. Low leakage and high blocking voltages are the targets sought for power devices. In general, the off-state leakage of the device mainly comprises bulk leakage and junction edge leakage, and the bulk leakage of the device can be reduced by reducing the net carrier concentration of the drift region, which, however, increases the on-resistance and on-state/switching loss of the device, which is not an ideal scheme for improving the off-state electrical characteristics of the device.
When the vertical type group III nitride power device is under reverse bias, off-state leakage of the device is mainly formed by junction region leakage (PN junction or schottky junction) interface and metal electrode (anode or source) edge, wherein the electric field crowding effect of the metal electrode edge causes the existence of peak electric field, which increases junction edge leakage of the device, causes the device to break down at the metal edge in advance, and particularly, the peak electric field is always on a leakage path, so that off-state blocking voltage of the device is reduced.
The prior art is difficult to effectively improve the off-state electrical characteristics of the device so as to reduce the switching loss of the device, and the specific description is as follows:
From the aspect of epitaxial materials, reverse leakage of the device can be reduced by reducing the net doping concentration of the drift region, and blocking voltage of the device is improved. However, on one hand, the on-state on-resistance of the device can be increased, and on-loss of the device can be increased, on the other hand, as breakdown of the device is mainly influenced by the edge spike electric field, the device is insensitive to the net carrier concentration of the drift region, that is, the edge spike electric field of the device can not be obviously reduced by reducing the net carrier concentration, that is, the blocking voltage of the device is difficult to be raised.
From a device process or design perspective, many termination structures have been used to improve the off-state electrical performance of the device, i.e., to reduce reverse leakage of the device and to increase blocking voltage. Terminal structures are often prepared near the main junction of the device, such as a field plate, an ion implantation terminal and a junction expansion terminal, wherein the ion implantation terminal can regulate and control the electron transportation process by introducing proper amount of material defects, so that the off-state electric leakage of the device is reduced, the reverse voltage resistance of the device is improved, and the process preparation is simple, thereby achieving great development. However, the conventional ion implantation region is located at the edge of the main junction, which results in defects being introduced that limit the lateral spread of current when the device is turned on in the forward direction. In addition, the introduced defect state is in the leakage channel, and can weaken the peak electric field at the edge of the main junction under the low reverse bias voltage, however, along with the filling of the injected electrons to the defect state, the regulation and control of the introduced defect state to the peak electric field at the edge of the main junction under the high reverse bias voltage are very limited. In fact, many termination structures exist that only attenuate the intensity of the main junction edge spike field, which is always on the leakage path of the main junction, resulting in high leakage of the device at high reverse bias voltages. Because the peak electric field of the device is always located on the leakage channel, the existing method can not change the essential condition, so that the off-state electrical performance of the device is difficult to improve fundamentally, namely synchronous optimization of reverse leakage and blocking voltage is realized.
How to raise the blocking voltage of the device and reduce off-state leakage at the same time without affecting the on-state electrical characteristics of the device has become an important issue in GaN vertical power devices.
Disclosure of Invention
The invention mainly aims to provide a structure, a method and application for improving the off-state electrical characteristics of a longitudinal power electronic device so as to overcome the defects in the prior art.
In order to achieve the purpose of the invention, the technical scheme adopted by the invention comprises the following steps:
One aspect of the present invention provides a structure for improving the off-state electrical characteristics of a vertical power electronic device, comprising:
a semiconductor substrate having a first region and a second region, the first region and the second region being distributed in a direction parallel to a surface of the semiconductor substrate;
The high-resistance region is arranged in the first region of the semiconductor substrate;
The electrode is electrically combined with the surface of the second area of the semiconductor substrate, and the electrode and the high-resistance area are arranged at intervals in the direction parallel to the surface of the semiconductor substrate;
a field plate medium at least continuously covering at least a partial surface of the high-resistance region and a partial surface of the second region of the semiconductor substrate, and at least a partial surface of the electrode is exposed from the field plate medium;
and the field plate metal is continuously covered on the surfaces of the field plate medium and the electrode and is electrically combined with the electrode.
Another aspect of the invention provides a method of improving the off-state electrical characteristics of a vertical power electronic device, comprising:
defining a first region and a second region in a semiconductor substrate, wherein the first region and the second region are distributed along a direction parallel to the surface of the semiconductor substrate;
Performing selective ion implantation on the first region of the semiconductor substrate to form a high-resistance region in the first region of the semiconductor substrate,
Or processing a groove-shaped structure in the first area of the semiconductor substrate, and filling a dielectric material in the groove-shaped structure, so that a high-resistance area is formed in the first area of the semiconductor substrate;
providing an electrode on the surface of the second region of the semiconductor substrate, electrically combining the electrode with the semiconductor substrate, and separating the electrode and the high-resistance region from each other in a direction parallel to the surface of the semiconductor substrate;
Continuously covering a field plate medium on at least partial surfaces of the high-resistance region and the second region of the semiconductor substrate, and opening a window on the field plate medium so that at least partial surfaces of the electrodes are exposed from the field plate medium;
And continuously covering field plate metal on the surfaces of the field plate medium and the electrode, and electrically combining the field plate metal with the electrode.
In a further aspect, the invention provides the use of the structure or method for improving the off-state electrical characteristics of a vertical power electronic device in the manufacture of a vertical power electronic device, in particular a vertical power electronic device of a group III nitride semiconductor.
According to the invention, the field plate medium and the high-resistance region are introduced into the structure of the longitudinal power electronic device, the electric field coupling can be carried out through the field plate medium, so that the peak electric field at the edge of the contact junction between the metal and the semiconductor is coupled to the edge of the field plate, and the peak electric field is far away from the leakage channel of the device, thereby greatly reducing reverse leakage of the device, simultaneously reducing the peak electric field at the edge of the field plate through the high-resistance region, greatly improving the overall blocking voltage of the device, and not affecting the forward electric property of the device, namely not increasing the on-resistance of the device, and not degrading the dynamic characteristics of the device. The scheme of combining the thin field plate and the ion implantation not only improves the reverse blocking voltage of the device and reduces reverse leakage, but also has no influence on the forward direction condition of the device; meanwhile, the thicker potential barrier of the field plate medium weakens the filling effect of the defects of the ion implantation area, so that the ion implantation area can still adjust the fringe electric field at high reverse bias voltage, and the adjusting effect of the electric field in turn reduces the effect of electric stress on the field plate, and improves the service life and the electrical reliability of the field plate.
Compared with the prior art, the invention has the advantages that:
(1) In the structure for improving the off-state electrical characteristics of the longitudinal power electronic device, the off-state leakage and blocking voltage can be greatly improved simultaneously by spatially separating the edge peak electric field region and the leakage region of the device.
(2) In the method for improving the off-state electrical characteristics of the longitudinal power electronic device, the anode contact of the device is not influenced, the forward conduction of the device is not influenced, namely the forward electrical properties (dynamic and static) of the device are not influenced.
(3) The method for improving the off-state electrical characteristics of the longitudinal power electronic device is simple, has a large process window, is particularly large in window of an ion implantation process, can be compatible with various other processes, is suitable for various longitudinal device power devices, comprises longitudinal diodes, triodes and the like, and is not limited to the processes.
Drawings
FIG. 1 is a schematic view of a semiconductor substrate according to an embodiment of the present invention;
FIG. 2 is a schematic view of an electrode disposed on the semiconductor substrate shown in FIG. 1;
FIG. 3 is a schematic illustration of the formation of high resistance regions in a semiconductor body of the device structure of FIG. 2 by selective ion implantation;
FIG. 4is a schematic illustration of the deposition of field medium on the surface of the device structure shown in FIG. 3;
FIG. 5 is a schematic illustration of a window in a field medium in the device structure of FIG. 4;
FIG. 6 is a schematic illustration of the deposition of field plate metal on the device structure shown in FIG. 5;
Fig. 7 is a schematic view of a semiconductor substrate with a recess formed therein to form a high-resistance region in the device structure of fig. 2 according to another embodiment of the present invention;
Fig. 8 is a schematic diagram of a vertical schottky barrier diode according to embodiment 1 of the present invention;
Fig. 9 is a schematic diagram of a vertical trench junction barrier schottky diode according to embodiment 2 of the present invention;
fig. 10 is a schematic diagram of the structure of a vertical pn diode according to embodiment 3 of the present invention;
fig. 11 is a schematic diagram of a quasi-vertical schottky barrier diode according to embodiment 4 of the present invention;
fig. 12 is a schematic diagram of a quasi-vertical type notch junction barrier schottky diode according to embodiment 5 of the present invention;
Fig. 13 is a schematic structural diagram of a vertical fin field effect transistor according to embodiment 6 of the present invention;
fig. 14 is a schematic structural diagram of a quasi-vertical pn diode in embodiment 7 of the present invention;
fig. 15 is a schematic diagram of a quasi-vertical fin field effect transistor according to embodiment 8 of the present invention;
fig. 16 is a schematic diagram showing the structure of a vertical schottky barrier diode according to embodiment 9 of the present invention.
Detailed Description
In view of the drawbacks of the prior art, the inventor of the present invention has long studied and put forward a technical solution of the present invention, and the technical solution, the implementation process and principle thereof will be further explained as follows. It is to be understood that within the scope of the present invention, the above-described features of the present invention and those specifically described in the following (embodiments) may be combined with each other to constitute new or preferred embodiments. Is limited to a space and will not be described in detail herein.
Some embodiments of the present invention provide a structure for improving the off-state electrical characteristics of a vertical power electronic device, including:
a semiconductor substrate having a first region and a second region, the first region and the second region being distributed in a direction parallel to a surface of the semiconductor substrate;
The high-resistance region is arranged in the first region of the semiconductor substrate;
The electrode is electrically combined with the surface of the second area of the semiconductor substrate, and the electrode and the high-resistance area are arranged at intervals in the direction parallel to the surface of the semiconductor substrate;
a field plate medium at least continuously covering at least a partial surface of the high-resistance region and a partial surface of the second region of the semiconductor substrate, and at least a partial surface of the electrode is exposed from the field plate medium;
and the field plate metal is continuously covered on the surfaces of the field plate medium and the electrode and is electrically combined with the electrode.
Further, the edges of the field plate metal are disposed on the surface of the high-resistance region, i.e., the field plate metal edges are seated in the surface region of the high-resistance region.
In one embodiment, the high resistance region is formed by selective ion implantation of a first region of the semiconductor substrate. The type, energy, dose, etc. of ions employed therein may be dependent upon practical requirements, including single energy implantation and multiple energy combination implantation (more evenly distributed in the semiconductor).
The ions may be selected from, but are not limited to, ions of helium, nitrogen, fluorine, magnesium, aluminum, argon, and the like.
For example, if the semiconductor substrate is a group III nitride material, the ions suitable for ion implantation in the selected region may be selected from nitrogen having an energy of about 10 to 1000keV and a dose of about 1e13 to 1e17cm -2.
In one embodiment, the high resistance region includes a trench-like structure formed within the first region of the semiconductor body and a dielectric material filled within the trench-like structure. The shape, size and type of the dielectric material of the slot-like structure can be determined according to actual requirements. For example, the dielectric material may be selected from inorganic or organic dielectric materials such as silicon oxide, aluminum oxide, silicon nitride (e.g., silicon nitride), spin-on glass (SOG), polyimide (PI), etc., and is not limited thereto.
In one embodiment, the first region may be a ring-shaped region disposed around the second region, and the high-resistance region may be a ring-shaped region disposed around the electrode. Or the first region may be distributed on two sides of the second region, and the high-resistance region is a regular or irregular block-shaped, strip-shaped region, or the like, and is not limited thereto.
In one embodiment, the electrodes are integrally provided with the field plate metal.
Some embodiments of the present invention also provide a method of improving the off-state electrical characteristics of a vertical power electronic device, comprising:
defining a first region and a second region in a semiconductor substrate, wherein the first region and the second region are distributed along a direction parallel to the surface of the semiconductor substrate;
Performing selective ion implantation on the first region of the semiconductor substrate to form a high-resistance region in the first region of the semiconductor substrate,
Or processing a groove-shaped structure in the first area of the semiconductor substrate, and filling a dielectric material in the groove-shaped structure, so that a high-resistance area is formed in the first area of the semiconductor substrate;
providing an electrode on the surface of the second region of the semiconductor substrate, electrically combining the electrode with the semiconductor substrate, and separating the electrode and the high-resistance region from each other in a direction parallel to the surface of the semiconductor substrate;
Continuously covering a field plate medium on at least partial surfaces of the high-resistance region and the second region of the semiconductor substrate, and opening a window on the field plate medium so that at least partial surfaces of the electrodes are exposed from the field plate medium;
And continuously covering field plate metal on the surfaces of the field plate medium and the electrode, and electrically combining the field plate metal with the electrode.
Further, the edge of the field plate metal is arranged on the surface of the high-resistance region.
In one embodiment, the method specifically comprises the following steps: and forming a high-resistance region in the first region of the semiconductor substrate, and continuously covering the field plate medium on at least partial surfaces of the high-resistance region and the second region of the semiconductor substrate.
In one embodiment, the method specifically comprises the following steps: and firstly, continuously covering a field plate medium on at least partial surfaces of the high-resistance region and the partial surfaces of the second region of the semiconductor substrate, and then forming the high-resistance region in the first region of the semiconductor substrate by a selective ion implantation mode. The process flow of the prior field plate medium and the subsequent ion implantation is favorable for maximizing the improvement of the off-state electrical performance of the device by the ion implantation area, and if the prior process flow of the prior ion implantation and the subsequent field plate medium is adopted, the effect of ion implantation can be weakened due to the high temperature process in the preparation process of the high-quality field plate medium.
In one embodiment, the method specifically comprises the following steps:
Firstly, preprocessing the surface of the semiconductor substrate;
then, continuously covering a field plate medium on at least partial surface of the high-resistance region and partial surface of the second region of the semiconductor substrate;
And then, a window through which the electrode can pass is formed in the field plate medium, an electrode is manufactured at the window, and the high-resistance region is formed in the first region of the semiconductor substrate in a selective ion implantation mode.
In one embodiment, the method further comprises: the semiconductor base is grown on a substrate including, but not limited to, any one or a combination of a silicon substrate, a sapphire substrate, a silicon carbide substrate, a GaN substrate, an AlN substrate, such as a composite substrate thereof.
In the invention, the thickness of the field plate medium is 20-400 nm, if the thickness of the field plate medium is too small, the electron tunneling probability under a strong electric field is larger, so that the reverse blocking voltage of the device is not high; if the thickness of the field plate medium is too large, the peak electric field at the edge of the main junction cannot be coupled to the edge of the medium field plate, on one hand, the field plate loses the function of regulating the peak electric field at the edge of the main junction, and meanwhile, the high-resistance area at the edge of the field plate cannot be utilized.
In the present invention, the field plate medium may be selected from, but not limited to, silicon oxide, aluminum oxide, silicon nitride, spin-on glass (SOG), polyimide (PI), and the like.
In the present invention, the material of the semiconductor substrate includes, but is not limited to, group III nitride (such as GaN, alN, inN and AlGaN or AlInGaN with any Al composition), gallium oxide or diamond, and other wide bandgap semiconductors. The semiconductor body may be n-type or p-type.
In the present invention, the semiconductor substrate may have a single-layer structure or a multi-layer structure, for example, an epitaxial structure of a diode or a triode, and is not limited thereto. The semiconductor substrate may be grown by HVPE (hydride vapor phase epitaxy), MOCVD (metal organic chemical vapor deposition), PECVD (plasma enhanced chemical vapor deposition), or the like, and is not limited thereto.
It should be noted that, in the present invention, the method may further include other pre-processes and subsequent device processing processes that are conventional in the art, such as epitaxial wafer cleaning and surface treatment in the pre-process, and mesa etching in the subsequent process.
Some embodiments of the present invention also provide for the use of the structure or method for improving the off-state electrical characteristics of a vertical power electronic device in the fabrication of a vertical power electronic device. The vertical power electronic device comprises a vertical diode or a vertical triode.
Referring to fig. 1-6, in one embodiment of the present invention, a method for improving the off-state electrical characteristics of a vertical power electronic device includes the steps of:
s1, performing related cleaning and interface treatment on the semiconductor substrate 105, as shown in fig. 1.
S2, depositing anode contact metal on the surface of the semiconductor substrate 105 processed in the step S1 to prepare the electrode 101, as shown in FIG. 2.
S3, performing selective ion implantation treatment on the surface of the semiconductor substrate 105, so as to form a high-resistance region 104 in the semiconductor substrate 105, as shown in FIG. 3.
S4, depositing a field plate medium 102 on the surface of the semiconductor substrate 105, as shown in FIG. 4.
S5, performing a field plate dielectric windowing process to expose a local surface of the electrode 101, as shown in FIG. 5.
S6, finally, depositing the field plate metal 103, so that the field plate metal 103 is in electrical contact with the electrode 101, as shown in FIG. 6.
In this embodiment, the order of performing the ion implantation field plate medium selection process and depositing the field plate medium, i.e., steps S3 and S4, may be reversed, i.e., the field plate medium 102 is deposited first and then the field plate medium selection ion implantation process is performed to form the high-resistance region 104.
The high-resistance region 104 is defined as a high-resistance region having a resistivity of 1×10 3～1x109 Ω·cm because the local region of the semiconductor substrate 105 is subjected to ion implantation and the resistance is increased as compared with other regions in the semiconductor substrate 105.
Referring to fig. 1-7, in another embodiment of the present invention, a method for improving the off-state electrical characteristics of a vertical power electronic device includes the following steps:
s1, performing related cleaning and interface treatment on the semiconductor substrate 105, as shown in fig. 1.
S2, depositing anode contact metal on the surface of the semiconductor substrate 105 processed in the step S1 to prepare the electrode 101, as shown in FIG. 2.
S3, processing grooves on the surface of the semiconductor substrate 105 by adopting dry etching, wet etching or physical grooving process, as shown in FIG. 7. The recesses are then filled with a medium by physical/chemical deposition, such as PVD, CVD, sputtering, etc., to form high resistance regions 104 in the semiconductor body 105, the resulting device structure may also be referred to in fig. 3.
S4, depositing a field plate medium 102 on the surface of the semiconductor substrate 105, and referring to FIG. 4.
S5, performing a field plate dielectric windowing process to expose a local surface of the electrode 101, as shown in FIG. 5.
S6, finally, depositing field plate metal 103, and enabling the field plate metal 103 to be in electrical contact with the electrode 101, as shown in FIG. 6.
The invention can realize the great improvement of off-state leakage and blocking voltage at the same time by spatially separating the edge peak electric field region and the leakage region of the longitudinal power electronic device, and has almost no influence on the forward electric properties (dynamic and static) of the device. Through the electric field coupling effect of the thin field plate, the peak electric field at the edge of the anode/source electrode is transferred to the edge of the field plate medium when the device is reversely biased, so that the reverse electric leakage of the device is reduced. Meanwhile, a local high-resistance region is formed at the metal edge of the field plate, so that the blocking voltage of the whole device is remarkably improved. Furthermore, the scheme of combining the thin field plate and the ion implantation adopted by the invention not only improves the reverse blocking voltage of the device and reduces reverse leakage, but also has no influence on the forward direction condition of the device; meanwhile, the thicker potential barrier of the field plate medium weakens the filling effect of the defect of the ion implantation area, so that the ion implantation area defect can still adjust the fringe electric field at high reverse bias voltage, and the adjusting effect of the electric field in turn reduces the effect of electric stress on the field plate, thereby prolonging the service life and the electric reliability of the field plate, and simultaneously, the transfer of the peak electric field can also greatly improve the reliability and the long-term stability of the device.
The technical scheme of the invention is further described in detail below through examples and with reference to the accompanying drawings. However, the examples are chosen to illustrate the invention only and are not intended to limit the scope of the invention.
Embodiment 1 referring to fig. 8, this embodiment provides a vertical schottky junction barrier diode (Schottky Barrier Diodes, SBDs) comprising the device structure shown in fig. 6 and comprising a heavily doped n-type GaN layer 106a (about 1 μm thick with a doping concentration of about 5 x 10 18/cm3) epitaxially grown on the front side of a GaN self-supporting substrate 107a and an n-type GaN drift region (about 6 μm thick with a doping concentration of about 5 x 10 15/cm3) as a semiconductor body 105 a. The n-type GaN drift region is formed with a high-resistance region 104a by ion implantation, and an electrode 101a (Ni/Au, thickness about 50/150 nm) as an anode is provided on the n-type GaN drift region, and a silicon nitride layer (thickness about 100 nm) as a field plate medium 102a and a field plate metal 103a (Cr/Au, thickness about 100/50 nm) are sequentially deposited on the n-type GaN drift region, and the edge of the field plate metal 103a is seated in the surface region of the high-resistance region 104 a. The GaN self-supporting substrate 107a has a cathode (Ti/Al/Ti/Au, thickness about 20/130/50/150nm, not shown) on its back side.
A method for manufacturing the vertical Schottky junction barrier diode comprises the following steps: before the epitaxial wafer (including the substrate) of the diode is subjected to a wafer flowing process, the epitaxial wafer is cleaned, a Schottky metal is deposited to form the anode, and Schottky contact annealing is performed. Then, photoresist with the thickness of about 2 mu m is adopted as a nitrogen ion implantation mask to carry out selective ion implantation on an n-type GaN drift region in an epitaxial wafer, the energy/dosage of the nitrogen ion implantation is 35keV/1.08×1013cm-2、100keV/6.7×1013cm-2、160keV/1.8×1014cm-2, respectively so as to convert a local region of the n-type GaN drift region into the high-resistance region, photoresist is removed after the ion implantation is finished, a silicon nitride layer is deposited on the whole front surface of the epitaxial wafer to serve as a field plate medium, then, a window is opened on the field plate medium by adopting dry etching and the like to enable the local surface of an anode to be exposed, then field plate metal is deposited, and finally back ohmic contact metal is deposited on the back surface of the epitaxial wafer (namely the back surface of the substrate), so that the cathode is formed.
Comparative example 1 the structure of a vertical schottky junction barrier diode and method for fabricating the same provided in this example are similar to example 1, except that: the aforementioned high-resistance region is not formed in the n-type GaN drift region.
Comparative example 2 the structure of a vertical schottky junction barrier diode and the method for manufacturing the same are similar to example 1, except that: the thickness of the field plate medium is 10nm.
Comparative example 3 the structure of a vertical schottky junction barrier diode and its fabrication method are similar to those of example 1, except that: the thickness of the field plate medium is 1000nm.
Comparative example 4: the structure of the vertical schottky junction barrier diode and the manufacturing method thereof provided in this embodiment are similar to those of embodiment 1, and the difference is that: the ion implantation region is connected with the edge of the main junction of the device.
The performance of SBDs devices finally obtained in example 1, comparative example 1 to comparative example 4 was tested based on the test method of electrical IV, and the results are shown in table 1.
TABLE 1 results of SBDs device Performance test of example 1, comparative example 1-comparative example 3
| Numbering device | Off-state leakage (A/cm 2) | Blocking voltage (V) | On-resistance (mΩ) |
| Example 1 | 1x10-5 | 840 | 1.2 |
| Comparative example 1 | 6x10-5 | 395 | 1.2 |
| Comparative example 2 | 4x10-4 | 410 | 1.2 |
| Comparative example 3 | 3x10-2 | 264 | 1.2 |
| Comparative example 4 | 2 | 668 | 2.3 |
Embodiment 2 referring to fig. 9, this embodiment provides a vertical trench junction barrier schottky diode which also has the device structure shown in fig. 6 and also includes a heavily doped n-type GaN layer 106b (about 1 μm thick with a doping concentration of about 5×10 18/cm3) epitaxially grown on the front side of the GaN self-supporting substrate 107b and an n-type GaN drift region (about 4.4 μm thick with a doping concentration of about 8×10 15/cm3) as the semiconductor body 105 b. The n-type GaN drift region is formed with a high-resistance region 104b by ion implantation, and an electrode 101b (Ni/Au, thickness about 50/150 nm) as an anode is disposed on the n-type GaN drift region, and vertical grooves are formed in regions between both sides of the electrode 101b and the high-resistance region, respectively, of the n-type GaN drift region. In addition, a silicon nitride layer (about 100nm thick) and a field plate metal 103b (Cr/Au, about 100/50nm thick) are sequentially deposited on the n-type GaN drift region as a field plate medium 102b, the field plate medium 102b and the field plate metal 103b continuously and conformally cover the walls of the vertical grooves, and the edges of the field plate metal 103b are located in the surface region of the high-resistance region 104 b. The GaN self-supporting substrate 107b has a cathode (Ti/Al/Ti/Au, thickness about 20/130/50/150nm, not shown) deposited on its back side. The vertical trench junction barrier schottky diode can be prepared in a similar manner to example 1.
Embodiment 3 referring to fig. 10, the present embodiment also provides a vertical schottky junction barrier diode, which has a similar structure and manufacturing method to those of embodiment 1, except that: wherein a p-GaN layer 109 (about 300nm thick with a Mg doping concentration of about 3x 10 19/cm3) grown on an n-type GaN drift region is used as the semiconductor substrate as described above. The p-GaN layer 109 has a high-resistance region 104c formed therein by ion implantation, and an anode 101c (Ni/Au, thickness about 50/150 nm) is provided on the p-GaN layer 109, and a field plate medium 102 and a field plate metal 103 are sequentially deposited on the p-GaN layer 109. The GaN self-supporting substrate 107 has a cathode 108 (Ti/Al/Ti/Au, thickness about 20/130/50/150 nm) deposited on the back side.
Embodiment 4 referring to fig. 11, the present embodiment provides a quasi-vertical schottky barrier diode, which is similar to embodiment 1 in structure and manufacturing method, except that: the epitaxial structure is a <100> Si substrate 107d, the heavily doped n-type GaN layer 106d comprises a stress buffer layer (about 2 μm thick) and a heavily doped n + GaN layer (about 1 μm thick and about 8×10 18/cm3 doping concentration) grown sequentially, the cathode 108d is located on the heavily doped n + GaN layer, and the mesa is formed by ICP deep etching.
Embodiment 5 referring to fig. 12, the present embodiment provides a quasi-vertical type trench junction barrier schottky diode, which is similar to embodiment 1 in structure and manufacturing method, except that: after the anode 101e is manufactured, deep etching is carried out on the n-type GaN drift region by adopting ICP equipment to form a vertical groove with the depth of about 1 mu m, silicon nitride (with the thickness of about 100 nm) is deposited on the whole front surface of an epitaxial wafer by adopting a PEVD mode to serve as a field plate medium, then the operation of ion implantation of a selected region is carried out, thereby forming a high-resistance region 104a in the n-type GaN drift region, photoresist is removed after the ion implantation is finished, then a window is opened on the field plate medium by adopting dry etching and the like to enable the local surface of the anode to be exposed, and then field plate metal (Cr/Au, with the thickness of about 100/50 nm) is deposited; and, the operation of forming a mesa by deep etching the n-type GaN drift region using ICP is also included, and a cathode 108e (ohmic contact metal Ti/Al/Ti/Au, thickness about 20/130/50/150 nm) is located on the heavily doped n-type GaN layer 106 a.
Example 6 referring to fig. 13, this example provides a vertical Fin field effect transistor (Fin-SHAPED FIELD EFFECT transistor, finFET) whose epitaxial structure includes a heavily doped n-type GaN layer 206 (about 1 μm thick with a doping concentration of about 5x 10 18/cm3), an n-type GaN drift region 205 (about 6 μm thick with a doping concentration of about 7x 10 15/cm3) and an n-GaN layer 211 (about 20nm thick with a doping concentration of about 2x 10 18/cm3) epitaxially grown sequentially on a GaN self-supporting substrate 207. The n-type GaN drift region 205 has a high-resistance region 204 formed therein. The top surface of the n-GaN layer is provided with a source 101 (Ti/Au, thickness about 50/150 nm), and the sidewall is provided with a gate dielectric 209 (alumina layer, thickness about 80 nm) and a gate 210 (Ni/Au, thickness about 50/50 nm) in this order. The n-type GaN drift region and the n-GaN layer are sequentially deposited with a silicon nitride layer (about 100nm thick) and a field plate metal 203 (Cr/Au, about 100/50nm thick) as the field plate dielectric 202, and the edges of the field plate metal 203 are located in the surface region of the high-resistance region 204. The GaN self-supporting substrate 207 has a drain 208 (Ti/Al/Ti/Au, thickness about 20/130/50/150 nm) deposited on the back side.
A method for manufacturing the vertical fin field effect transistor upper tube comprises the following steps: before the epitaxial wafer (including the substrate) of the diode is subjected to a wafer flowing process, the epitaxial wafer is cleaned, then a mesa pattern with the width of about 180nm is formed by adopting an electron beam lithography technology, and then a mesa with the depth of about 1 mu m is formed by adopting ICP (inductively coupled plasma) for mesa etching. Source ohmic contact metal is then deposited and ohmic annealed to form source 101. Then, photoresist with the thickness of about 2 μm is adopted as a nitrogen ion implantation mask, after photoresist removal is carried out by N ion implantation with the energy/dose of 35keV/1.08×1013cm-2,100keV/6.7×1013cm-2,160keV/1.8×1014cm-2., a grid medium 209 is formed on the whole surface in a PEALD mode, a grid medium in a non-grid area is removed, grid metal is deposited again to form a grid 210, a field plate medium 202 is deposited on the whole surface in a PECVD mode, a field plate metal 203 is deposited after the field plate medium 202 is windowed, and finally ohmic contact metal is deposited on the back surface of a substrate to form a drain electrode 208.
Embodiment 7 referring to fig. 14, the present embodiment provides a quasi-vertical schottky barrier diode, which has a similar structure and manufacturing method to those of embodiment 4, except that: the epitaxial structure of the diode also includes a p-GaN layer 109f (about 300nm thick with a Mg doping concentration of about 3 x 10 19/cm3) on the n-type GaN drift region 105 f. And the n-type GaN drift region 105f and the p-GaN layer 109f are etched back by ICP to the surface of the heavily doped n-type GaN layer 106f, forming a mesa. The p-GaN layer 109f has a high-resistance region 104f formed therein by ion implantation, and an anode 101f (Ni/Au, thickness about 50/150 nm) is provided on the p-GaN layer 109f, and a field plate medium 102f and a field plate metal 103f are sequentially deposited on the p-GaN layer 109 f. A cathode 108f (ohmic contact metal Ti/Al/Ti/Au, thickness about 20/130/50/150 nm) is located on the heavily doped n-type GaN layer 106 f.
Embodiment 8 referring to fig. 15, the present embodiment provides a quasi-vertical fin field effect transistor upper tube, which has a similar structure and manufacturing method to those of embodiment 6, and is different in that: the n-type GaN drift region 205 is etched back by ICP to the surface of the heavily doped n-type GaN layer 206, forming a mesa. The drain 208a is located on the heavily doped n-type GaN layer 206.
Embodiment 9 referring to fig. 16, the present embodiment provides a vertical schottky barrier diode, which has a similar structure and manufacturing method to those of embodiment 3, except that: wherein the anode 101g and the field plate metal are integrally provided. In the process of manufacturing the vertical schottky barrier diode, a silicon nitride layer is deposited on the whole front surface of the epitaxial wafer as a field plate medium, then a selective ion implantation operation is performed (the energy/dose of nitrogen ion implantation is 35keV/1.08×1013cm-2,100keV/6.7×1013cm-2,160keV/1.8×1014cm-2),, and then a window is opened on the field plate medium by adopting dry etching or the like, so that the area of the surface of the heavily doped n-type GaN layer 106a for setting the anode is exposed, then field plate metal is deposited, and finally back ohmic contact metal is deposited on the back surface of the epitaxial wafer, thereby forming the cathode 108.
In the above embodiment of the present invention, by separating the edge spike electric field of the group III nitride semiconductor longitudinal power electronic device from the spatial position of the leakage channel, the effects of reducing off-state leakage and improving blocking voltage can be achieved at the same time, and the dynamic and static forward electrical properties of the device are effectively ensured, and the reliability and long-term stability of the device are significantly improved.
It should be understood that the above embodiments are merely for illustrating the technical concept and features of the present invention, and are intended to enable those skilled in the art to understand the present invention and implement the same according to the present invention without limiting the scope of the present invention. All equivalent changes or modifications made in accordance with the spirit of the present invention should be construed to be included in the scope of the present invention.
Claims (10)
1. A structure for enhancing off-state electrical characteristics of a vertical power electronic device, comprising:
a semiconductor substrate having a first region and a second region, the first region and the second region being distributed in a direction parallel to a surface of the semiconductor substrate;
The high-resistance region is arranged in the first region of the semiconductor substrate;
The electrode is electrically combined with the surface of the second area of the semiconductor substrate, and the electrode and the high-resistance area are arranged at intervals in the direction parallel to the surface of the semiconductor substrate;
a field plate medium at least continuously covering at least a partial surface of the high-resistance region and a partial surface of the second region of the semiconductor substrate, and at least a partial surface of the electrode is exposed from the field plate medium;
and the field plate metal is continuously covered on the surfaces of the field plate medium and the electrode and is electrically combined with the electrode.
2. The structure for improving the off-state electrical characteristics of a vertical power electronic device according to claim 1, wherein: the high-resistance region is formed by performing selective ion implantation on the first region of the semiconductor substrate.
3. The structure for improving the off-state electrical characteristics of a vertical power electronic device according to claim 1, wherein: the high-resistance region includes a trench structure formed in a first region of the semiconductor substrate and a dielectric material filled in the trench structure.
4. A structure for improving the off-state electrical characteristics of a vertical power electronic device according to any one of claims 1-3, wherein: the thickness of the field plate medium is 20-400 nm; and/or the material of the semiconductor matrix comprises III-nitride, gallium oxide or diamond; and/or the semiconductor body is n-type or p-type; and/or the edge of the field plate metal is arranged on the surface of the high-resistance region.
5. A method of enhancing off-state electrical characteristics of a vertical power electronic device, comprising:
defining a first region and a second region in a semiconductor substrate, wherein the first region and the second region are distributed along a direction parallel to the surface of the semiconductor substrate;
Performing selective ion implantation on the first region of the semiconductor substrate to form a high-resistance region in the first region of the semiconductor substrate,
Or processing a groove-shaped structure in the first area of the semiconductor substrate, and filling a dielectric material in the groove-shaped structure, so that a high-resistance area is formed in the first area of the semiconductor substrate;
providing an electrode on the surface of the second region of the semiconductor substrate, electrically combining the electrode with the semiconductor substrate, and separating the electrode and the high-resistance region from each other in a direction parallel to the surface of the semiconductor substrate;
Continuously covering a field plate medium on at least partial surfaces of the high-resistance region and the second region of the semiconductor substrate, and opening a window on the field plate medium so that at least partial surfaces of the electrodes are exposed from the field plate medium;
And continuously covering field plate metal on the surfaces of the field plate medium and the electrode, and electrically combining the field plate metal with the electrode.
6. The method for improving the off-state electrical characteristics of a vertical power electronic device according to claim 5, comprising the following steps:
Forming a high-resistance region in a first region of the semiconductor substrate, and continuously covering the field plate medium on at least partial surfaces of the high-resistance region and the second region of the semiconductor substrate;
Or a field plate medium is continuously coated on at least partial surfaces of the high-resistance region and the partial surfaces of the second region of the semiconductor substrate, and then the high-resistance region is formed in the first region of the semiconductor substrate by a selective ion implantation mode.
7. The method for improving the off-state electrical characteristics of a vertical power electronic device according to claim 5, comprising the following steps:
Firstly, preprocessing the surface of the semiconductor substrate;
then, continuously covering a field plate medium on at least partial surface of the high-resistance region and partial surface of the second region of the semiconductor substrate;
And then, a window through which the electrode can pass is formed in the field plate medium, an electrode is manufactured at the window, and the high-resistance region is formed in the first region of the semiconductor substrate in a selective ion implantation mode.
8. The method of improving the off-state electrical characteristics of a vertical power electronic device of claim 5, further comprising: the semiconductor base is grown on a substrate comprising any one or a combination of a plurality of silicon substrates, sapphire substrates, silicon carbide substrates, gaN substrates, alN substrates.
9. The method for improving the off-state electrical characteristics of a vertical power electronic device according to claim 5, wherein the thickness of the field plate medium is 20-400 nm; and/or the material of the semiconductor matrix comprises III-nitride, gallium oxide or diamond; and/or the semiconductor body is n-type or p-type; and/or the edge of the field plate metal is arranged on the surface of the high-resistance region.
10. Use of a structure according to any of claims 1-4 or a method according to any of claims 5-9 for the preparation of a vertical power electronic device comprising a vertical diode or a vertical triode.
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