CN118302866A - Semiconductor device and method for manufacturing the same - Google Patents

Semiconductor device and method for manufacturing the same Download PDF

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Publication number
CN118302866A
CN118302866A CN202280077780.2A CN202280077780A CN118302866A CN 118302866 A CN118302866 A CN 118302866A CN 202280077780 A CN202280077780 A CN 202280077780A CN 118302866 A CN118302866 A CN 118302866A
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substrate
layer
semiconductor device
layers
insulating layer
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郝荣晖
黄敬源
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Innoscience Zhuhai Technology Co Ltd
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Innoscience Zhuhai Technology Co Ltd
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0611—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region
    • H01L27/0617—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type
    • H01L27/0629—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration integrated circuits having a two-dimensional layout of components without a common active region comprising components of the field-effect type in combination with diodes, or resistors, or capacitors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/8258—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using a combination of technologies covered by H01L21/8206, H01L21/8213, H01L21/822, H01L21/8252, H01L21/8254 or H01L21/8256
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/107—Substrate region of field-effect devices
    • H01L29/1075—Substrate region of field-effect devices of field-effect transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7786—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with direct single heterostructure, i.e. with wide bandgap layer formed on top of active layer, e.g. direct single heterostructure MIS-like HEMT
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1066—Gate region of field-effect devices with PN junction gate
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds
    • H01L29/2003—Nitride compounds
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8613—Mesa PN junction diodes

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Abstract

The semiconductor device includes a substrate, an insulating layer, and a plurality of epitaxial structures. The substrate includes a first substrate layer and a plurality of second substrate layers. The first substrate layer is doped with a p-type dopant. The second substrate layer is doped with an n-type dopant and disposed over the first substrate layer. A p-n junction is formed between each of the second substrate layer and the first substrate layer. The insulating layer is disposed over the second substrate layers such that each second substrate layer has a first region covered by the insulating layer and a second region not covered by the insulating layer. The plurality of epitaxial structures are respectively and directly arranged on the second area of the second substrate layer, so that each epitaxial structure is limited by the insulating layer.

Description

Semiconductor device and method for manufacturing the same
Technical Field
The present invention relates generally to nitride-based semiconductor devices. More particularly, the present invention relates to a nitride-based semiconductor device having a substrate integrated with at least one p-n junction/diode.
Background
In recent years, a great deal of research has been conducted on High Electron Mobility Transistors (HEMTs), particularly for high power switches and high frequency applications. Group III nitride based HEMTs utilize a heterojunction interface between two materials with different bandgaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2 DEG) region, meeting the requirements of high power/high frequency devices. Examples of devices having a heterostructure include Heterojunction Bipolar Transistors (HBTs), heterojunction Field Effect Transistors (HFETs), and modulation doped FETs (MODFETs) in addition to HEMTs.
Disclosure of Invention
According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a substrate, an insulating layer, and a plurality of epitaxial structures. The substrate includes a first substrate layer and a plurality of second substrate layers. The first substrate layer is doped with a p-type dopant. The plurality of second substrate layers are doped with n-type dopants and disposed over the first substrate layers. The plurality of second substrate layers are in contact with the first substrate layer such that a p-n junction is formed between each of the plurality of second substrate layers and the first substrate layer. The insulating layer is disposed over the plurality of second substrate layers such that each of the plurality of second substrate layers has a first region covered by the insulating layer and a second region not covered by the insulating layer. The epitaxial structures are disposed directly over the second regions of the plurality of second substrate layers, respectively, such that each of the plurality of epitaxial structures is defined by the insulating layer.
According to one aspect of the present disclosure, a method for manufacturing a semiconductor device is provided. The method comprises the following steps. A substrate is formed that includes a first substrate layer and a plurality of second substrate layers over the first substrate layer. The first substrate layer is p-doped and the plurality of second substrate layers is n-doped. An insulating layer is formed over the plurality of second substrate layers such that each of the plurality of second substrate layers has a non-device region covered by the insulating layer and a device region not covered by the insulating layer. The plurality of epitaxial structures are respectively formed on the device regions of the plurality of second substrate layers such that each of the plurality of epitaxial structures is defined by the insulating layer.
According to one aspect of the present disclosure, a semiconductor device is provided. The semiconductor device includes a substrate, an insulating layer, and a plurality of buffer layers. The substrate has a first portion and a plurality of second portions located over the first portion. The first portions have a first conductivity type and each second portion has a second conductivity type opposite the first conductivity type. The insulating layer is arranged above the first part and the second part, and the insulating layer is provided with a plurality of through holes respectively positioned right above the second parts. A plurality of buffer layers are disposed over the plurality of second portions, respectively. Each of the plurality of buffer layers contacts a corresponding second portion through a corresponding via of the insulating layer, and each of the plurality of buffer layers is defined by the insulating layer.
With the above configuration, in the present invention, the substrate includes the substrate layers of two different conductivity types. A second substrate layer having a second conductivity type is disposed on/over/on the first substrate layer having the first conductivity type such that a p-n junction/diode is formed across each second substrate layer and the first substrate layer. In this way, a substrate integrated with a plurality of p-n diodes can be realized. With such a structure, the voltage resistance in the vertical direction of the semiconductor device can be improved. Accordingly, the semiconductor device of the present disclosure is suitable for high voltage operation.
Drawings
Aspects of the disclosure can be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that the various features may not be drawn to scale. That is, the dimensions of the various features may be arbitrarily increased or decreased for clarity of discussion. Embodiments of the invention are described in more detail below with reference to the attached drawing figures, wherein:
Fig. 1A is a top view of a semiconductor device according to some embodiments of the present disclosure;
FIG. 1B is a vertical cross-sectional view of the semiconductor device taken along line A-A' in FIG. 1A;
FIG. 1C is an enlarged vertical cross-sectional view of region A of FIG. 1A;
Fig. 2A, 2B, 2C, 2D, 2E, and 2F illustrate different stages of a method for fabricating a semiconductor device according to some embodiments of the present disclosure;
fig. 3 is a top view of a semiconductor device according to some embodiments of the present disclosure;
Fig. 4 is a top view of a semiconductor device according to some embodiments of the present disclosure;
Fig. 5 is a top view of a semiconductor device according to some embodiments of the present disclosure;
fig. 6A is a top view of a semiconductor device according to some embodiments of the present disclosure; and
Fig. 6B is a vertical cross-sectional view of the semiconductor device taken along line E-E' in fig. 6A.
Detailed Description
The same reference indicators will be used throughout the drawings and the detailed description to refer to the same or like parts. Embodiments of the present disclosure will be readily understood by the following detailed description in conjunction with the accompanying drawings.
Spatial descriptors, such as "upper," above, "" below, "" upward, "" left, "" right, "" downward, "" top, "" bottom, "" vertical, "" horizontal, "" side, "higher," "lower," "upper," "above," "below," etc., are described with respect to a component or group of components, or with respect to a plane of the component or group of components, for describing the orientation of one or more components shown in the relevant figures. It should be understood that the spatial descriptors used herein are for illustrative purposes only, and that the actual implementation of the structures described herein may be spatially arranged in any direction or manner so long as such arrangement does not depart from the advantages of the embodiments of the present disclosure.
Further, it should be noted that the actual shape of the various structures depicted as being approximately rectangular may be curved, have rounded edges, have slightly uneven thickness, etc. in an actual device due to device manufacturing conditions. Straight lines and right angles are used for convenience only to represent layers and features.
In the following description, a semiconductor device/die/package, a method of manufacturing the same, and the like are set forth as preferred examples. It will be apparent to those skilled in the art that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the disclosure. Specific details may be omitted in order not to obscure the disclosure; however, the disclosure is written to enable any person skilled in the art to practice the teachings herein without undue experimentation.
In order to realize a high-voltage device, a silicon substrate (HR silicon substrate) having a high resistance may be introduced into the device to improve the withstand voltage of the device in the vertical direction. Due to the polarization effect, an electron inversion layer is formed at the interface between the aluminum nitride buffer layer and the silicon substrate. However, when a high voltage is applied to such a device, a leakage current problem occurs at the edges of the aluminum nitride buffer layer and the silicon substrate, resulting in leakage current flowing from the inversion layer to the edges, and thus resulting in poor reliability of the device.
On the other hand, applying a thicker buffer layer to the device can also improve the withstand voltage of the device in the vertical direction. However, this approach may result in an increase in the thickness of the device, which is not consistent with the trend toward miniaturization of electronic devices. Additional stress problems can occur due to the thicker buffer layer.
At least to avoid the above problems, the present invention aims to develop a novel semiconductor device structure. The detailed structure/arrangement will be described in detail below.
Fig. 1A is a top view of a semiconductor device 1A according to some embodiments of the present disclosure. Fig. 1B is a vertical sectional view of the semiconductor device 1A taken along the line A-A' in fig. 1A. The semiconductor device 1A includes a substrate 10A, an insulating layer 20, and a plurality of epitaxial structures 30.
In order to increase the pressure resistance of the semiconductor device 1A in the vertical direction, the substrate 10A of the present disclosure adopts a novel structure.
Specifically, referring to fig. 1A and 1B, the substrate 10A includes a substrate layer 102A and a plurality of substrate layers 104A. Substrate layer 102A may be part of substrate 10A and substrate layer 104A may be another part of substrate 10A. The substrate layer 104A is disposed on/over/above the substrate layer 102A such that the upper surface 1042 of the substrate layer 104A is higher than the upper surface 1022 of the substrate layer 102A. The substrate layer 104A is disposed on/over the substrate layer 102A in an array (as shown in fig. 1A). The substrate layer 104A is patterned into rectangular islands from a top view of the semiconductor device 1A in fig. 1A.
An exemplary material for substrate 10A may include silicon. The silicon substrate 10A has a <111> orientation. The substrate layer 102A is doped with a p-type dopant, where the p-type dopant may include a group III element, such as boron (B) and gallium (Ga). Each substrate layer 104A is doped with an n-type dopant, where the n-type dopant may include a group V element, such As phosphorus (P), arsenic (As), or antimony (Sb). Thus, the substrate layers 102A are doped to have a P conductivity type, and each of the substrate layers 104A is doped to have an N conductivity type opposite to the P conductivity type.
The substrate layers 104A are disposed on/over/above the substrate layers 102A such that each substrate layer 104A may be in contact with the substrate layer 102A, thereby forming a p-n junction PN (i.e., a p-n diode) between each substrate layer 104A and the substrate layer 102A. By configuring the substrate layer 102A and the substrate layer 104A to be of different conductivity types, the substrate 10A may be integrated with a plurality of p-n diodes/junctions PN.
Insulating layer 20 is disposed on/over substrate layer 102A and substrate layer 104A. Insulating layer 20 covers substrate layer 102A and substrate layer 104A. The insulating layer 20 together with the substrate layer 104A covers the entire upper surface 1022 of the substrate layer 102A.
For each substrate layer 104A, the region R1 of the substrate layer 104A that is covered by the insulating layer 20 is defined as a non-device region, and the region R2 of the substrate layer 104A that is not covered by the insulating layer 20 is defined as a device region, wherein the device region is a region on the substrate 10A where the epitaxial structure 30 is to be formed. The insulating layer 20 has a plurality of through holes TH. The region R2 of the substrate layer 104A is defined by the through holes TH of the insulating layer 20. The definition of the region R2 by the through holes TH includes a dimension, such as an area, a width, or a length, of the region R2.
The insulating layer 20 extends to an area between any two adjacent substrate layers 104A such that the plurality of substrate layers 104A of the substrate 10A are spaced apart from one another by the insulating layer 20. At least a portion of insulating layer 20 is in contact with any two adjacent substrate layers 104A.
The insulating layer 20 may include, but is not limited to, for example, siO x、Si3N4, siON, siC, siBN, siCBN, oxide, nitride, plasma Enhanced Oxide (PEOX), or combinations thereof. In some embodiments, the insulating layer 20 may be a multi-layer structure, such as a composite dielectric layer of Al 2O3/SiN, a composite dielectric layer of Al 2O3/silicon dioxide (SiO 2), a composite dielectric layer of aluminum nitride (AlN)/silicon nitride (SiN), a composite dielectric layer of aluminum nitride/silicon dioxide (SiO 2), or a combination thereof. In the present embodiment, the insulating layer 2 includes SiO 2.
The epitaxial structures 30 are each disposed directly over a region R2 of the substrate layer 104A such that each of the plurality of epitaxial structures 30 is bounded by the insulating layer 20. The width of each epitaxial structure 30 is less than the width of the corresponding substrate layer 104A. The orthographic projection of each epitaxial structure 30 onto substrate layer 102A falls entirely within the orthographic projection of the corresponding substrate layer 104A onto substrate layer 102A. The plurality of epitaxial structures 30 are separated from one another by insulating layers 20.
Here, "epitaxial structure 30 is limited by insulating layer 20" includes limiting the growth area of epitaxial structure 30. Thus, when growth is complete, epitaxial structures 30 may be separated from each other. For epitaxial structures without the above-mentioned insulating layer 20, these epitaxial structures may be separated from each other by performing at least one etching process, which may damage sidewalls of the epitaxial structures. The damaged sidewall may cause leakage current problems because leakage current tends to flow through the damaged sidewall. Furthermore, by limiting the growth area of epitaxial structure 30, epitaxial structure 30 may be grown as small blocks/islands, such that the stress built up therein, as well as lattice defects therein, may be reduced.
Specifically, each epitaxial structure 30 of the plurality of epitaxial structures 30 includes a buffer layer 302, a nitride-based semiconductor layer 304, and a nitride-based semiconductor layer 306. The buffer layer 302 is disposed between the substrate layer 104A of the substrate 10A and the nitride-based semiconductor layer 302. Buffer layer 302 is disposed on/over the corresponding substrate layer 104A. The width of the buffer layer 302 is smaller than the width of the corresponding substrate layer 104A. Buffer layer 302 is thicker than insulating layer 20 on the corresponding substrate layer 104A such that the upper surface of buffer layer 302 is higher than the upper surface of insulating layer 20.
Each buffer layer 302 penetrates the insulating layer 20 through the corresponding through hole TH to be in contact with the corresponding substrate layer 104A, thereby forming an interface IF1 between the buffer layer 302 and the substrate layer 104A. Thus, each of the buffer layers 302 is bounded by the insulating layer 20. More specifically, each of the buffer layers 302 abuts against the inner side surface of the insulating layer 20. The insulating layer 20 extends from a side surface 3022 of the insulating layer 20 along the upper surface 1042 and the side surface 1044 of the substrate layer 104A to the upper surface 1022 of the substrate layer 102A. Thus, the interface IF1 between the buffer layer 302 and the substrate layer 104A is within the thickness T of the insulating layer 20.
The buffer layer 302 may be configured to reduce lattice mismatch and thermal mismatch between the substrate layer 104A and the nitride-based semiconductor layer 302, thereby eliminating defects due to mismatch/variance. Buffer layer 302 may include a III-V compound. The III-V compounds may include, for example, but are not limited to, aluminum, gallium, indium, nitrogen, or combinations thereof. Thus, exemplary materials for buffer layer 302 may also include, for example, but are not limited to GaN, alN, alGaN, inAlGaN or combinations thereof.
In this embodiment, the material of the buffer layer 302 may be selected to be AlN. When a high voltage is applied to such a semiconductor device 1A, an inversion layer of electrons is formed at the interface IF1 between the AlN buffer layer 302 and the silicon substrate layer 104A due to polarization effect. Since the side surface 3022 of the buffer layer 302 is spaced apart from the side surface 1044 of the substrate layer 104A, a possible leakage current path is cut off. In this regard, once the sidewalls of two stacked layers are connected to each other, leakage current tends to flow from one sidewall to the other sidewall as the sidewalls may have more defects. Accordingly, since the insulating layer 20 can indirectly restrict the position of the inversion layer of electrons (i.e., the side 3022 of the buffer layer 302 is spaced apart from the side 1044 of the substrate layer 104A), current leakage from the side surface 3022 of the buffer layer 302 to the side surface 1044 of the substrate layer 104A can be reduced, thereby improving the reliability of the semiconductor device 1A. Therefore, the semiconductor device 1A is suitable for high-voltage operation. In addition, since the side surface 3022 of the buffer layer 302 can be formed without etching, there are fewer defects with respect to the side wall defined by the etching method.
In some embodiments, epitaxial structure 30 may also include a nucleation layer (not shown). A nucleation layer may be formed between the substrate layer 104A and the buffer layer 302. The nucleation layer may be configured to provide a transition to accommodate the mismatch/difference between the substrate layer 104A and the group III nitride layer of the buffer layer. Exemplary materials for the nucleation layer may include, for example, but are not limited to, alN or any alloy thereof.
A nitride-based semiconductor layer 304 is disposed on/over the buffer layer 302. The nitride-based semiconductor layer 306 is disposed on/over the nitride-based semiconductor layer 304. Exemplary materials for nitride-based semiconductor 304 may include, for example, but are not limited to: nitrides or III-V compounds, for example GaN, alN, inN, in xAlyGa_(1–x–y) N, where x+y.ltoreq.1, al yGa(1-y) N, where y.ltoreq.1. Exemplary materials for nitride-based semiconductor layer 306 may include, for example, but are not limited to: nitrides or III-V compounds, for example GaN, alN, inN, in xAlyGa(1–x–y) N, where x+y.ltoreq.1, al y Ga(1–y) N, where y.ltoreq.1.
The exemplary materials of nitride-based semiconductor layers 304 and 306 are selected such that the bandgap of nitride-based semiconductor layer 306 (i.e., the forbidden bandwidth) is greater than the bandgap of nitride-based semiconductor layer 304, which results in their electron affinities being different from each other and forming a heterojunction between them. For example, when nitride-based semiconductor layer 304 is an undoped gallium nitride (GaN) layer having a bandgap of about 3.4eV, nitride-based semiconductor layer 306 may be an aluminum gallium nitride (AlGaN) layer having a bandgap of about 4.0 eV. In this way, the nitride-based semiconductor layers 304 and 306 can function as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the bonding interface between the channel layer and the barrier layer such that electrons accumulate in the triangular well, thereby creating a two-dimensional electron gas (2 DEG) region near the heterojunction. Accordingly, the semiconductor device 1A may include at least one GaN-based high electron mobility transistor TR (HEMT).
Electrodes E1 and E2 are disposed on/over the nitride-based semiconductor layer 306. The electrodes E1 and E2 may be in contact with the nitride-based semiconductor layer 306. In some embodiments, electrode E1 may serve as a source electrode. In some embodiments, electrode E2 may act as a drain. In some embodiments, electrode E1 may serve as a source electrode. In some embodiments, electrode E2 may act as a drain. The role of electrodes E1 and E2 depends on the design of the device.
In some embodiments, electrodes E1 and E2 may include, for example, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. Exemplary materials for electrodes E1 and E2 may include, for example, but are not limited to: titanium (Ti), alSi, titanium nitride (TiN), or a combination thereof. Each of the electrodes E1 and E2 may be a single layer or a plurality of layers having the same or different compositions. The electrodes E1 and E2 form ohmic contacts with the nitride-based semiconductor layer 306. In addition, ohmic contact may be achieved by applying Ti, al, or other suitable materials to the electrodes E1 and E2.
In some embodiments, each of the electrodes E1 and E2 is formed of at least one conformal layer and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials for the conformal layer may include, for example, but are not limited to Ti, ta, tiN, al, au, alSi, ni, pt or combinations thereof. Exemplary materials for the conductive filler may include, for example, but are not limited to AlSi, alCu, or combinations thereof.
The doped nitride-based semiconductor layer 50 is disposed on/over/above the nitride-based semiconductor layer 306. The doped nitride-based semiconductor layer 50 is in contact with the nitride-based semiconductor layer 306. The gate electrode 52 is disposed on/over the doped nitride-based semiconductor layer 50 and the nitride-based semiconductor layer 306. The gate electrode 52 is in contact with the doped nitride-based semiconductor layer 50. The doped nitride-based semiconductor layer 50 is disposed between the gate electrode 52 and the nitride-based semiconductor layer 306.
The gate electrode 52 is narrower than the doped nitride-based semiconductor layer 30. In some embodiments, the width of the doped nitride-based semiconductor layer 50 is substantially the same as the width of the gate electrode 52. The profile of the doped nitride-based semiconductor layer 50 and the profile of the gate electrode 52 are identical, e.g., they are both rectangular profiles. In other embodiments, the profile of the doped nitride-based semiconductor layer 50 and the profile of the gate electrode 52 may be different from each other. For example, the profile of the doped nitride-based semiconductor layer 50 may be a trapezoidal profile and the profile of the gate electrode 52 may be a rectangular profile.
In the exemplary illustration of fig. 1B, transistor TR of semiconductor device 1A is an enhancement device that is in a normally-off state when gate electrode 52 is at about zero bias. Specifically, the doped nitride-based semiconductor layer 50 may form at least one p-n junction with the nitride-based semiconductor layer 306 to deplete the 2DEG region such that at least one region of the 2DEG region corresponding to a location below the corresponding gate 52 has different characteristics (e.g., different electron concentration) than the rest of the 2DEG region, and is thus blocked.
Due to this mechanism, the transistor TR of the semiconductor device 1A has normally-off characteristics. In other words, when no voltage is applied to the gate electrode 52 or the voltage applied to the gate electrode 52 is less than the threshold voltage (i.e., the minimum voltage required to form an inversion layer under the gate electrode 52), the 2DEG region remains blocked at the region under the gate electrode 52, and thus no current flows.
In some embodiments, the doped nitride-based semiconductor layer 50 may be omitted such that the transistor TR of the semiconductor device 1A is a depletion device, which means that the transistor TR of the semiconductor device 1A is in a normally-on state at zero gate-source voltage.
The doped nitride-based semiconductor layer 50 may be a p-type III-V doped semiconductor layer. Exemplary materials for doped nitride-based semiconductor layer 50 may include, for example, but are not limited to, p-doped group III-V nitride semiconductor materials, such as p-type GaN, p-type AlGaN, p-type InN, p-type AlInN, p-type InGaN, p-type AlInGaN, or combinations thereof. In some embodiments, the p-doped material is achieved by using p-type impurities such as Be, zn, cd, and Mg. In some embodiments, nitride-based semiconductor layer 304 comprises undoped GaN and nitride-based semiconductor layer 306 comprises AlGaN, doped nitride-based semiconductor layer 50 is a p-type GaN layer that can bend the underlying band structure upward and deplete the corresponding region of the 2DEG region, thereby placing transistor TR of semiconductor device 1A in an off state.
Exemplary materials for gate electrode 52 may include metals or metal compounds. The gate electrode 52 may be formed as a single layer or multiple layers having the same or different compositions. Exemplary materials for the metal or metal compound may include, for example, but are not limited to W, au, pd, ti, ta, co, ni, pt, mo, tiN, taN, metal alloys or compounds thereof, or other metal compounds.
In the present disclosure, the epitaxial structure 30 is disposed/formed on the substrate 10A integrated with the p-n diode/p-n junction PN, and each of the plurality of epitaxial structures 30 is electrically coupled/connected to the corresponding p-n diode/p-n junction PN. In some embodiments, electrode E1 (as the source) and substrate 10A may be electrically connected to the same ground voltage, while electrode E2 (as the drain) may be electrically connected to a drain voltage that is higher than the ground voltage. During such operation, the p-n diode/p-n junction PN is reverse biased, and when the transistor TR of the semiconductor device 1A is in a normally-off state, the p-n diode/p-n junction PN can share a part of the voltage, thereby improving the withstand voltage of the transistor TR of the semiconductor device 1A.
Fig. 1C is an enlarged vertical cross-sectional view of region a of fig. 1A. Referring to fig. 1C, the substrate layer 102A and each substrate layer 104A collectively form a depletion region DPR. In this embodiment, the doping concentration of the p-type dopant of the substrate layer 102A is different from the doping concentration of the n-type dopant of the substrate layer 104A. Thus, the thickness T1 of the depletion region DPR in the substrate layer 102A is different from the thickness T2 of the depletion region DPR in the substrate layer 104A.
For example, the doping concentration of the p-type dopant of substrate layer 102A is greater than the doping concentration of the n-type dopant of substrate layer 104A. Thus, substrate layer 102A may also be referred to as a p+ substrate layer/region, and substrate layer 104A may also be referred to as an n-substrate layer/region. Thickness T1 is greater than thickness T2. By adjusting the ratio of the doping concentrations of the p-type dopant and the n-type dopant, the electrical performance of the p-n diode/p-n junction PN in the substrate 10A can be adjusted accordingly for best results.
Fig. 2A, 2B, 2C, 2D, 2E, and 2F described below illustrate different stages of a method for manufacturing the semiconductor device 1A. Hereinafter, deposition techniques may include, for example, but are not limited to, atomic Layer Deposition (ALD), physical Vapor Deposition (PVD), chemical Vapor Deposition (CVD), metal Organic CVD (MOCVD), plasma Enhanced CVD (PECVD), low Pressure CVD (LPCVD), plasma-assisted vapor deposition, epitaxial growth, or other suitable processes.
Referring to fig. 2A, a p-doped intermediate substrate 60 is provided.
Referring to fig. 2B, an ion implantation process is performed on the p-type doped intermediate substrate 60 using an n-type dopant such that the top 62 of the intermediate substrate 60 is doped n-type and the bottom 64 of the intermediate substrate 60 is still p-type doped as the first substrate layer 102A of the substrate 10A. The implantation depth is determined according to the device withstand voltage requirements. A thermal annealing process is then performed during the steps of the ion implantation process to activate the n-type dopants in the top portion 62 and the p-type dopants in the bottom portion 64.
Referring to fig. 2C, the top 62 of the intermediate substrate 60 is patterned into a plurality of physically separated layers/islands/blocks to serve as the plurality of substrate layers 104A of the substrate 10A. Thereby, the substrate 10A including the substrate layer 102A and the plurality of second substrate layers 104A is formed.
Referring to fig. 2D, a cover insulating layer 70 is formed to cover the substrate layer 102A and the substrate layer 104A. The cover insulating layer 70 is subjected to a patterning process to define a plurality of device regions DR on the plurality of substrate layers 104A, respectively. Then, an insulating layer 104 having a plurality of through holes TH is formed. Each device region DR of the substrate layer 104A is defined as a region of the substrate layer 104A not covered by the insulating layer 104. In contrast, each non-device region NDR of the substrate layer 104A is defined as the area of the substrate layer 104A that is covered by the insulating layer 104.
Referring to fig. 2E, a plurality of epitaxial structures 30 are respectively formed on a plurality of device regions DR of the substrate layer 104A such that each epitaxial structure 30 is defined by the insulating layer 20. Specifically, a plurality of buffer layers 302 are formed in the plurality of device regions DR, respectively. A plurality of nitride-based semiconductor layers 304 are respectively located on the buffer layer 302. A plurality of nitride-based semiconductor layers 306 are respectively located on the nitride-based semiconductor layers 304. Each nitride-based semiconductor layer 306 has a different band gap than nitride-based semiconductor layer 304. Thereafter, electrodes E1, E2, a doped nitride-based semiconductor layer 50, and a gate electrode 52 are formed. Thus, the semiconductor device 1A in fig. 1A and 1B is obtained.
Fig. 3 is a top view of a semiconductor device 1B according to some embodiments of the present disclosure. The semiconductor device 1B is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A, except that the substrate layer 104B is patterned into circular islands.
Fig. 4 is a top view of a semiconductor device 1C according to some embodiments of the present disclosure. The semiconductor device 1C is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A, except that the substrate layer 104C is patterned into a stripe shape.
Fig. 5 is a top view of a semiconductor device 1D according to some embodiments of the present disclosure. The semiconductor device 1D is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A, except that the substrate layer 104D is patterned into hexagonal islands.
That is, different patterns in the substrate layers 104A, 104B, 104C, 104D may provide different design parameters for the device, such as pitch, width, or diameter. In this way, the semiconductor devices 1A, 1B, 1C, 1D, 1E may be further tuned to the above design parameters to obtain the best results.
Fig. 6A is a top view of a semiconductor device 1E according to some embodiments of the present disclosure. Fig. 6B is a vertical sectional view of the semiconductor device 1E taken along line E-E' in fig. 6A. The semiconductor device 1E is similar to the semiconductor device 1A described and illustrated with reference to fig. 1A, except that the portion P1 of the substrate layer 104E1 has a wider width/larger area, and the other portion P2 of the substrate layer 104E2 has a smaller width/smaller area. Epitaxial structures 30E1, 30E2 having different areas are defined by forming substrate layers 104E1, 104E2 having different areas. More specifically, the boundaries of the epitaxial structures 30E1, 30E2 may be defined by the isolation layer 20E without etching, and thus different regions of the epitaxial structures 30E1, 30E2 may not undergo etching.
Based on the above description, the present invention can electrically couple each epitaxial structure on the device region with a corresponding p-n junction/diode by forming p-n junctions/p-n diodes in a plurality of device regions of the substrate, respectively, thereby improving the voltage resistance of the semiconductor device without thickening the buffer layer. In addition, the epitaxial structure is separated into smaller blocks/islands by the insulating layer, and thus stress accumulated therein can be reduced, thereby reducing lattice defects therein. Therefore, the semiconductor device of the present invention can accommodate high voltage operation and has good reliability.
The embodiments were chosen and described in order to best explain the principles of the disclosure and its practical application, to thereby enable others skilled in the art to understand the disclosure for various embodiments and with various modifications as are suited to the particular use contemplated.
As used herein and not otherwise defined, the terms "substantially," "about," and "approximately" are used to describe and explain minor variations. When used in connection with an event or circumstance, the terms can encompass instances where the event or circumstance occurs precisely and instances where the event or circumstance occurs very closely. For example, when used in conjunction with a numerical value, these terms may encompass a variation of less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces lying within a few microns near the same plane, for example within 40 μm, within 30 μm, within 20 μm, within 10 μm, or within 1 μm near the same plane.
As used herein, the singular terms "a," "an," and "the" may include plural referents unless the context clearly dictates otherwise. In the description of some embodiments, an element disposed "on" or "over" another element may encompass the situation in which the former element is directly on (e.g., in physical contact with) the latter element, as well as the situation in which one or more intermediate elements are located between the former element and the latter element.
While the present disclosure has been depicted and described with reference to particular embodiments thereof, such depicted and described are not meant to be limiting. It will be understood by those skilled in the art that various changes may be made and equivalents substituted without departing from the true spirit and scope of the disclosure as defined by the appended claims. The illustrations are not necessarily drawn to scale. There may be differences between artistic manifestations in the present disclosure and actual devices due to manufacturing processes and tolerances. Furthermore, it should be understood that the actual devices and layers may deviate from the rectangular layer depictions in the drawings. And may include angled surfaces or edges, rounded corners, etc. due to manufacturing processes such as conformal deposition, etching, etc. Other embodiments not specifically shown may exist in the present disclosure. The specification and drawings are to be regarded in an illustrative rather than a restrictive sense. Modifications may be made to adapt a particular situation, material, composition of matter, method or process to the objective, spirit and scope of the present disclosure. All such modifications are intended to fall within the scope of the appended claims. Although the methods disclosed herein have been described with reference to particular operations being performed in a particular order, it should be understood that these operations may be combined, sub-divided, or reordered to form an equivalent method without departing from the teachings of the present invention. Accordingly, unless specifically indicated herein, the order and grouping of operations is not limited.

Claims (25)

1. A semiconductor device, comprising:
A substrate, comprising:
A first substrate layer doped with a p-type dopant; and
A plurality of second substrate layers doped with n-type dopants and disposed over the first substrate layer, wherein the plurality of second substrate layers are in contact with the first substrate layer such that a p-n junction is formed between each of the plurality of second substrate layers and the first substrate layer;
An insulating layer disposed over the plurality of second substrate layers such that each of the plurality of second substrate layers has a first region covered by the insulating layer and a second region not covered by the insulating layer; and
The plurality of epitaxial structures are respectively arranged right above the plurality of second areas of the plurality of second substrate layers, so that each epitaxial structure in the plurality of epitaxial structures is limited by the insulating layer.
2. The semiconductor device of claim 1, wherein a width of each epitaxial structure of the plurality of epitaxial structures is less than a width of a corresponding second substrate layer.
3. The semiconductor device of claim 1, wherein an orthographic projection of each epitaxial structure of the plurality of epitaxial structures onto the first substrate layer falls entirely within an orthographic projection of a corresponding second substrate layer onto the first substrate layer.
4. The semiconductor device according to claim 1, wherein the insulating layer and the plurality of second substrate layers cover an entire upper surface of the first substrate layer.
5. The semiconductor device of claim 1, wherein at least a portion of the insulating layer is in contact with any two adjacent second substrate layers.
6. The semiconductor device of claim 1, wherein the substrate comprises a silicon substrate.
7. The semiconductor device of claim 1, wherein the p-type dopant comprises a group III element.
8. The semiconductor device of claim 1, wherein the n-type dopant comprises a group V element.
9. The semiconductor device of claim 1, wherein a doping concentration of the p-type dopants of the first substrate layer is greater than a doping concentration of the n-type dopants of the plurality of second substrate layers.
10. The semiconductor device of claim 1, wherein the second substrate layers are arranged in an array.
11. The semiconductor device of claim 1, wherein the insulating layer comprises silicon oxide.
12. The semiconductor device of claim 1, wherein each epitaxial structure of the plurality of epitaxial structures comprises:
A buffer layer disposed over the corresponding second substrate layer;
a first nitride-based semiconductor layer disposed over the buffer layer;
A second nitride-based semiconductor layer disposed over the first nitride-based semiconductor layer and having a bandgap different from that of the first nitride-based semiconductor layer.
13. The semiconductor device according to claim 12, wherein the insulating layer extends from a side surface of the buffer layer to an upper surface of the first substrate layer along an upper surface and a side surface of the second substrate layer.
14. The semiconductor device of claim 12, wherein the buffer layer is thicker than the insulating layer on the corresponding second substrate layer.
15. The semiconductor device of claim 12, wherein a width of the buffer layer is less than a width of the corresponding second substrate layer.
16. A method of manufacturing a semiconductor device, comprising:
forming a substrate, wherein the substrate comprises a first substrate layer and a plurality of second substrate layers on the first substrate layer, the first substrate layer is doped with p type, and the plurality of second substrate layers are doped with n type;
Forming an insulating layer on the plurality of second substrate layers such that each of the plurality of second substrate layers has a non-device region covered by the insulating layer and a device region not covered by the insulating layer; and
A plurality of epitaxial structures are formed on the device regions of the plurality of second substrate layers, respectively, such that each epitaxial structure of the plurality of epitaxial structures is defined by the insulating layer.
17. The method of claim 16, wherein forming the substrate further comprises:
Performing an ion implantation process on a p-type doped intermediate substrate, so that the top of the intermediate substrate is doped n-type, the bottom of the intermediate substrate is still p-type doped and serves as the first substrate layer of the substrate; and
The top of the intermediate substrate is patterned into a plurality of physically separate layers as the plurality of second substrate layers of the substrate.
18. The method of claim 17, further comprising:
a thermal annealing process is performed during the step of performing the ion implantation process.
19. The method of claim 16, wherein forming the insulating layer further comprises:
Forming a cover insulating layer to cover the first substrate layer and the plurality of second substrate layers; and
And patterning the covering insulating layer to define the device regions on the second substrate layers respectively.
20. The method of claim 16, wherein forming the plurality of epitaxial structures further comprises:
forming a plurality of buffer layers in the device region, respectively;
forming a plurality of first nitride-based semiconductor layers on the plurality of buffer layers, respectively; and
And forming a plurality of second nitride-based semiconductor layers on the plurality of first nitride-based semiconductor layers, respectively, wherein each of the second nitride-based semiconductor layers has a band gap different from that of the first nitride-based semiconductor layer.
21. A semiconductor device, comprising:
a substrate having a first portion and a plurality of second portions over the first portion, wherein the first portion has a first conductivity type, each of the plurality of second portions has a second conductivity type opposite the first conductivity type;
An insulating layer disposed over the first portion and the plurality of second portions and having a plurality of through holes respectively located directly over the plurality of second portions; and
And a plurality of buffer layers respectively arranged above the second parts, wherein each buffer layer penetrates through the insulating layer through a corresponding through hole to be in contact with the corresponding second part, and each buffer layer is limited by the insulating layer.
22. The semiconductor device of claim 21, wherein each of the first portion and the plurality of second portions collectively form a depletion region, and a thickness of the depletion region in the first portion is different from a thickness of the depletion region in the second portion.
23. The semiconductor device of claim 21, wherein an interface is formed between the buffer layer and the corresponding second portion, and the interface is within a thickness of the insulating layer.
24. The semiconductor device of claim 21, wherein the insulating layer extends into a region between any two adjacent second portions such that the plurality of second portions of the substrate are spaced apart from one another by the insulating layer.
25. The semiconductor device according to claim 21, wherein an upper surface of the second portion is higher than an upper surface of the first portion.
CN202280077780.2A 2022-07-15 2022-07-15 Semiconductor device and method for manufacturing the same Pending CN118302866A (en)

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