CN118299417A - Silicon carbide semiconductor element - Google Patents

Abstract

A silicon carbide semiconductor device comprises a silicon carbide substrate, a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a plurality of trenches and a gate electrode. The first doped region is disposed in the drift layer and forms a plurality of first p-n junctions and a plurality of JFET regions with the drift layer. The second doped region is disposed within the first doped region and forms a plurality of second p-n junctions with the first doped region. The third doped region is disposed in the first doped region and adjacent to the second doped region. The trench penetrates from the main surface into the drift layer and extends horizontally through at least a portion of the JFET region. The gate electrode is disposed on the main surface and in the trench electrically isolated from the drift layer by a gate insulating layer.

Description

Silicon carbide semiconductor element

Technical Field

The present invention relates to a semiconductor device, and more particularly, to a silicon carbide semiconductor device having a composite gate structure.

Background

Silicon carbide (SiC) power devices have become a promising material for power transistors in power conversion applications, including Metal Oxide Semiconductor Field Effect Transistors (MOSFETs), insulated Gate Bipolar Transistors (IGBTs), heterostructure Field Effect Transistors (HFETs), junction Field Effect Transistors (JFETs), and High Electron Mobility Transistors (HEMTs). Compared with similar silicon products, the silicon carbide power transistor such as silicon carbide MOSFET has the advantages of high input impedance, low driving loss, low on-resistance, high blocking voltage, low switching loss, high switching speed, large safe working area and the like.

One of the key considerations of SiC MOSFETs is to reduce the on-resistance of a particular region. The total on-resistance of the SiC MOSFET includes channel resistance, JFET resistance, contact resistance, drift resistance, and substrate resistance. The active region of a SiC MOSFET is composed of an array of unit cells (array of unit cells), one strategy to reduce the total on-resistance is to increase the channel width density, reducing the channel resistance by reducing the cell pitch. However, as the cell pitch decreases, the JFET region becomes narrower, which increases the JFET resistance, and in order to avoid increasing the JFET resistance beyond the reduced channel resistance, a current spreading layer (current SPREADING LAYER, CSL) is typically introduced, which has a higher doping concentration than the drift layer to mitigate the JFET effect, and the JFET resistance decreases with increasing doping concentration of the CSL, but if the doping concentration of the CSL is too high, the blocking voltage decreases, and decreasing the on-resistance by decreasing the cell pitch requires an optimization process at the trade-off condition between CSL doping and blocking voltage, and requires better process control, which is a great challenge to improve the yield of the SiC MOSFET.

Disclosure of Invention

According to some embodiments described herein, a silicon carbide semiconductor device includes a silicon carbide substrate, a drift layer, a plurality of first doped regions, a plurality of second doped regions, a plurality of third doped regions, a plurality of trenches, and a gate electrode. The drift layer has a first conductivity type and is disposed on the silicon carbide substrate. The first doped regions have a second conductivity type opposite to the first conductivity type and are arranged in the drift layer, the first doped regions comprise a plurality of first sub-portions and a plurality of first extension portions horizontally extending from the first sub-portions along a first horizontal direction, and the first doped regions and the drift layer form a plurality of first p-n junctions and a plurality of JFET regions. The second doped regions have the first conductivity type and are arranged in the first doped region, the second doped regions comprise a plurality of second sub-portions and a plurality of second extension portions horizontally extending from the second sub-portions along the first horizontal direction, the second doped regions and the first doped regions form a plurality of second p-n junctions, and a plurality of channel regions are arranged between the first p-n junctions and the second p-n junctions along a main surface of the drift layer. The plurality of third doped regions have the second conductivity type, and the third doped regions are disposed in the first sub-portion of the first doped region and adjacent to the second sub-portion of the second doped region. The plurality of trenches penetrate from the main surface into the drift layer, the plurality of trenches extending horizontally through at least a portion of the JFET region. The gate electrode is disposed over the main surface and within the trench, the gate electrode being electrically isolated from the drift layer by a gate insulating layer.

In an embodiment, each of the first sub-portions and each of the second sub-portions are connected by one or more first extension portions and one or more second extension portions, respectively.

In an embodiment, each of the first sub-portions and each of the second sub-portions are connected by at least four first extension portions and at least four second extension portions, respectively.

In an embodiment, the first extension portion of the first doped region and the second extension portion of the second doped region extend along the first horizontal direction, and the trench extends substantially parallel to the first extension portion and the second extension portion.

In one embodiment, the trench extends along a second horizontal direction orthogonal to the first horizontal direction.

In one embodiment, the grooves include a first set and a second set that extend substantially along the first horizontal direction and a second horizontal direction that is orthogonal to the first horizontal direction.

In an embodiment, the first doped region and the second doped region further include a plurality of first connection portions and a plurality of second connection portions, respectively, the first connection portions and the second connection portions horizontally extend from the first sub-portion and the second sub-portion along a second horizontal direction.

In one embodiment, a bottom of the trench is deeper than a bottom of the first doped region.

In one embodiment, a plurality of shielding regions of the second conductivity type disposed at a bottom of the trench are further included, the shielding regions being electrically coupled (ELECTRICALLY COUPLED) to the first doped region.

In one embodiment, a distance between a sidewall of the trench and the first extension is equal to or greater than 1nm.

In one embodiment, the drift layer further comprises a current spreading layer of the first conductivity type adjacent to the main surface and having a higher doping concentration than a remaining portion of the drift layer.

In one embodiment, a bottom of the current spreading layer is deeper than a bottom of the first doped region and shallower than a bottom of a shielding region.

Accordingly, the described embodiments are configured to improve the performance of silicon carbide semiconductor elements. Furthermore, trench structures according to embodiments described herein may increase the overall channel width density.

Drawings

Fig. 1 is a perspective view of a silicon carbide semiconductor device according to a first embodiment of the present invention prior to forming a gate structure.

Fig. 2 is a perspective view of a silicon carbide semiconductor device after forming a gate structure in accordance with a first embodiment of the present invention.

Fig. 3 is a top view of the silicon carbide semiconductor device shown in fig. 2.

Fig. 4 is a perspective view of a silicon carbide semiconductor device according to a second embodiment of the present invention prior to forming a gate structure.

Fig. 5 is a perspective view of a silicon carbide semiconductor device after forming a gate structure in accordance with a second embodiment of the present invention.

Fig. 6 is a top view of the silicon carbide semiconductor device shown in fig. 5.

Fig. 7 is a top view of a silicon carbide semiconductor device according to a third embodiment of the present invention.

Fig. 8 is a top view of a silicon carbide semiconductor device according to a fourth embodiment of the present invention.

Fig. 9 is a top view of a silicon carbide semiconductor device according to a fifth embodiment of the present invention.

Fig. 10 is a schematic view showing a vertical section along line A-A of fig. 9.

Fig. 11 is a top view of a silicon carbide semiconductor device according to a sixth embodiment of the present invention.

Fig. 12 is a schematic vertical sectional view along line B-B of fig. 11.

Fig. 13 is a schematic vertical sectional view along line C-C of fig. 11.

Fig. 14 is a perspective view of a silicon carbide semiconductor device according to a seventh embodiment of the present invention.

Detailed Description

It will be understood that, although the terms first, second, etc. may be used herein to describe various elements, these terms are not intended to limit the elements. These terms are only used to distinguish one element from another element. For example, a first element could be termed a second element, and, similarly, a second element could be termed a first element, without departing from the scope of the present invention.

The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items.

In the drawings, the thickness of layers and regions are exaggerated for clarity. It will also be understood that when an element such as a layer, portion, region or substrate is referred to as being "on," "covering" or "over …" another element, it can be directly on, directly on or over the element; or other elements may be present in between. In contrast, when an element is referred to as being "directly on," "directly overlying" or "directly over" another element, there are no intervening elements present.

Terms such as "above," "below," "horizontal," "transverse," or "vertical" may be used herein to describe one element, layer, section or region's relationship to another element, layer, section or region in the figures. It will be understood that terms other than those described above are intended to encompass different orientations of the element in addition to the orientation depicted in the figures. The various embodiments will now be described wherein like structural features are identified by like or similar reference numerals. As used herein, "lateral" or "lateral direction" is understood to mean a direction or extent that extends substantially parallel to the lateral extent of the semiconductor element, and thus extends substantially parallel to a surface or side thereof. In contrast, the term "thickness direction" is understood to mean a direction extending substantially perpendicular to its surface or side and thus perpendicular to the transverse direction.

The terminology used in the description of the various embodiments herein is for the purpose of describing particular examples only and is not intended to be limiting. As used herein, the singular forms "a", "an", and "the" include plural referents unless the context clearly dictates otherwise or deliberately limit the number of elements. It will be further understood that the terms "comprises" and/or "comprising," when used herein, specify the presence of stated features, elements, and/or components, but do not preclude the addition or presence of one or more other features, elements, components, and/or groups thereof. The indefinite and definite articles are intended to encompass both the plural and singular unless the context clearly dictates otherwise.

The terms "first conductivity type" and "second conductivity type" refer to opposite conductivity types, such as N-type or P-type, however, the description and illustrations of each embodiment herein also include their complementary embodiments, like numbers referring to like elements throughout.

The described embodiments are configured to improve the performance of silicon carbide semiconductor elements. In particular, embodiments described herein may reduce the JFET resistance of SiC MOSFETs and also reduce parasitic gate-to-drain capacitance (Cgd) to enhance switching performance. Furthermore, the trench structure according to embodiments described herein may increase the overall channel width density (CHANNEL WIDTH DENSITY).

Fig. 1 is a perspective schematic view of a silicon carbide semiconductor element of a first embodiment of the present invention, only partially showing the structure of a silicon carbide semiconductor element 1. The silicon carbide semiconductor device 1 includes a silicon carbide substrate 10, a drift layer 20, one or more first doped regions 30, one or more second doped regions 40, one or more third doped regions 50, and one or more trenches 60.

The silicon carbide substrate 10 has a first conductivity type (e.g., N-type) and may be, for example, a nitrogen doped 4H-SiC substrate. The drift layer 20 is disposed on the silicon carbide substrate 10 and has the first conductivity type. The first doped region 30 may be disposed on the drift layer 20 and adjacent to a major surface 21 of the drift layer 20. The first doped region 30 has a second conductivity type (e.g., P-type) opposite the first conductivity type. The first doped region 30 may be formed by implanting aluminum ions as dopants into the N-type drift layer to form a counter-doped P-type region adjacent to the major surface 21 of the drift layer 20. The second doped region 40 is formed by implanting nitrogen ions or phosphorus ions as dopants into the P-type first doped region 30, forming a heavily doped N-type region (heavily doped N-type regions).

The third doped region 50 has the first conductivity type and is disposed within the first doped region 30 and adjacent to the second doped region 40. In one example, the drift layer 20 is N-type, has a thickness of about 10 μm, and has a doping concentration of about 8E15 cm ^-3; the first doped region 30 is P-type, has a depth of about 0.5 μm, and has a doping concentration of about 1e17 cm ^-3; the second doped region 40 is N-type, has a depth of about 0.2 μm, and has a doping concentration of about 1E20 cm ^-3.

The trench 60 penetrates the main surface 21 of the drift layer 20 and extends directly to the drift layer 20 along a thickness direction. Each of the grooves 60 has a bottom wall 61 and a side wall 62 connected to the bottom wall 61. The bottom wall 61 of the trench 60 may be deeper than a bottom 30a of the first doped region 30.

Referring to fig. 2, the first doped region 30 and the drift layer 20 form a plurality of first p-n junctions PN1 and a plurality of JFET regions, the second doped region 40 and the first doped region 30 form a plurality of second p-n junctions PN2, and a plurality of channel regions CH are disposed between the first p-n junctions PN1 and the second p-n junctions PN2 along the main surface 21.

The silicon carbide semiconductor element 1 further comprises one or more gate structures 70 and one or more shielding regions 80. The gate structure 70 is disposed on the main surface 21 and in the trench 60, the gate structure 70 includes a gate insulating layer 71 and a gate electrode 72, the gate insulating layer 71 is formed and extends on the main surface 21, the bottom wall 61 and the sidewall 62 of the trench 60, and the gate electrode 72 is formed on the gate insulating layer 71, the gate insulating layer 71 may fully insulate the gate electrode 72 from the drift layer 20, the gate insulating layer 71 may be implemented by SiO ₂ or SiO _xN_y, and the gate electrode 72 may be implemented by polysilicon (poly-Si). The shielding region 80 has the second conductivity type and is disposed at a bottom of the trench 60, the shielding region 80 is electrically coupled (ELECTRICALLY COUPLED) to the first doped region 30, and an electrical connection between the shielding region 80 and the first doped region 30 is described in other embodiments below.

Fig. 3 is a top view of the silicon carbide semiconductor device shown in fig. 2. The silicon carbide semiconductor device 1 may further include one or more source contacts 90 disposed on the third doped region 50 and a region of the second doped region 40 surrounding the third doped region 50. The first doped region 30 includes a plurality of first sub-portions 31 and a plurality of first extension portions 32. In the present embodiment, the first extension portion 32 extends horizontally along a first horizontal direction (e.g. Y direction in fig. 1) from the corner of the first sub-portion 31. The second doped region 40 includes a plurality of second sub-portions 41 and a plurality of second extension portions 42, and the second extension portions 42 also extend horizontally along the first horizontal direction from corners of the second sub-portions 41. Referring to fig. 2, each of the first doped region 30 and the second doped region 40 exhibits a ladder-like configuration (ladder-like configuration) when viewed along a normal line of the main surface 21 of the drift layer 20, each of the ladder-like configurations extending along the first horizontal direction. The trench 60 also extends along the first horizontal direction and is parallel to the stepped configuration of the first doped region 30 and the second doped region 40. The stepped configuration of the first doped region 30 and the second doped region 40 sequentially alternates with the trench 60. In addition, the first doped region 30 is spaced apart from the trench 60 by a distance equal to or greater than 1nm in the lateral spacing.

From the layout of the first doped region 30, the second doped region 40 and the third doped region 50, the silicon carbide semiconductor device 1 includes a plurality of unit cells UC, which are the smallest repeating unit structures of the silicon carbide semiconductor device 1 (e.g., MOSFET) and are arranged in an active region. In one embodiment, the first doped region 30 may have a width W1 ranging between 0.5 μm and 10 μm, the unit cell UC may have a cell spacing W2 ranging between 1 μm and 20 μm, and the trench 60 may have a trench width W3 ranging between 0.2 μm and 10 μm.

The embodiments of fig. 1-3 illustrate non-limiting examples of composite gate semiconductor devices according to the present disclosure. The composite gate includes a planar gate structure formed along the XY plane around the source contact 90 and a trench gate structure formed along the XZ and/or YZ planes around the trench 60. The planar gate structure facilitates forming lateral channels and the trench gate structure reduces JFET resistance because a cumulative layer (accumulation layer) along the sidewalls 62 of the trench 60 will be formed when a positive gate bias (positive gate bias voltage) is applied. The accumulation layer has a higher carrier density (CARRIER DENSITY) than the doping of the drift layer 20 and provides a low resistance current path from a drain electrode to a source electrode of the SiC MOSFET. In addition, the shielding region 80 of the embodiment of fig. 2 reduces the gate-to-drain capacitance Cgd, thereby reducing the switching time and switching loss of on and off. Therefore, the channel density of the composite gate semiconductor device is the same as that of the conventional structure having the same cell pitch, but the JFET resistance and parasitic gate-to-drain capacitance Cgd are reduced due to the configuration of the composite gate, thereby improving the overall on-resistance and switching performance. The lower JFET resistance and parasitic capacitance of the silicon carbide elements of the embodiments herein compared to conventional silicon carbide elements makes them ideal in high power applications.

Fig. 4-6 illustrate a second embodiment of the present disclosure, contrary to the first embodiment, the trench 60 extends along the second horizontal direction (e.g., X-direction in fig. 4) when viewed along a normal to the main surface 21 of the drift layer 20, the trench 60 being perpendicular to the stepped configuration of the first doped region 30 and the second doped region 40. The trench 60 in this embodiment spans the first extension 32 of the first doped region 30 and the second extension 42 of the second doped region 40 and is disposed between the first subsection 31 of the first doped region 30 and the second subsection 41 of the second doped region 40.

In one embodiment, the first doped region 30 may have a width W1 ranging between 0.5 μm and 10 μm, the unit cell UC may have a cell spacing W2 ranging between 1 μm and 20 μm, and the trench 60 may have a trench width W3 ranging between 0.2 μm and 10 μm. Embodiments disclosed herein provide a silicon carbide semiconductor element 1 (e.g., a MOSFET) having an increased overall channel width density. In one example, the first extension 32 of the first doped region 30 has a width of 2 μm, the first doped region 30 has a depth of 0.7 μm, and the trench has a width of 1 μm. Referring to fig. 4, by providing the trench 60, a portion of the lateral channel width is sacrificed due to the trench structure. Assuming that the trench width W3 is 1 μm, the variation in the lateral channel width can be expressed as:

-4×1μm＝-4μm

but the trench structure also creates vertical channels on both sides of the sidewalls 62 of the trench 60. Assuming that a depth of the first doped region 30 is 0.7 μm and a width of the first extension 32 is 2 μm, the width variation of the vertical channel can be expressed as:

+2×(4×0.7μm+2×2μm)＝+13.6μm

thus, by providing one trench for each stepped configuration of the first doped region 30, the channel width will increase by 9.6 μm. The overall channel width may be further increased by providing more trenches.

The embodiments of fig. 4-6 illustrate non-limiting examples of composite gate semiconductor devices according to the present disclosure. The composite gate includes a planar gate structure formed along the XY plane around the source contact 90 and a trench gate structure formed along the XZ and/or YZ planes around the trench 60. The planar gate structure facilitates the formation of lateral channels, while the trench gate structure facilitates the formation of vertical channels. In addition, the shielding region 80 of the embodiment of fig. 5 reduces the gate-to-drain capacitance Cgd, thereby reducing the switching time and switching loss of on and off. Therefore, the channel density of the composite gate semiconductor device is higher than that of the conventional structure of the same cell pitch, and the JFET resistance and parasitic gate-to-drain capacitance Cgd are also reduced due to the configuration of the composite gate, so that the overall on-resistance and switching performance are enhanced. The lower channel resistance and parasitic capacitance of the silicon carbide elements of the embodiments herein compared to conventional silicon carbide elements make them ideal in high power applications.

Fig. 7 shows a third embodiment of the present disclosure. The present embodiment can be regarded as a combination of the first embodiment and the second embodiment. The trench 60 includes a first group 60a and a second group 60b. The first group 60a of the grooves 60 extends substantially in the first horizontal direction, and the second group 60b of the grooves 60 extends substantially in the second horizontal direction. The first group 60a of the trenches 60 is disposed between the stepped configurations of the first doped region 30 and the second doped region 40, and the second group 60b of the trenches 60 is disposed across the stepped configurations of the first doped region 30 and the second doped region 40, thereby forming a mesh structure of the trenches 60, the first group 60a and the second group 60b of the trenches 60 are connected to each other, and the trench widths and depths of the first group 60a and the second group 60b may be the same or different to optimize the performance of the silicon carbide semiconductor device 1.

In one embodiment, the first doped region 30 may have a width W1 ranging between 0.5 μm and 10 μm, the unit cell UC may have a cell spacing W2 ranging between 1 μm and 20 μm, and the trench 60 may have a trench width W3 ranging between 0.2 μm and 10 μm. Embodiments disclosed herein provide a silicon carbide semiconductor element 1 (e.g., a MOSFET) with reduced channel resistance, JFET resistance, and Cgd.

The configuration of the first doped region 30 and the second doped region 40 need not be stepped, but may be other geometries.

Fig. 8 shows a fourth embodiment of the present disclosure. In the present embodiment, the first extension portion 32 extends horizontally in the first horizontal direction from the front and rear of the first sub-portion 31, and the second extension portion 42 also extends horizontally in the first horizontal direction from the front and rear of the second sub-portion 41. When viewed along the normal line of the main surface 21 of the drift layer 20, the first doped region 30 and the second doped region 40 each have a stripe configuration (stripe configuration) as shown in fig. 8, each of the stripe configurations extends along the first horizontal direction, the trench 60 also extends along the first horizontal direction and is parallel to the stripe configurations of the first doped region 30 and the second doped region 40, and the stripe configurations of the first doped region 30 and the second doped region 40 sequentially alternate with the trench 60.

The fourth embodiment may have various possible alternatives, for example, the trench 60 may be arranged and extended along the second horizontal direction, and the trench 60 is perpendicular to the stripe-like configuration of the first doped region 30 and the second doped region 40 when viewed along the normal of the main surface 21 of the drift layer 20. In addition, the trench 60 may include a first group 60a and a second group 60b to form a net-like structure (net-like structure), as shown in fig. 7.

Fig. 9 shows a fifth embodiment of the present disclosure. In contrast to the first embodiment, the trench 60 includes a first group 60a and a third group 60c. The first group 60a of the grooves 60 extends substantially continuously along the first horizontal direction as shown in the first embodiment, and the third group 60c of the grooves 60 extends substantially intermittently along the first horizontal direction.

The first doped region 30 and the second doped region 40 both exhibit a ladder-like configuration as shown in fig. 9 when viewed along the normal of the main surface 21 of the drift layer 20. The corresponding ladder arrangements are configured to extend in the first horizontal direction, the first group 60a of the grooves 60 being disposed between the ladder arrangements. When viewed along the second horizontal direction, it can be seen that the first group 60a of the trenches 60 sequentially alternates with the ladder-like configuration of the first doped region 30 and the second doped region 40. Each of the third groups 60c of the trenches 60 may include one or more trench segments along the first horizontal direction, the trench segments being disposed in the drift layer 20 surrounded by the first sub-portion 31 and the first extension portion 32.

In the present embodiment, the third doped region 50 extends along the first horizontal direction to the end of the third group 60c of the trench 60. In fig. 9, only a single third doped region 50 is present under the source contact 90, but the third doped region 50 may be divided into two parts to increase the contact area between the second doped region 40 and the source contact 90.

In one embodiment, the first doped region 30 may have a width W1 ranging between 0.5 μm and 10 μm, the unit cell UC may have a cell pitch W2 ranging between 1 μm and 20 μm, the first group 60a of trenches 60 may have a trench width W3 ranging between 0.2 μm and 10 μm, and the third group 60c of trenches 60 may have a trench width W4 ranging between 0.2 μm and 10 μm.

Fig. 10 is a schematic vertical cross-section along line A-A of fig. 9, further illustrating the gate structure 70 formed in the trench 60c and the shielding region 80 located below the trench 60c and the gate structure 70. The shielding region 80 extends along a bottom of the trench 60c and is electrically connected to the third doped region 50 extending to an end of the trench 60.

Fig. 10 shows that a portion 50a of the third doped region 50 under the trench 60c overlaps the shielding region 80. In an exemplary process sequence, the first doped region 30, the second doped region 40 and the third doped region 50 are sequentially formed, then the trench 60c is etched in the third doped region 50, and the shielding region 80 is formed under the trench 60 c. Since a bottom 50b of the third doped region 50 is deeper than a bottom 601c of the trench 60c, a sacrificial portion of the third doped region 50 is removed during etching of the trench 60c after forming the trench 60c, and the portion 50a remains under the trench 60c, so that after forming the shielding region 80, the portion 50a of the third doped region 50 naturally makes electrical contact with the shielding region 80 because both the third doped region 50 and the shielding region 80 are P-type doped regions.

Fig. 11 shows a sixth embodiment of the present disclosure. The first doped region 30 includes a plurality of first sub-portions 31, a plurality of first extension portions 32, and a plurality of first connection portions 33. The second doped region 40 includes a plurality of second sub-portions 41, a plurality of second extension portions 42, and a plurality of second connection portions 43. The first extension portion 32 and the second extension portion 42 extend horizontally along the first horizontal direction from the corners of the first sub-portion 31 and the second sub-portion 41, respectively, and the first connection portion 33 and the second connection portion 43 extend horizontally along the second horizontal direction from both sides of the first sub-portion 31 and the second sub-portion 41, respectively.

The unit cells of the first doped region 30 and the second doped region 40 include a first unit cell UC1 and a second unit cell UC2, and the first unit cell UC1 and the second unit cell UC2 are alternately arranged at a certain interval. The source contact 90 is disposed on the third doped region 50 in the first unit cell UC 1. The trench 60 extends along the second horizontal direction and passes through the third doped region 50 in the second unit cell UC 2. In other words, the trench 60 is disposed between and parallel to the alignment direction of the third doped region 50 in the first unit cell UC 1.

Fig. 12 and 13 are schematic vertical cross-sectional views of portions along line B-B and line C-C of fig. 11. In the present embodiment, the third doped region 50 in the second unit cell UC2 is disposed deep enough to connect the shielding region 80 under the trench 60, thereby achieving the electrical connection between the first doped region 30 and the shielding region 80.

Fig. 14 shows a further embodiment, the drift layer 20 further comprising a current spreading layer 22. The current spreading layer 22 has a higher doping concentration than the rest of the drift layer 20. In one example, the first doped region 30 has a depth of 0.6 μm, the trench 60 has a depth of 1 μm, and the shielding region 80 has a depth of 0.2 μm, i.e., a bottom 80a of the shielding region 80 is located below a bottom 601 of the trench 60. The drift layer 20 has a doping concentration of 8E15cm ^-3, the current spreading layer 22 has a doping concentration of 1E17cm ^-3, and a depth of the current spreading layer 22 is set to 1 μm, i.e. a bottom 22a of the current spreading layer 22 is lower than a bottom 30a of the first doped region 30 and higher than the bottom 80a of the shielding region 80.

Although specific embodiments and examples have been illustrated and described herein, it will be appreciated by those of ordinary skill in the art that a variety of alternate and/or equivalent implementations may be substituted for the specific embodiments and examples without departing from the scope of the present application. It is intended that the application encompass any adaptations or variations of the specific embodiments and examples discussed herein. Accordingly, the scope of the application is limited only by the claims and the equivalents thereof.

[ Symbolic description ]

1: Silicon carbide semiconductor element

10: Silicon carbide substrate

20: Drift layer

21: Major surface

22: Current spreading layer

22A: bottom part

30: First doped region

31: First subsection

32: A first extension part

33: First connecting portion

40: Second doped region

41: A second sub-part

42: A second extension part

43: Second connecting portion

50: Third doped region

50A: part of the

50B: bottom part

60: Groove(s)

60A: a first group of

60B: second group of

60C: third group (groove)

601: Bottom part

601C: bottom part

61: Bottom wall

62: Side wall

70: Gate structure

71: Gate insulating layer

72: Gate electrode

80: Shielded region

80A: bottom part

90: Source contact

PN1: first p-n junction

PN2: second p-n junction

CH: channel region

UC: unit cell

UC1: first unit cell

UC2: second unit cell

W1: width of (L)

W2: cell spacing

W3: trench width

W4: trench width.

Claims (12)

1. A silicon carbide semiconductor element, comprising:

A silicon carbide substrate;

A drift layer of a first conductivity type disposed on the silicon carbide substrate and having a major surface;

A plurality of first doped regions of a second conductivity type opposite to the first conductivity type and disposed in the drift layer, the first doped regions including a plurality of first sub-portions and a plurality of first extension portions extending horizontally from the first sub-portions along a first horizontal direction, the first doped regions forming a plurality of first p-n junctions and a plurality of JFET regions with the drift layer;

A plurality of second doped regions of the first conductivity type disposed within the first doped region, the second doped regions including a plurality of second sub-portions and a plurality of second extension portions extending horizontally from the second sub-portions along the first horizontal direction, the second doped regions forming a plurality of second p-n junctions with the first doped region, a plurality of channel regions disposed between the first p-n junctions and the second p-n junctions along the main surface;

A plurality of third doped regions of the second conductivity type disposed in the first sub-portion of the first doped region and adjacent to the second sub-portion of the second doped region;

A plurality of trenches penetrating into the drift layer from the main surface, the plurality of trenches extending horizontally through at least a portion of the JFET region; and

And a gate electrode disposed on the main surface and in the trench, the gate electrode being electrically isolated from the drift layer by a gate insulating layer.

2. The silicon carbide semiconductor device of claim 1, wherein each of the first sub-portions and each of the second sub-portions are connected by one or more first extension portions and one or more second extension portions, respectively.

3. The silicon carbide semiconductor device of claim 1, wherein each of the first sub-portions and each of the second sub-portions are connected by at least four first extensions and at least four second extensions, respectively.

4. The silicon carbide semiconductor device of claim 1, wherein the first extension of the first doped region and the second extension of the second doped region extend along the first horizontal direction, and the trench extends parallel to the first extension and the second extension.

5. The silicon carbide semiconductor device of claim 1, wherein the trench extends along a second horizontal direction orthogonal to the first horizontal direction.

6. The silicon carbide semiconductor device of claim 1, wherein the trenches comprise a first set and a second set, the first set and the second set extending along the first horizontal direction and a second horizontal direction orthogonal to the first horizontal direction.

7. The silicon carbide semiconductor device of claim 1, wherein the first doped region and the second doped region further comprise a plurality of first connecting portions and a plurality of second connecting portions, respectively, the first connecting portions and the second connecting portions extending horizontally from the first sub-portion and the second sub-portion along a second horizontal direction.

8. The silicon carbide semiconductor device of claim 1, wherein a bottom of the trench is deeper than a bottom of the first doped region.

9. The silicon carbide semiconductor device of claim 1, further comprising a plurality of shielding regions of the second conductivity type disposed at a bottom of the trench, the shielding regions electrically coupled to the first doped region.

10. The silicon carbide semiconductor device of claim 4, wherein a distance between a sidewall of the trench and the first extension is equal to or greater than 1 nanometer.

11. The silicon carbide semiconductor device of claim 1, wherein the drift layer further comprises a current spreading layer of the first conductivity type adjacent to the major surface and having a higher doping concentration than a remaining portion of the drift layer.

12. The silicon carbide semiconductor device of claim 11, wherein a bottom of the current spreading layer is deeper than a bottom of the first doped region and shallower than a bottom of a shielding region.