CN118299368A - 2.5D packaging test integrated circuit, test method and packaging method - Google Patents
2.5D packaging test integrated circuit, test method and packaging method Download PDFInfo
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Abstract
The invention provides a 2.5D packaging test integrated circuit, a testing method and a packaging method. By utilizing the technical scheme provided by the invention, whether the key signal points on the middle layer and the chip have a connecting effect or not can be effectively detected, the subsequent packaging can be directly carried out after the detection is finished and the judgment is qualified, the original functions and circuit structures of all signal pins after the chip packaging are not influenced, the detection efficiency and accuracy are ensured, and the yield and the efficiency of the final packaging can be improved.
Description
Technical Field
The invention relates to the technical field of semiconductor packaging and testing, in particular to a 2.5D packaging test integrated circuit, a testing method and a packaging method.
Background
Semiconductor chip packaging is the final stage of the semiconductor device manufacturing process. At this critical point, the semiconductor blocks are covered with a protective layer that protects the Integrated Circuits (ICs) from potential external hazards and time erosion. Such packages essentially act as protective enclosures, shielding the IC blocks and facilitating electrical connections responsible for transmitting signals to the electronic device circuit board. Advanced packaging has emerged in a variety of sophisticated technologies, each with unique advantages that can meet the increasing demands of modern technology. 2.5D packaging involves stacking two or more chips side by side and connecting them through an interposer. This approach improves performance and power efficiency by facilitating faster data transfer between chips. The interposer is a bridge for electrically connecting the chip and the substrate, and connects the chip on the upper surface and the substrate on the lower surface through the through silicon via in the center. Because the interposer is used for circuit switching, the arrangement quantity of the through silicon vias is more, and the conduction yield of the through silicon vias directly influences the yield of the packaged integrated circuit, the conduction of the through silicon vias of the interposer needs to be tested in the packaging process, and defective interposers are removed and repaired in time, so that the defect of low yield of finished products caused by the defects of the interposers in finished products is avoided.
By searching, technical literature on relevant package testing is disclosed in the prior art. For example, the invention patent publication with publication number "CN104299959a" entitled "test structure for flip chip, and method of manufacturing flip chip". A flip chip test structure, a flip chip and a method of manufacturing a flip chip are disclosed. The flip chip comprises a wafer and a packaging substrate in a test structure of the flip chip, and the test structure comprises: one or more via link structures disposed within the die; the plurality of electric connection units are arranged on the functional surface of the wafer and connected with the through hole chain structure, and the plurality of electric connection units are connected in series through the through hole chain structure; and the two test leads are fixed on the packaging substrate and are respectively connected with the electric connection units at the head and tail positions in a one-to-one correspondence manner. The technical scheme disclosed in the prior art aims at testing the packaging effect and whether the packaged wafer is warped or leaked, and does not provide a corresponding technical scheme for the conduction yield of the interposer.
For example, the invention patent publication with publication number "CN105051878a" entitled "package integrity monitor with sacrificial bumps". Disclosed is an apparatus having a package integrity monitoring function, comprising: a package having a die connected to an interposer via a plurality of bumps, wherein at least a portion of the bumps contain dummy bumps; a package integrity monitor having a transmitter for transmitting test signals and a receiver for receiving the test signals; and a first scan chain containing a plurality of alternating interconnects connecting a portion of the dummy bumps in series within the die and within the interposer, wherein the first scan chain has a first end coupled to the transmitter of the package integrity monitor and a second end coupled to the receiver of the package integrity monitor. This prior art is similar to the prior art described above and is directed to monitoring die-to-interposer connectivity during operation of an IC package.
For example, japanese patent publication No. "JP2006165325A" entitled "wiring structure of board mounted IC package and method of inspecting electric connection defect". A new wiring structure and inspection method are proposed for solving the problems associated with inspection of the electrical connection quality of an IC package in which an IC package (BGA package) having a semiconductor element mounted on an intermediate layer is electrically connected to a substrate through a conductive element. A wiring structure of a substrate on which an IC package is mounted, wherein a plurality of solder rings are provided on an interposer and connected by wires through the wiring, a BGA package is mounted on the substrate, and conductive members of the wires constitute a series of series circuit test loops. The prior art has the same technical problems as the prior art.
Although the conductivity of the packaging system can be tested in the prior art, the interposer cannot be tested separately, and how the tested interposer and other devices can be packaged after the test is passed is not considered. Therefore, it may be of great significance to propose a 2.5D packaged test integrated circuit, a test method and a packaging method that can be tested for an interposer and that will not affect the subsequent packaging process after testing.
Disclosure of Invention
In order to overcome the shortcomings of the prior art, the invention provides a 2.5D packaging interposer, the upper and lower surfaces of which can be etched, and the interposer further comprises a via hole for electrically connecting signal points on the upper and lower surfaces, the interposer is divided into a signal region to be tested and a test region, wherein the signal region to be tested is provided with signal points A n and signal points A n are respectively mapped to signal mapping points B n connected to the test region through the surface etching circuit of the interposer, Signal point a n is mapped by the via of the interposer to probe point C n on the lower surface of the interposer, where n is a natural number greater than 1; The probe point C n is used for etching a circuit through the lower surface of the interposer and mapping to a probe mapping point D n on the upper surface of the interposer through a via hole, a test chip is connected to the upper surface of the test area, the lower surface of the test chip is provided with a conductive part which is coupled and connected with the via hole of the interposer, and the conductive part is connected with the upper surface of the test chip through a through silicon via hole; The conductive portion is coupled to signal mapping point B n or probe mapping point D n, which, when signal mapping point B n is shorted or probe mapping point D n and signal mapping point B n+1 are shorted on the upper surface of the test chip, A test loop may be formed between probe point C n, signal point a n, signal map point B n.
Further, the signal points a n are each mapped to the signal mapping point B n connected to the test area by the interposer upper surface etching circuit.
Further, the upper surface of the test chip is provided with a conductive layer, and the signal mapping point B n or the probe mapping point D n is short-circuited after being mapped to the conductive layer by the conductive part.
Further, the signal points a n are respectively mapped to the signal mapping points B n connected to the test area through the etching circuit on the upper surface of the interposer, and the signal mapping points B n are all shorted to the conductive layer on the upper surface of the test chip.
Or the signal point a 1 and the signal point a 2 are respectively mapped to a signal mapping point B 1 and a signal mapping point B 2 which are connected to the test area through an etching circuit on the upper surface of the interposer, the conductive layers are divided into n-th conductive layers which are not conductive to each other, wherein the signal mapping point B 1 and the signal mapping point B 2 are short-circuited through the first conductive layer, and the probe mapping point D n is connected to the signal mapping point B n+1 through an etching circuit on the lower surface of the interposer and through a via hole, a through silicon via hole and the n-th conductive layer.
The 2.5D packaging test method is also provided, the test integrated circuit is adopted, the two probe points C n are divided into one group, electric signals are respectively input into the test signal loop through the probe points C n by using the probes, when the test signal loop in each group of probe tests is in a normal path, the connection between the probe points C n and the signal point A n is indicated to be normal, and otherwise, the test is judged to be abnormally ended.
The 2.5D packaging test method is also provided, the test integrated circuit is adopted, an electric signal is input into the test signal loop through the probe point C 1 and the probe point C n by using the probe, when the test signal loop is in a normal path in the probe test, the connection between the probe point C n and the signal point A n is indicated to be normal, otherwise, the test signal loop is judged to be bad; if the test result is poor in return, the probe point C 1 is used as an anode, and the probe points C 2 to C n are used as cathodes in sequence for fault detection so as to determine whether an open circuit exists between the probe point C n and the signal point A n.
The 2.5D packaging method is also provided, and after the test result returns to normal, a formal chip is connected to the signal area to be tested by adopting the packaging test method; plastic packaging and protecting the formal chip and the test chip; flip-chip connecting the interposer to the substrate; the test chip is lapped or diced until the conductive layer is completely removed such that an open circuit is formed between signal points a n.
Compared with the prior art, the technical scheme of the application has the following beneficial effects: by utilizing the technical scheme provided by the application, whether the key signal points on the middle layer and the chip have a connecting effect or not can be effectively detected, the subsequent packaging can be directly carried out after the detection is finished and the judgment is qualified, the original functions and circuit structures of all signal pins after the chip packaging are not influenced, the detection efficiency and accuracy are ensured, and the yield and the efficiency of the final packaging can be improved.
Drawings
Fig. 1: a schematic plan view after encapsulation;
fig. 2: schematic plan view of interposer;
fig. 3: the fourth embodiment of the invention provides an integrated test circuit schematic diagram;
Fig. 4: the fifth embodiment of the invention provides an integrated test circuit schematic diagram;
Fig. 5: the integrated test circuit schematic diagram provided by the sixth embodiment of the invention;
Fig. 6: the fifth embodiment of the invention provides an integrated test circuit equivalent circuit diagram;
Fig. 7: the integrated test circuit equivalent circuit diagram provided by the embodiment six of the invention;
Fig. 8: the invention relates to a test chip mounting schematic diagram in a packaging method;
Fig. 9: the invention relates to a formal chip mounting schematic diagram in a packaging method;
fig. 10: the invention relates to a plastic package intermediate layer schematic diagram in a packaging method;
Fig. 11: the invention relates to a substrate and interposer connection schematic diagram in a packaging method;
Fig. 12: the invention relates to a method for removing an interposer conductive layer in a packaging method.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Embodiment one, as shown in fig. 1 and 2.
The present embodiment aims to provide an interposer 1 that can be used for package testing. The upper and lower surface etchable circuits further comprise via holes 13 for electrically connecting the signal points on the upper and lower surfaces, the interposer 1 is divided into a signal area 11 to be tested and a test area 12, wherein the signal area 11 to be tested is provided with signal points A n, signal points A n are respectively mapped to signal mapping points B n connected to the test area 12 through the surface etching circuit of the interposer 1, signal points A n are mapped to probe points C n on the lower surface of the interposer 1 by the via holes of the interposer 1, and a test loop can be formed among the probe points C n, the signal points A n and the signal mapping points B n after the signal mapping points B n are shorted, wherein n is a natural number greater than 1.
In the present embodiment, the via hole 13 is a through silicon via for electrically connecting the chip on the upper surface of the interposer 1 to the substrate 6 on the lower surface. The yield of the electrical conduction through the vias 13 will determine whether the packaged product is acceptable. the upper surface signal points a n of the interposer 1 cannot be directly tested by the probes due to the small pitch, while the pitch of the probe points C n fanned out to the back surface of the interposer 1 by the vias 13 is significantly larger than the pitch between the signal points a n, And thus can be used as an input test point for probe testing. Since the signal points a n are open-circuited, even if the probe test uses the probe point C n as an input point, the circuit cannot be formed between the signal points a n without performing a certain circuit optimization design on the interposer 1, the electrical conduction test of the via 13 cannot be completed. In this embodiment, after signal points a n are mapped to signal mapping points B n of test region 12 by the interposer 1 surface etching circuit, for example, signal mapping points B n are shorted, and probe point C n is used as an input point, An effective test loop is formed between the probe point C n, the signal point a n, the shorted signal mapping point B n, and the electrical conductivity of the via 13 can be tested. It should be noted that, since the interposer 1 provided in this embodiment aims at the electrical conduction test of the via hole 13, the surface etched circuit designed for this improvement is to ensure the yield during the test, on the one hand, the yield of the etched circuit is more guaranteed than the processing yield of the via hole 13, and on the other hand, the surface etched circuit is considered as a reliable premise as the technical means adopted by this embodiment for achieving the test purpose.
Furthermore, it is still more important that the interposer 1 provided in this embodiment can continue to connect the chip and the substrate 6 as the subsequent package component after the above-mentioned test is completed, which is not dedicated to the test, and this is one of the important objects of this embodiment. It should be a temporary short when shorting signal map B n, i.e., the re-shorting should be removed after the test is completed, avoiding that the individual signal points a n are shorted after the chip is attached to the surface of interposer 1, which would render the chip unusable after packaging. Since the number of vias 13 in the interposer 1 is large, but the number of signal points a n to be transferred through the interposer 1 is not so large for a certain type of package, the vias 13 to which these signal points a n are connected need to be tested after the package of the chip is determined, which can be determined after the package is determined. The interposer 1 provided in this embodiment thus makes the above package testing possible.
In the second embodiment, the interposer 1 provided in the present embodiment may form a parallel test loop among the probe point C n, the signal point a n, and the signal mapping point B n.
Based on the first embodiment, the signal points a n are mapped to the signal mapping points B n connected to the test area 12 through the etching circuit on the upper surface of the interposer 1. The surface etched circuitry may be present on the upper or lower surface of the interposer 1, but more preferably is mapped by the upper surface etched circuitry. In this way, the signal point A n can be mapped onto the upper surface of the test area 12 without additionally processing the via hole 13 in the test area 12, so that the test circuit is simplified, and the reject ratio of the test area 12 caused by additionally processing the via hole 13 is avoided. in the case of having three signal points, the present embodiment can form an equivalent circuit diagram as shown in fig. 6. The thick solid line is a temporary short circuit which can be removed, and when the probe point is used as the probe signal input point, the probe point C 1, the signal point A 1, the signal mapping point B 1, the signal mapping point B 2, The signal point A 2 and the probe point C 2 can form a test loop, and the probe point C 1 and the signal point A 1, Another loop in parallel is formed between signal mapping point B 1, signal mapping point B 3, signal point a 3, and probe point C 3. It is apparent that after the aforementioned loop is formed, a corresponding probe point may be selected as a probe signal input point for a probe test to test electrical conductivity between the corresponding probe point and the signal point.
In the third embodiment, the interposer 1 provided in the present embodiment is further optimized based on the second embodiment, and a test loop connected in series may be formed between the probe point Cn, the signal point An, and the signal mapping point Bn.
Specifically, the probe point C n is etched through the lower surface of the interposer 1 and mapped to the probe mapping point D n on the upper surface of the interposer 1 through the via 13, and when the probe mapping point D n and the signal mapping point B n+1 are shorted, a test loop is formed among the probe point C n, the signal point a n and the signal mapping point B n. In this embodiment, the probe point C n is mapped to the upper surface of the test area 12 of the interposer 1, so that all of the probe points C n, the signal points a n and the signal mapping points B n can be connected in series to form a series test circuit by using the vias 13 of the area. Taking four signal points as an example, fig. 7 shows an equivalent circuit diagram. The thick solid line portion of the figure is a temporary removable shorting, where probe point C 2, signal mapping point B 3, and probe point C 3, signal mapping point B 4 are all shorted after being mapped to the upper surface of test area 12 through via 13 of test area 12. The test loop can simplify the input times of the probe points of the probe test, and can conveniently check specific open-circuit bad points.
Embodiment four, as shown in figure 3.
A2.5D package test integrated circuit comprises an interposer 1, wherein the upper surface of a test area 12 is connected with a test chip 2, the lower surface of the test chip 2 is provided with a conductive part 21 which is coupled and connected with a via hole 13 of the interposer 1, and the conductive part 21 is connected with the upper surface of the test chip 2 through a through silicon via 22; the conductive portion 21 is coupled to the signal mapping point B n or the probe mapping point D n, and when the signal mapping point B n is shorted to the upper surface of the test chip 2 or the probe mapping point D n is shorted to the signal mapping point B n+1, a test circuit is formed among the probe point C n, the signal point a n and the signal mapping point B n. In this embodiment, a main purpose is to provide a possible implementation manner of the temporary short circuit described in the first embodiment to the third embodiment. The signal mapping point B n in the present embodiment is mapped to the upper surface of the test chip 2 by the conductive portion 21 of the test chip 2. The temporary shorting may be performed on the upper surface of the test chip 2 with respect to the surface mapping of the interposer 1 in the first to third embodiments. Since the test chip 2 is different from other chips required to realize specific functions, the test chip 2 can be fabricated by a similar structure and process as the interposer 1, but the density of the conductive portions 21 and the through-silicon vias 22 can be lower than those of the interposer 1. And since the test chip 2 does not realize a specific function even after final packaging into a product, the upper surface of the test chip 2 can be destructively removed such as an etched circuit or the like used for realizing temporary shorting, and the function of a subsequent packaged finished product is not affected. Although the test chip 2 occupies a certain package volume, the packaged test integrated circuit provided by the present embodiment can improve the yield of the final packaged product, and thus the sacrifice of the volume is acceptable.
In a more preferred embodiment, the upper surface of the test chip 2 has a conductive layer 23, and the signal mapping point B n or the probe mapping point D n is shorted after being mapped to the conductive layer 23 by the conductive portion 21. The conductive layer 23 on the upper surface of the test chip 2 may be ground and cut away in a subsequent packaging process to remove the aforementioned temporary shorts. As shown in fig. 3, taking three signal points as an example, the signal mapping point B 1 and the signal mapping point B 2 are shorted by the conductive layer 23, after the test is completed, the entire conductive layer 23 may be completely ground and removed, so that the signal point a 1 and the signal point a 2 form an open circuit.
In the fifth embodiment, as shown in fig. 4 and 6, the test chip 2 is used to form a parallel test loop on the basis of the second embodiment.
Specifically, the signal points a n are respectively mapped to the signal mapping points B n connected to the test area 12 through the etching circuit on the upper surface of the interposer 1, and the signal mapping points B n are all shorted to the conductive layer 23 on the upper surface of the test chip 2. The circuit structure of fig. 4 is equivalent to fig. 7, and its circuit configuration is identical to that of the second embodiment. In this embodiment, three signal points are illustrated, and it is apparent that the test loop is similarly constructed when there are a plurality of signal points. Signal point a 1, signal point a 2, signal point a 3 respectively map signal mapping point B 1, signal mapping point B 2, signal mapping point B 3 connected to test area 12 respectively via the upper surface etching circuit of interposer 1, and signal mapping point B 1, signal mapping point B 2, signal mapping point B 3 are shorted on conductive layer 23 on the upper surface of test chip 2.
According to the integrated test circuit provided in the fifth embodiment, the two probe points C n are divided into one group by adopting the following package test method, the electric signals are respectively input into the test signal loop through the probe points C n by using the probes, when the test signal loop in each group of probe tests is normally conducted, the connection between the probe points C n and the signal point a n is normal, Otherwise, judging that the test is abnormally ended. Because of the parallel test loops, it is necessary to perform the probe test on the probe points C n in a group of one by one, and taking fig. 6 as an example, when the probe points C 1 and C 3 are used as probe signal input points, the conductivity of probe point C 1 and signal point a 1 and probe point C 3 and signal point a 3 can be tested, If the conductivity of probe point C 2 and signal point a 2 is to be tested, Then test probe point C 1 and signal point a 1 and probe point C 2 and signal point a 2 are required to be probe signal input points.
In the sixth embodiment, as shown in fig. 5 and 8, the test chip 2 is used to form a series test circuit on the basis of the third embodiment.
In particular, the method comprises the steps of, The signal points a 1 and a 2 are respectively mapped to the signal mapping point B 1 and the signal mapping point B 2 connected to the test area 12 by the surface etching circuit on the interposer 1, The conductive layer 23 is divided into an n-th conductive layer 23n which is not conductive, wherein the signal mapping point B 1 and the signal mapping point B 2 are short-circuited by the first conductive layer 231, and the probe mapping point D n is etched by etching the circuit through the lower surface of the interposer 1 and through the via hole 13, the through silicon via 22 and the n-th conductive layer 23n are connected to the signal mapping point B n+1. The constitution of the test circuit is the same as that provided in the third embodiment, and in this embodiment, the n-th conductive layer 23n may be a short circuit etched on the upper surface of the test chip 2 without connection to each other. The present embodiment is described with four signal points, and it is apparent that the test loop is similarly constructed when there are a plurality of signal points. Probe point C 2 is mapped to probe mapping point D 2 by the circuit on the lower surface of interposer 1 and via hole 13 of test region 12, and signal mapping point B 3 and probe mapping point D 2 are shorted on the upper surface of test chip 2 by second conductive layer 232; Accordingly, probe point C 3 is mapped to probe mapping point D 3 by the circuit on the lower surface of interposer 1 and through via 13 of test region 12, and signal mapping point B 4 and probe mapping point D 3 are shorted to the upper surface of test chip 2 through third conductive layer 233. as can be seen from the equivalent circuit shown in fig. 7, a series test loop is formed between the signal points.
The specific method for performing package test by using the test integrated circuit provided by the embodiment may be: an electrical signal is input to the test signal loop by the probe through probe point C 1 and probe point C n, and when the test signal loop is normally routed in the probe test, the connection between probe point C n and signal point a n is normally indicated, Otherwise, judging that the test piece is bad; If the test result is poor in return, the probe point C 1 is used as an anode, and the probe points C 2 to C n are used as cathodes in sequence for fault detection so as to determine whether an open circuit exists between the probe point C n and the signal point A n. Because the test integrated circuit provided in this embodiment forms a series loop, the probe point C 1 and the probe point C n at the first two ends of the loop can be used as signal input points, for example, any one of the probe point C n and the signal point a n in the loop is open or bad, the whole loop will not conduct and therefore can return directly to the result of failed test. If a specific open circuit or bad signal point needs to be located, the probe point C 1 needs to be further used as an anode, and the probe points C 2 -C n are sequentially used as cathodes for fault detection.
In the seventh embodiment, as shown in fig. 8 to 12, the present embodiment is based on the test method for forming the package test circuit in the above embodiment, and finally forms a package method to ensure the yield of the package.
Specifically, after the packaging test result returns to normal, the formal chip 3 is connected to the signal area 11 to be tested; the formal chip 3 and the test chip 2 are subjected to plastic package protection; flip-chip bonding the interposer 1 to the substrate 6; the test chip 2 is ground or diced until the conductive layer 23 is completely removed such that an open circuit is formed between the signal points a n. The packaging method formed in this way can carry out subsequent packaging after the packaging test is normal, and avoids the defect of the whole packaging finished product caused by the defect of the interposer 1 detected after packaging. And will not affect any function of the packaged regular chip 2 after the conductive layer 23 of the test chip 2 is ground or cut to form an open circuit between the signal points a n.
It is noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.
Although embodiments of the present invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made therein without departing from the principles and spirit of the invention, the scope of which is defined in the appended claims and their equivalents.
Claims (8)
1. A 2.5D packaged test integrated circuit, comprising an interposer (1), wherein the interposer (1) has upper and lower surface etched circuits, and further comprises vias (13) for electrically connecting upper and lower surface signal points, and the interposer (1) is divided into a signal region to be tested (11) and a test region (12), wherein the signal region to be tested (11) has signal points a n, signal points a n are respectively mapped to signal mapping points B n connected to the test region (12) through the interposer (1) surface etched circuits, signal points a n are mapped to probe points C n on the lower surface of the interposer (1) by the vias (13) of the interposer (1), and the probe points C n are mapped to probe mapping points D n on the upper surface of the interposer (1) through the interposer (1) lower surface etched circuits and through the vias (13), wherein n is a natural number greater than 1;
The upper surface of the test area (12) is connected with a test chip (2), the lower surface of the test chip (2) is provided with a conductive part (21) which is coupled and connected with a via hole (13) of the interposer (1), and the conductive part (21) is connected with the upper surface of the test chip (2) through a silicon through hole (22); the conductive part (21) is coupled with the signal mapping point B n or the probe mapping point D n, and when the signal mapping point B n is short-circuited on the upper surface of the test chip (2) or the probe mapping point D n is short-circuited with the signal mapping point B n+1, a test loop is formed among the probe point C n, the signal point A n and the signal mapping point B n.
2. The 2.5D packaged test integrated circuit of claim 1, wherein the signal points a n each map signal mapping points B n connected to the test area (12) through the interposer (1) upper surface etched circuitry.
3. The 2.5D packaged test integrated circuit of claim 2, wherein the upper surface of the test chip (2) has a conductive layer (23), and the signal mapping point B n or the probe mapping point D n is shorted after being mapped to the conductive layer (23) by the conductive portion (21).
4. A 2.5D package test integrated circuit as claimed in claim 3, characterized in that the signal points a n are each mapped by means of an interposer (1) upper surface etching circuit to signal mapping points B n connected to the test area (12), and the signal mapping points B n are all shorted to the conductive layer (23) on the upper surface of the test chip (2).
5. A 2.5D packaged test integrated circuit according to claim 3, wherein signal point a 1 and signal point a 2 are each mapped by an interposer (1) upper surface etched circuit to signal mapping point B 1 and signal mapping point B 2, respectively, connected to test area (12), said conductive layer (23) being distinguished as an nth conductive layer (23 n) which is non-conductive to each other, wherein signal mapping point B 1 and signal mapping point B 2 are shorted by a first conductive layer (231), and said probe mapping point D n is connected to signal mapping point B n+1 by interposer (1) lower surface etched circuit and by via (13), through-silicon via (22), nth conductive layer (23 n).
6. A2.5D packaging test method is characterized in that the 2.5D packaging test integrated circuit as claimed in claim 4 is adopted, two probe points C n are divided into one group, electric signals are respectively input into test signal loops through the probe points C n by using probes, when the test signal loops in each group of probe tests are in normal paths, the connection between the probe points C n and the signal points A n is indicated to be normal, otherwise, the test is judged to be abnormal.
7. A 2.5D package testing method, wherein the integrated circuit is tested by adopting the 2.5D package according to claim 5, and electric signals are input into a test signal loop through a probe point C 1 and a probe point C n by using a probe, when the test signal loop is in a normal path in the probe test, the connection between the probe point C n and the signal point a n is indicated to be normal, otherwise, the connection is judged to be bad; if the test result is poor in return, taking the probe point C 1 as an anode, and sequentially taking the probe points C 2 -C n as cathodes to conduct fault detection so as to determine whether an open circuit exists between the probe point C n and the signal point A n.
8. A 2.5D packaging method, characterized by comprising the 2.5D packaging test method according to claim 6 or 7, and connecting a formal chip (3) on the signal area (11) to be tested after the test result returns to normal; the formal chip (3) and the test chip (2) are subjected to plastic package protection; flip-chip bonding the interposer (1) to the substrate (6); the test chip (2) is lapped or diced until the conductive layer (23) is completely removed such that an open circuit is formed between the signal points a n.
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