CN118281128A

CN118281128A - Light emitting diode and light emitting device

Info

Publication number: CN118281128A
Application number: CN202410403128.6A
Authority: CN
Inventors: 杨人龙; 张平; 林雅雯; 黄事旺; 张中英
Original assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Current assignee: Xiamen Sanan Optoelectronics Technology Co Ltd
Priority date: 2024-04-03
Filing date: 2024-04-03
Publication date: 2024-07-02

Abstract

The invention relates to a light emitting diode, comprising: a semiconductor stack, a first electrode, and a second electrode. The semiconductor lamination comprises a first semiconductor layer, a light-emitting layer and a second semiconductor layer which are sequentially stacked, and a mesa structure exposing a part of the first semiconductor layer; a first electrode formed over the mesa structure and electrically connected to the first semiconductor layer; and a second electrode formed on the second semiconductor layer and electrically connected to the second semiconductor layer. The mesa structure includes a first mesa and a second mesa, the second mesa includes a roughened microstructure, the roughness of the first mesa is less than the roughness of the second mesa, and the first electrode is formed over a portion of the first mesa. Therefore, on the premise of not affecting the electrical performance, the light emitting area is increased, the total internal reflection of photons in the chip is reduced, and the light extraction efficiency of the LED is further improved.

Description

Light emitting diode and light emitting device

Technical Field

The present invention relates to the field of semiconductor devices, and more particularly, to a light emitting diode and a light emitting device.

Background

The light emitting Diode (LIGHT EMITTING Diode, LED) has the advantages of high efficiency, long service life, small volume, low power consumption and the like, and is widely applied to the fields of indoor and outdoor white light illumination, screen display, backlight sources and the like.

At present, the quantum efficiency in most gallium nitride-based LED chips is close to 99%, the light extraction efficiency is generally low, and the most important factor is that the light source generated by the light-emitting layer can be only extracted in a small part due to the fact that a serious total reflection phenomenon exists in the LED chips. In order to improve the light extraction efficiency of the LED chip, the prior art proposes to effectively improve the light extraction efficiency by roughening the entire surface of the N-type semiconductor layer. However, after the roughening morphology of the whole surface is formed on the N-type semiconductor layer, on one hand, the corresponding roughening morphology is formed in the evaporation process of the N-type electrode metal layer, and the surface of the electrode is roughened, so that the reliability of the LED chip is affected; on the other hand, roughening of the N-type semiconductor layer in the current flow path region also affects current conduction, resulting in an increase in voltage. Therefore, how to improve the light extraction efficiency of the LED chip without affecting the photoelectric performance is one of the technical problems to be solved.

Disclosure of Invention

In view of the above-mentioned drawbacks and shortcomings of the prior art, the present invention provides a light emitting diode chip and a light emitting device, by which the light extraction efficiency of the LED chip can be improved without affecting the photoelectric performance.

An embodiment of the present invention provides a light emitting diode chip, including:

A semiconductor stack including a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in this order, and a mesa structure exposing a portion of the first semiconductor layer;

a first electrode formed over the mesa structure and electrically connected to the first semiconductor layer;

A second electrode formed on the second semiconductor layer and electrically connected to the second semiconductor layer;

The method is characterized in that the mesa structure comprises a first mesa and a second mesa, the second mesa comprises a roughened microstructure, the roughness of the first mesa is smaller than that of the second mesa, and the first electrode is formed on part of the first mesa.

According to another aspect of the present invention, there is also provided a light emitting diode chip including:

A semiconductor stack including a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in this order, a mesa structure exposing a portion of the first semiconductor layer, and a sidewall connecting the second semiconductor layer and the mesa structure;

the mesa structure is characterized by comprising a first region, a second region and a third region, wherein the third region comprises a roughened microstructure, the roughness of the first region and the second region is smaller than that of the third region, a first electrode is formed on the first region, and the second region comprises a mesa between a side wall and the first electrode.

According to another aspect of the present invention, there is provided a method of manufacturing a light emitting diode, comprising the steps of:

(1) Providing a substrate, and growing a semiconductor laminated layer formed by sequentially laminating a first semiconductor layer, a light-emitting layer and a second semiconductor layer;

(2) Etching the semiconductor stack from one side of the second semiconductor layer to form a mesa structure exposing a portion of the first semiconductor layer;

(3) The method comprises the steps that a region which is defined on a mesa structure and is not covered by a first electrode and is not where a current flow path is located is subjected to nano roughening treatment;

(4) First and second electrodes are fabricated on the first and second semiconductor layers, respectively.

According to another aspect of the present invention, there is provided a light emitting device employing the light emitting diode provided in any one of the above embodiments.

As described above, the light emitting diode chip and the light emitting device of the present application have the following advantages:

The coarsening microstructure is arranged on the selective part of the N-type semiconductor layer, specifically, the coarsening microstructure is distributed on the table top which is covered by the non-N-type electrode of the N-type semiconductor layer and is not where the current flow path is located. On one hand, the electrode surface roughness caused by the corresponding coarsening morphology formed by the N-type electrode metal layer in the evaporation process can be prevented, so that the reliability of the LED chip is ensured; on the other hand, roughening of the N-type semiconductor layer surface where the current flow path is located can be avoided, so that influence on current conduction is avoided, and the possibility of voltage rise is reduced. In addition, the coarsened microstructure is distributed on the mesa which is covered by the non-N-type electrode and is not where the current flow path is located, and the coarsened microstructure can be distributed on the surface of the region, so that more photons can be emitted from the chip, total reflection is reduced, and the brightness is improved. Therefore, the light extraction efficiency of the LED chip is improved on the premise of not affecting the photoelectric performance.

Additional features and advantages of the invention will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the invention.

Drawings

Fig. 1 is a schematic cross-sectional view of a light emitting diode chip according to a first embodiment of the present invention;

FIG. 2 is an enlarged partial schematic view of area A of FIG. 1;

fig. 3 is a schematic top view of a light emitting diode chip according to a first embodiment of the present invention;

FIG. 4 is a schematic diagram of a current path of a LED chip according to the present invention;

fig. 5 is a schematic cross-sectional structure of a light emitting diode chip according to a second embodiment of the present invention;

FIG. 6 is an enlarged partial schematic view of area A of FIG. 5;

Fig. 7 is a schematic cross-sectional structure of a light emitting diode chip according to a third embodiment of the present invention;

FIG. 8 is an enlarged partial schematic view of area A of FIG. 7;

Fig. 9 is a schematic cross-sectional structure of another led chip according to the third embodiment of the present invention;

FIG. 10 is an enlarged partial schematic view of area A of FIG. 9;

fig. 11 is a schematic cross-sectional structure of another led chip according to the third embodiment of the present invention;

FIG. 12 is an enlarged partial schematic view of area A of FIG. 11;

Fig. 13 is a schematic cross-sectional view of a light emitting diode according to a fourth embodiment of the present invention;

fig. 14 is a schematic top view of a light emitting diode according to a fourth embodiment of the present invention;

Fig. 15 is a schematic cross-sectional view of a light emitting diode chip according to a fifth embodiment of the present invention;

Fig. 16 is a flow chart illustrating a method for manufacturing a light emitting diode device according to an embodiment of the invention.

Description of element numbers:

10-a substrate; 12-a semiconductor stack; 123-a first semiconductor layer; 124-a light emitting layer; 125-a second semiconductor layer; 126-sidewalls; an M-mesa structure; m1-a first mesa; m2-a second mesa; a P1 first region; a P2 second region; a P3 third region; 21-a first electrode; 211-a first electrode pad; 212-a first electrode extension; 22-a second electrode; 221-a second electrode pad; 222-a second electrode extension; 14-a current blocking layer; 16-a transparent conductive layer; 18-an insulating layer; 41-a first bonding pad; 42-a second bonding pad; d-a first distance; 51-interconnect electrode.

Detailed Description

Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. In order to overcome the above-mentioned drawbacks and disadvantages of the prior art, the present invention provides a light emitting diode chip and a light emitting device, which can improve the light extraction efficiency of the LED chip without affecting the photoelectric performance. In some embodiments, a light emitting diode chip includes:

The method is characterized in that the mesa structure comprises a first mesa and a second mesa, the second mesa comprises a roughened microstructure, the roughness of the first mesa is smaller than that of the second mesa, and the first electrode is formed on part of the first mesa. Roughening of the electrode surface not only increases the current conduction distance to cause voltage rise, but also affects the cladding property of the metal layer, and possibly affects the recognition degree of bonding wires during die bonding, thereby affecting the reliability of the chip. Therefore, the coarsened microstructure with smaller roughness is not distributed or distributed on the first table surface covered by the electrode, and the electrode metal layer can be prevented from forming a corresponding coarsened morphology in the evaporation process, so that the light efficiency and the reliability of the LED chip are ensured. On the other hand, the coarsened microstructure with larger distribution roughness is reserved on the second table top, so that more photons can be emitted from the inside of the chip, total reflection is reduced, and the brightness of the chip is improved. Therefore, the light extraction efficiency of the LED chip is improved on the premise of ensuring that the photoelectric performance is not affected.

In some embodiments, the roughness of the first mesa is no greater than 10nm. On the one hand, the coarsening microstructure with smaller roughness can be distributed on the first table surface covered by the electrode, on the other hand, the light extraction efficiency of the LED chip can be improved through the coarsening microstructure, and on the other hand, the coarsening of the surface of the electrode can be reduced, so that the light efficiency and the reliability of the LED chip are ensured to a certain extent.

In some embodiments, the roughness of the first mesa is no greater than 2nm. Coarsened microstructures with smaller roughness are distributed on the first table surface covered by the electrode, so that the reliability of the LED chip is further ensured.

In some embodiments, the first mesa does not include a roughened microstructure. The coarsening microstructure is not distributed on the first table surface covered by the electrode, so that the coarsening of the surface of the electrode can be prevented, and the reliability of the LED chip is further ensured.

In some embodiments, the roughness of the second mesa comprises 4-600 nm. And the coarsened microstructure with larger distribution roughness is reserved on the second table top, so that more photons can be emitted from the inside of the chip, total reflection is reduced, and the light extraction efficiency of the LED chip is improved.

In some embodiments, the roughness ratio of the second mesa and the first mesa is not less than 2 times. Preferably, in some embodiments, the roughness ratio of the second mesa to the first mesa is 3-2000 times. By coarsening the microstructure with the difference in distribution roughness between the first table top and the second table top, the light extraction efficiency of the LED chip is further improved on the premise of not affecting the photoelectric performance.

In some embodiments, the light emitting diode further comprises a sidewall connecting the second semiconductor layer and the mesa structure, the first mesa comprising a mesa between the sidewall and the first electrode. The N-type semiconductor layer between the sidewall and the first electrode generally belongs to a region where a current flow path from the P-type semiconductor to the N-type semiconductor is located, and the inventor researches have found that roughening the surface of the N-type semiconductor layer in this region generally affects current conduction, thereby increasing the voltage of the light emitting diode. Therefore, the coarsened microstructure with smaller roughness is not distributed or distributed on the table surface where the current flow path is located, and the voltage of the LED chip can be effectively reduced.

In some embodiments, the second mesa is formed in a partial region outside of the mesa structure covered by the first electrode.

Preferably, in some embodiments, the area ratio of the second mesa to the region outside the mesa structure covered by the first electrode is not less than 1. The area ratio of the second table surface, namely the area ratio of the coarsened microstructure of the N-type semiconductor layer is ensured, and the light extraction efficiency of the LED chip is improved.

In some embodiments, at least a portion of the first mesa includes a roughened microstructure, the first mesa includes a first region and a second region, the first region has a roughness not greater than a roughness of the second region, the first electrode is formed over the first region, the light emitting diode further includes a sidewall connecting the second semiconductor layer and the mesa, and the second region includes a mesa between the sidewall and the first electrode. Through further dividing the area on the first table top, coarsening microstructures with smaller roughness are not distributed or distributed on the first area covered by the electrode, so that the light efficiency and the reliability of the LED chip are ensured; the coarsening microstructure with a certain small roughness is reserved on the second area where the current flow path is located, so that the area of the coarsening microstructure distributed on the N-type semiconductor layer is increased, the light extraction efficiency is improved, and meanwhile, the voltage of the LED chip can be effectively reduced.

In some embodiments, the first region does not include a roughened microstructure. Coarsening microstructures are not distributed on the first area covered by the electrode, so that the reliability of the LED chip is further ensured.

In some embodiments, the roughness of the second region is no greater than 10nm. The roughness of the second region is controlled, on one hand, the area of the distribution coarsening microstructure of the N-type semiconductor layer is increased, and therefore the light extraction efficiency is improved; on the other hand, the influence on the current conduction can be avoided, and the voltage is reduced.

In some embodiments, the roughness ratio of the second region and the first region is 1 to 100 times. By distributing coarsening microstructures with different roughness in the first area and the second area, the light extraction efficiency of the LED chip is further improved on the premise of not affecting the photoelectric performance.

The present invention also provides a light emitting diode, which in some embodiments includes:

The mesa structure is characterized by comprising a first region, a second region and a third region, wherein the third region comprises a roughened microstructure, the roughness of the first region and the second region is smaller than that of the third region, a first electrode is formed on the first region, and the second region comprises a mesa between a side wall and the first electrode. The coarsened microstructure with smaller roughness is not distributed or distributed on the first area covered by the electrode, so that the electrode metal layer can be prevented from forming a corresponding coarsened morphology in the evaporation process, and the light efficiency and the reliability of the LED chip are ensured; the coarsened microstructure with smaller roughness is not distributed or distributed on the second area where the current flow path is located, so that the voltage of the LED chip can be effectively reduced; and the coarsened microstructure with larger distribution roughness is reserved in the third area, so that more photons can be emitted from the chip, total reflection is reduced, and the brightness of the chip is improved. The exposed N-type semiconductor layer mesa structure is divided into the first area, the second area and the third area, and coarsening microstructures with different roughness are respectively distributed in the three areas, so that the light extraction efficiency of the LED chip is improved on the premise that the photoelectric performance is not affected.

In some embodiments, the roughness of the first region is not greater than the roughness of the second region, the first region not including the roughened microstructure. Coarsening microstructures are not distributed on the first area covered by the electrode, so that the reliability of the LED chip is ensured; meanwhile, a coarsened microstructure with certain roughness is reserved on a second area where the current flow path is located, so that the area of the coarsened microstructure distributed by the N-type semiconductor layer is increased, the photon emission probability is improved, and the brightness of the chip is improved.

In some embodiments, the first region, the second region, and the third region do not include roughened microstructures. Coarsening microstructures are not distributed on the first area and the second area, so that the reliability of the LED chip is further ensured, and the voltage is reduced.

In some embodiments, the roughness of the first region is no greater than 2nm and the roughness of the second region is no greater than 10nm. On one hand, the roughness of the first area and the second area is controlled, and on the other hand, the area of the distribution coarsening microstructure of the N-type semiconductor layer is increased, so that the light extraction efficiency is improved; on the other hand, the influence of the roughening of the electrode surface on the chip reliability is avoided, and the influence on the current conduction is avoided.

In some embodiments, the roughness of the third region comprises 4-600 nm. And a coarsened microstructure with larger distribution roughness is reserved in the third area, so that more photons can be emitted from the chip, total reflection is reduced, and the light extraction efficiency of the LED chip is improved.

In some embodiments, the roughness ratio of the third region and the first region is 15-2000 times, and the roughness ratio of the third region and the second region is 3-2000 times. Further, in some embodiments, the roughness ratio of the second region to the first region is 1 to 100 times. The coarsening microstructures with different roughness are distributed in the three areas respectively, so that the area ratio of the coarsening microstructures of the N-type semiconductor layer is ensured on the premise of not affecting the photoelectric performance, and the light extraction efficiency of the LED chip is improved.

In some embodiments, the roughened microstructure pattern comprises pillars or cones.

The invention provides a manufacturing method of a light emitting diode, which comprises the following steps:

(3) The method comprises the steps that a region which is defined on the mesa structure and is not covered by a first electrode and is not where a current flow path is located is subjected to nano roughening treatment;

(4) And manufacturing a first electrode and a second electrode on the first semiconductor layer and the second semiconductor layer respectively. By only coarsening the microstructure in a region which is not covered by the first electrode and where the non-current flow path is located, the photon emergence rate can be increased through coarsening, so that the brightness of the chip is improved; the roughening of the surface of the electrode can be prevented, so that the reliability of the LED chip is ensured; meanwhile, the influence on current conduction can be prevented, and the voltage of the LED chip is effectively reduced. The light extraction efficiency of the LED chip is improved on the premise of ensuring that the photoelectric performance is not affected.

In some embodiments, the nano-roughening process includes etching the region using metal nanoparticles, polystyrene particles, siO2 nanoparticles, etc. as a mask structure, and then removing the mask structure to form a plurality of nano-pillars in the region. By the method, a coarsened microstructure is formed on the surface of the N-type semiconductor layer, so that the photon emergence rate is increased, total reflection is reduced, and the brightness of the chip is improved.

The invention also provides a light-emitting device which adopts the light-emitting diode provided by any embodiment. The light-emitting device adopting the light-emitting diode chip has good reliability and light-emitting performance.

The technical solutions of the present invention will be clearly and completely described in the following description of various embodiments with reference to the drawings in the examples of the present invention.

Example 1

Referring to fig. 1 to 4, fig. 1 is a schematic cross-sectional structure of a light emitting diode chip according to an embodiment of the present invention, fig. 2 is a partially enlarged schematic view of a region a of fig. 1 (a region circled by a dotted line in fig. 1), fig. 3 is a schematic top view of a light emitting diode chip according to an embodiment of the present invention, that is, fig. 1 is a schematic cross-sectional structure along a direction F-F1 in fig. 3, and fig. 4 is a schematic current flow path of a light emitting diode chip according to an embodiment of the present invention. A first embodiment of the present invention provides a light emitting diode, as shown in the figures, which may include a substrate 10, a semiconductor stack 12, a first electrode 21, and a second electrode 22.

A stack of semiconductor layers 12 is disposed on the substrate 10. The substrate 10 may be an insulating substrate, and preferably, the substrate 10 may be made of a transparent material or a translucent material. In the illustrated embodiment, the substrate 10 is a sapphire substrate. In some embodiments, substrate 10 may be a patterned sapphire substrate, but the present application is not limited thereto. The substrate 10 may also be made of a conductive material or a semiconductor material. For example: the substrate 10 material may include at least one of silicon carbide, silicon, magnesium aluminum oxide, magnesium oxide, lithium aluminum oxide, aluminum gallium oxide, and gallium nitride.

The semiconductor stack 12 includes a first semiconductor layer 123, a light emitting layer 124, and a second semiconductor layer 125. I.e., the light emitting layer 124 is located between the first semiconductor layer 123 and the second semiconductor layer 125. A portion of the upper surface of the first semiconductor layer 123 is not covered with the light emitting layer 124, and a mesa structure M (mesa) is formed where the electrode is mainly disposed.

The first semiconductor layer 123 may be an N-type semiconductor layer, and may supply electrons to the light emitting layer 124 under the power supply. In some embodiments, the first semiconductor layer 123 includes an N-type doped nitride layer. The N-doped nitride layer may include one or more N-type impurities of a group IV element. The N-type impurity may include one of Si, ge, sn, or a combination thereof. In some embodiments, a buffer layer may also be provided between the N-type semiconductor layer and the substrate 10 to mitigate lattice mismatch between the substrate 10 and the N-type semiconductor layer. The buffer layer may include an un-doped AlN layer (u-AlN for short) or an un-doped AlGaN layer (u-AlGaN for short). The N-type semiconductor layer may be bonded to the substrate 10 by an adhesive layer.

The light emitting layer 124 may be a Quantum Well (QW) structure. In some embodiments, the light emitting layer 124 may also be a multiple quantum Well structure (Multiple Quantum Well, abbreviated as MQW), where the multiple quantum Well structure includes multiple quantum Well layers (Well) and multiple quantum Barrier layers (Barrier) alternately arranged in a repetitive manner, and may be, for example, a multiple quantum Well structure such as GaN/AlGaN, inAlGaN/InAlGaN or InGaN/AlGaN. Further, the composition and thickness of the well layer within the light emitting layer 124 determine the wavelength of the generated light. To increase the light emitting efficiency of the light emitting layer 124, this may be achieved by varying the depth of the quantum wells, the number of layers, thickness, and/or other characteristics of the pairs of quantum wells and quantum barriers in the light emitting layer 124.

The second semiconductor layer 125 may be a P-type semiconductor layer, and may provide holes to the light emitting layer 124 under the power supply. In some embodiments, the second semiconductor layer 125 includes a P-type doped nitride layer. The P-doped nitride layer may include one or more P-type impurities of a group II element. The P-type impurity may include one of Mg, zn, be, or a combination thereof.

Although the first semiconductor layer 123 and the second semiconductor layer 125 may have a single-layer structure, respectively, the present disclosure is not limited thereto, and the first semiconductor layer 123 and the second semiconductor layer 125 may have a multi-layer structure having different compositions and may further include a superlattice layer. In addition, the arrangement of the semiconductor stack 12 is not limited thereto, and other kinds of semiconductor stacks 12 may be selected according to actual requirements. For example, in other embodiments, in the case where the first semiconductor layer 123 is doped with a P-type impurity, the second semiconductor layer 125 may be doped with an N-type impurity, i.e., the first semiconductor layer 123 is a P-type semiconductor layer, and the second semiconductor layer 125 is an N-type semiconductor layer.

The first electrode 21 is located over the first semiconductor layer 123. The first electrode 21 may be made of a metal material, which may be a single-layer metal structure, a double-layer metal structure, or a multi-layer metal structure, for example: ti/Al, ti/Al/Ti/Au, ti/Al/Ni/Au, V/Al/Pt/Au, and the like. In some embodiments, the first electrode 21 may be directly formed on the mesa of the first semiconductor layer 123, forming a good ohmic contact with the first semiconductor layer 123. In some embodiments, the first electrode 21 includes a first electrode pad 211 and at least one first electrode extension 212. The first electrode pad 211 is connected to the first electrode extension 212, and the first electrode extension 212 extends from the first electrode pad 211 toward the second electrode 22, so that the current is uniformly diffused. In the present embodiment, please refer to fig. 3, the first electrode 21 includes a first electrode pad 211 and a first electrode extension 212, wherein the first electrode extension 212 has a stripe structure.

The second electrode 22 is located over the second semiconductor layer 125. The second electrode 22 may be made of a metal material, the second electrode 22 may be made of the same or similar material as the first electrode 21, and the second electrode 22 may be made of a different material from the first electrode 21. In some embodiments, the second electrode 22 may include a second electrode pad 221 and a second electrode extension 222. The second electrode pad 221 is connected to the second electrode extension 222, and the second electrode extension 222 extends from the second electrode pad 221 toward the first electrode pad 211, so that the current is uniformly diffused. In the present embodiment, please refer to fig. 3, the second electrode 22 includes a second electrode pad 221 and a second electrode extension 222, wherein the second electrode extension 222 has a stripe structure.

The mesa structure M includes a first mesa M1 and a second mesa M2, the second mesa M2 includes a roughened microstructure, the roughness of the first mesa M1 is smaller than the roughness of the second mesa M2, and the first electrode 21 is formed over a portion of the first mesa M1. In some embodiments, the roughness of the first mesa M1 is not greater than 2nm. Roughening of the electrode surface not only increases the current conduction distance to cause voltage rise, but also affects the cladding property of the metal layer, and possibly affects the recognition degree of bonding wires during die bonding, thereby affecting the reliability of the chip. Therefore, the coarsening microstructure with smaller roughness is distributed on the first table surface M1 covered by the first electrode 21, so that the electrode metal layer can be prevented from forming a corresponding coarsening morphology in the evaporation process, and the light efficiency and the reliability of the LED chip are ensured. On the other hand, the coarsened microstructure with larger distribution roughness is reserved on the second table top M2, so that more photons can be emitted from the inside of the chip, total reflection is reduced, and the brightness of the chip is improved. Therefore, the light extraction efficiency of the LED chip is improved on the premise of ensuring that the photoelectric performance is not affected. Preferably, in some embodiments, the first mesa M1 does not include a roughened microstructure, thereby further ensuring the reliability of the LED chip.

In some embodiments, the roughness of the second mesa M2 comprises 4-600 nm. The coarsening microstructure roughness on the second table top M2 is controlled, so that more photons can be emitted from the inside of the chip, total reflection is reduced, and the light extraction efficiency of the LED chip is improved. Preferably, in some embodiments, the roughness of the second mesa M2 is 30 to 150nm, and more preferably, in some embodiments, the roughness of the second mesa M2 may be 30 to 50nm.

In some embodiments, the roughness ratio of the second mesa M2 and the first mesa M1 is not less than 2 times. Preferably, in some embodiments, the roughness ratio of the second mesa M2 to the first mesa M1 is 3 to 2000 times. By coarsening the microstructure with the difference in distribution roughness between the first table top M1 and the second table top M2, the light extraction efficiency of the LED chip is further improved on the premise of not affecting the photoelectric performance. More preferably, in some embodiments, the roughness ratio of the second mesa M2 to the first mesa M1 is 30 to 150 times, for example, when the roughness of the second mesa M2 is 30 to 50nm, the roughness of the first mesa M1 is 1nm; or when the roughness of the second mesa M2 is 30-50 nm, the first mesa M1 does not include a roughened microstructure, i.e., the roughness of the first mesa M1 is 0.

In some embodiments, the led further includes a sidewall 126 connecting the second semiconductor layer 125 and the mesa structure M, the first mesa M1 includes a mesa between the sidewall 126 and the first electrode 21 (see region P2 in fig. 4), fig. 4 is a schematic view of a current flow path of the led chip provided by the present invention, and the N-type semiconductor layer between the sidewall 126 and the first electrode 21 generally belongs to a region where a current flow path from the P-type semiconductor to the N-type semiconductor is located, and it has been found through the study of the inventor that the surface roughening of the N-type semiconductor layer in this region generally affects the current conduction, thereby resulting in an increase in the voltage of the led. Therefore, the coarsened microstructure with smaller roughness is not distributed or distributed on the table surface (P2 area) where the current flow path is located, and the voltage of the LED chip can be effectively reduced.

In some embodiments, the second mesa M2 is formed in a partial region outside the mesa structure covered by the first electrode 21. Preferably, in some embodiments, the area ratio of the second mesa M2 to the area outside the mesa structure covered by the first electrode 21 is not greater than 1. More preferably, in some embodiments, the area of the second mesa M2 is more than 2 times the area of the region outside the mesa structure covered by the first electrode 21, for example, the area of the second mesa M2 is 3 times or 4 times the area of the region outside the mesa structure covered by the first electrode 21. The area ratio of the second mesa M2, namely the area ratio of the coarsened microstructure of the N-type semiconductor layer, is ensured, and the light extraction efficiency of the LED chip is improved.

In some embodiments, the roughness of the first mesa M1 is not greater than 10nm. Referring to fig. 2, at least a portion of the first mesa M1 includes a roughened microstructure, the first mesa M1 includes a first region P1 and a second region P2, the roughness of the first region P1 is not greater than that of the second region P2, the first electrode 21 is formed on the first region P1, the light emitting diode further includes a sidewall 126 connecting the second semiconductor layer and the mesa structure, and the second region P2 includes a mesa between the sidewall 126 and the first electrode 21. Referring to fig. 3, a region between the first electrode 21 and a line segment between the point a and the point B in fig. 3 is defined as a second region P2 when viewed from above the light emitting diode toward the semiconductor stack 12. Through further dividing the area on the first table top M1, coarsening microstructures with smaller roughness are not distributed or distributed on the first area P1 covered by the electrode, so that the light efficiency and the reliability of the LED chip are ensured; the coarsened microstructure with certain roughness is reserved on the second region P2 where the current flow path is located, so that the area of the coarsened microstructure distributed by the N-type semiconductor layer is increased, the probability that photons can exit from the chip can be improved, and the light extraction efficiency is improved.

In some embodiments, the roughness of the first region P1 is not greater than 2nm. Coarsening microstructures with smaller roughness are distributed on the first area P1 covered by the electrode, so that the light extraction efficiency of the LED chip is improved, and meanwhile, the reliability of the LED chip is ensured to a certain extent. Preferably, in some embodiments, the first region P1 does not include a roughened microstructure, thereby further ensuring the reliability of the LED chip.

In some embodiments, the roughness of the second region P2 is not greater than 10nm. Preferably, the roughness of the second region P2 is 2 to 10nm. The roughness of the second region P2 is controlled, on one hand, the area of the distribution coarsening microstructure of the N-type semiconductor layer is increased, and therefore the light extraction efficiency is improved; on the other hand, the influence on the current conduction can be avoided, and the voltage is reduced. In some embodiments, the second region P2 may not include a roughened microstructure, which may effectively reduce the voltage of the LED chip.

In some embodiments, the roughness ratio of the second region P2 to the first region P1 is 1 to 100 times. By coarsening the microstructure with the difference of the distribution roughness in the first region P1 and the second region P2, the light extraction efficiency of the LED chip is further improved on the premise of not affecting the photoelectric performance. More preferably, in some embodiments, the roughness ratio of the second region P2 to the first region P1 is 1 to 50 times, for example, when the roughness of the second mesa M2 is 2 to 10nm, the roughness of the first mesa M1 is 1nm; or when the roughness of the second mesa M2 is 2-10 nm, the first mesa M1 does not include a roughened microstructure, i.e., the roughness of the first mesa M1 is 0.

The current blocking layer 14 is located on the second semiconductor layer 125, and is used for blocking the current flowing vertically into the second semiconductor layer 125 from the upper electrode, and the current blocking layer 14 is a transparent insulating material, and includes at least one of transparent inorganic insulating materials such as silicon oxide, silicon nitride, silicon oxynitride, titanium oxide, or aluminum oxide. The current blocking layer 14 may also be a single layer or an alternating multi-layer structure, and the single layer may be a material having a high light transmittance, for example, more than 80%, such as silicon oxide. The current blocking layer 14 may also be a multilayer structure combined to form a reflective material, such as a Bragg reflector, with a reflectivity of greater than 60%. The thickness of the current blocking layer 14 may be selected from any thickness ranging from 50nm to 500nm, but the embodiments of the present disclosure are not limited thereto. In some embodiments, the current blocking layer 14 may be continuously distributed or discontinuously distributed, and the continuously distributed current blocking layer may effectively enhance the effect of blocking the current flowing vertically into the second semiconductor layer 125 from the upper electrode, and the discontinuously distributed current blocking layer may increase the contact between the electrode and the epitaxial layer, enhance the adhesion of the electrode, and enhance the wire bonding capability, which is not limited in this embodiment. Further, in some embodiments, the current blocking layer 14 may also be disposed between the first electrode 21 and the first semiconductor layer 123, which is not limited in this disclosure.

The transparent conductive layer 16 is located on the second semiconductor layer 125, and is used for guiding the current to be injected into the second semiconductor layer 125 from the upper electrode more uniformly, so as to achieve the effect of current expansion. As an example, the transparent conductive material may include Indium Tin Oxide (ITO), zinc indium oxide (indium zinc oxide, IZO), indium oxide (InO), tin oxide (tin oxide, snO), cadmium tin oxide (cadmium tin oxide, CTO), tin antimony oxide (antimony tin oxide, ATO), aluminum zinc oxide (aluminum zinc oxide, AZO), zinc tin oxide (zinc tin oxide, ZTO), zinc oxide doped gallium (gallium doped zinc oxide, GZO), indium oxide doped tungsten (tungsten doped indium oxide, IWO), or zinc oxide (zinc oxide, znO), but the embodiments of the present disclosure are not limited thereto.

In some embodiments, the light emitting diode further comprises a protective layer 18, the protective layer 18 covering the sidewalls and part of the upper surface of the semiconductor stack 12 and the transparent conductive layer 16, the first electrode 21 and the second electrode 22. The protective layer 18 has an opening, and the first electrode 21 and the second electrode 22 are located in the opening of the protective layer 18 to facilitate subsequent wire bonding. The protection layer 18 has different functions according to the related location, for example, covering the sidewall of the epitaxial layer to prevent the conductive material from leaking so that the first semiconductor layer 123 and the second semiconductor layer 125 are electrically connected, so as to reduce the abnormal short circuit of the led chip, but the embodiment of the disclosure is not limited thereto. In some embodiments, the material of the protective layer 18 comprises a non-conductive material. The non-conductive material is preferably an inorganic material or a dielectric material. The inorganic material comprises silica gel (Silicone) or Glass (Glass). The dielectric material including aluminum oxide (AlO), silicon nitride (SiNx), silicon oxide (SiOx), titanium oxide (TiOx), or magnesium fluoride (MgFx) may be an electrically insulating material. For example, the protective layer 18 may be silicon dioxide, silicon nitride, titanium oxide, tantalum oxide, niobium oxide, barium titanate, or a combination thereof, such as a Bragg reflector (DBR) formed by repeated stacking of two materials.

Example 2

Referring to fig. 5 to fig. 6, fig. 5 is a schematic cross-sectional structure of a light emitting diode chip according to a second embodiment of the invention, and fig. 6 is an enlarged partial schematic view of a region a of fig. 5. Compared with the light emitting diode of the first embodiment of fig. 1 and 2, the light emitting diode of the second embodiment mainly comprises the following differences: the area of the first mesa M1 is flared so that the area of the first region P1 is larger than the area of the first electrode 21, and in some embodiments, the distance d between the edge of the first region P1 and the corresponding sidewall of the first electrode 21 is 0 to 5 micrometers, preferably, in some embodiments, the distance d between the edge of the first region P1 and the sidewall of the first electrode is within 3 micrometers, for example, the distance d between the edge of the first region P1 and the sidewall of the first electrode is 1 micrometer, 2 micrometers, and 3 micrometers. Or in some embodiments, the diameter of the first region P1 is 0 to 5 micrometers greater than the diameter of the corresponding first electrode pad 211, and preferably, in some embodiments, the diameter of the first region P1 is 1 to 3 micrometers greater than the diameter of the corresponding first electrode pad 211. The problems that local color difference of the electrode and poor coating property of the periphery of the electrode are caused by the fact that local electrodes possibly cover a coarsening structure due to alignment deviation during electrode coating are prevented, and metal reflectivity is affected due to the fact that the thickness difference of the coating is caused are solved.

Example 3

Referring to fig. 7 to 12, fig. 7, 9 and 11 are schematic cross-sectional views of three led chips according to a third embodiment of the present invention, fig. 8 is a partially enlarged schematic view of a region a of fig. 7, fig. 10 is a partially enlarged schematic view of a region a of fig. 9, and fig. 12 is a partially enlarged schematic view of a region a of fig. 11. Compared with the light emitting diode of the first embodiment of fig. 1 and 2, the light emitting diode of the third embodiment mainly comprises the following differences: the mesa structure M includes a first region P1, a second region P2, and a third region P3, the third region P3 includes a roughened microstructure, the roughness of the first region P1 and the second region P2 is smaller than that of the third region P3, the first electrode 21 is formed over the first region P1, and the second region P2 includes a mesa between the sidewall 126 and the first electrode 21. The coarsened microstructure with smaller roughness is not distributed or distributed on the first area P1 covered by the electrode, so that the electrode metal layer can be prevented from forming a corresponding coarsened morphology in the evaporation process, and the light efficiency and the reliability of the LED chip are ensured; the coarsened microstructure with smaller roughness is not distributed or distributed on the second region P2 where the current flow path is located, so that the voltage of the LED chip can be effectively reduced; and the coarsened microstructure with larger distribution roughness is reserved in the third region P3, so that more photons can be emitted from the inside of the chip, the occurrence of total reflection is reduced, and the brightness of the chip is improved. The exposed N-type semiconductor layer mesa structure M is divided into the first region P1, the second region P2 and the third region P3, and coarsening microstructures with different roughness are respectively distributed in the three regions, so that the light extraction efficiency of the LED chip is improved on the premise of not affecting the photoelectric performance.

In some embodiments, the roughness of the first region P1 is not greater than the roughness of the second region P2, the first region P1 not including a roughened microstructure. Coarsening microstructures are not distributed on the first area P1 covered by the electrode, so that the coarsening of the surface of the electrode is prevented, and the reliability of the LED chip is ensured; meanwhile, a coarsened microstructure with certain roughness is reserved on the second region P2 where the current flow path is located, so that the area of the coarsened microstructure distributed by the N-type semiconductor layer is increased, and the brightness of the chip is improved.

Preferably, in some embodiments, neither the first region P1 nor the second region P2 includes a roughened microstructure. Coarsening microstructures are not distributed on the first region P1 and the second region P2, so that the reliability of the LED chip is further ensured, and the voltage is reduced.

In some embodiments, the roughness of the first region P1 is not greater than 2nm and the roughness of the second region P2 is not greater than 10nm. The roughness of the first region P1 and the second region P2 is controlled, on one hand, the area of the N-type semiconductor layer distribution coarsening microstructure is increased, and therefore the light extraction efficiency is improved; on the other hand, the influence of the roughening of the electrode surface on the chip reliability is avoided, and the influence on the current conduction is avoided. Preferably, in some embodiments, the first region P1 does not include a roughened microstructure, and the roughness of the second region P2 is 2-10 nm.

In some embodiments, the roughness of the third region P3 comprises 4-600 nm. The coarsening of the third region P3 can enable more photons to be emitted from the inside of the chip, so that total reflection is reduced, and the light extraction efficiency of the LED chip is improved. Preferably, in some embodiments, the roughness of the second mesa M2 is 30 to 150nm, and more preferably, in some embodiments, the roughness of the second mesa M2 may be 30 to 50nm.

Preferably, in some embodiments, the ratio of the area of the third region P3 to the sum of the areas of the second region P2 and the third region P3 is not greater than 1. More preferably, in some embodiments, the area of the third region P3 is more than 2 times of the sum of the areas of the second region P2 and the third region P3, and the larger the area ratio of the roughened microstructure of the N-type semiconductor layer is, the more advantageous to improve the light extraction efficiency of the LED chip.

In some embodiments, the roughness ratio of the third region P3 to the first region P1 is 15 to 2000 times, and the roughness ratio of the third region P3 to the second region P2 is 3 to 2000 times. Further, in some embodiments, the roughness ratio of the second region P2 to the first region P1 is 1 to 100 times. For example, referring to fig. 7 and 8, when the roughness of the third region P3 is 30-100 nm, the roughness of the second region P2 is 2-10 nm, and the roughness of the first region P1 is 0; or referring to fig. 9 and 10, when the roughness of the third region P3 is 30-100 nm, the roughness of the second region P2 and the first region P1 is less than 2nm, and the roughness of the second region P2 is equal to the roughness of the first region P1; or referring to fig. 11 and 12, when the roughness of the third region P3 is 30-100 nm, the roughness of the second region P2 is 2-10 nm, and the roughness of the first region P1 is less than 2 nm. The coarsening microstructures with different or stepped roughness are distributed in the three areas respectively, so that the area ratio of the coarsening microstructures of the N-type semiconductor layer is ensured on the premise of not affecting the photoelectric performance, and the light extraction efficiency of the LED chip is improved. Of course, the present embodiment may further include, for example, when the roughness of the third region P3 is 30-100 nm, and the roughness of the second region P2 and the roughness of the first region P1 are both 0 (not shown in the drawings), and the roughness of the three regions may be combined and matched arbitrarily on the premise of meeting the scope of the present invention, which is not limited in the embodiments disclosed herein.

Example 4

Referring to fig. 13 to 14, fig. 13 is a schematic cross-sectional structure of a light emitting diode chip according to a fourth embodiment of the present invention, and fig. 14 is a schematic top view of a light emitting diode according to a fourth embodiment of the present invention. Compared to the light emitting diode of the first embodiment of fig. 3, the light emitting diode of the fourth embodiment mainly differs in that: the light emitting diode of the present embodiment is a flip-chip diode, and further includes a first pad 41 and a second pad 42, where the first pad 41 and the second pad 42 are connected to the first electrode 21 and the second electrode 22, respectively, through openings of the protective layer 18. The light emitting diode of the first embodiment is a diode with a forward structure.

Example 5

Referring to fig. 15, fig. 15 is a schematic cross-sectional structure of a led chip according to a fifth embodiment of the invention. The light emitting diode provided in each of the embodiments is applicable not only to the chips of the normal mounting structure and the flip chip structure shown in fig. 1 and 13, but also to the chips of the high voltage structure. As shown in the drawing, the chip of the high voltage structure includes a plurality of light emitting units, a substrate 10 and an insulating layer 18, wherein adjacent light emitting units are isolated from each other by isolation grooves on the substrate 10, and are electrically connected by interconnection electrodes 61 crossing over the isolation grooves. A second current blocking layer 15 is disposed below the interconnection electrode 61 to achieve a current blocking effect, so as to avoid a current aggregation phenomenon.

Further, each light emitting unit includes a semiconductor stack 12, and the semiconductor stack 12 includes a first semiconductor layer 123, a light emitting layer 124, and a second semiconductor layer 125. Each light emitting cell further includes a first electrode 21 electrically connected to the first semiconductor layer 123 or a second electrode 22 electrically connected to the second semiconductor layer 125. Wherein a current blocking layer 14 as described in the above embodiments is provided under the second electrode 22. Reference should be made to the foregoing for additional details, features and advantages, and no further details will be provided herein.

Example 6

The embodiment also provides a method for manufacturing a light emitting diode element, as shown in fig. 16, which includes the following steps:

(1) Providing a substrate 10, growing a semiconductor laminated layer 12 formed by sequentially stacking a first semiconductor layer 123, a light-emitting layer 124 and a second semiconductor layer 125;

referring to fig. 1, a substrate 10 is a transparent substrate, such as a sapphire substrate or the like. An epitaxial growth is performed on the substrate 10, and a first semiconductor layer 123, a light emitting layer 124, and a second semiconductor layer 125 are grown in this order. In this embodiment, the first semiconductor layer 123 is an N-type layer, and the second semiconductor layer 125 is a P-type layer.

(2) Etching the semiconductor stack 12 from one side of the second semiconductor layer 125 to form a mesa structure M exposing a portion of the first semiconductor layer 123;

referring again to fig. 1, semiconductor stack 12 is etched down from one side of second semiconductor layer 125 until first semiconductor layer 123 is exposed to form mesa structure M. Alternatively, the second semiconductor layer 125, the light emitting layer 124 are sequentially etched from one side of the second semiconductor layer 125 until the first semiconductor layer 123 is exposed, or the second semiconductor layer 125, the light emitting layer 124 and a portion of the first semiconductor layer 123 are sequentially etched from one side of the second semiconductor layer 125 to expose the first semiconductor layer 123. The semiconductor stack 12 remaining around the mesa structure M forms the light exit region of the light emitting diode element.

(3) A region which is defined on the mesa structure M and is not covered by the first electrode 21 and is not where a current flow path is located is subjected to nano roughening treatment;

Referring to fig. 2, a region, which is defined on the mesa structure M and is not covered by the first electrode 21 and is not where a current flow path is located, is a second mesa M2, and the second mesa M2 is subjected to nano-roughening treatment. In some embodiments, the roughness of the second mesa M2 comprises 4-600 nm. Preferably, in some embodiments, the roughness of the second mesa M2 is 30 to 150nm, and more preferably, in some embodiments, the roughness of the second mesa M2 may be 30 to 50nm.

Further, in an alternative embodiment, the first mesa M1 may define a first region P1 covered by the first electrode 21 and a second region P2 where the current flow path is located, and nano-roughening treatment is performed on the second region P2, where in some embodiments, the roughness of the second region P2 includes 2-10 nm.

Further, in another alternative embodiment, the first region P1 may be further subjected to micro-nano roughening treatment, and in some embodiments, the roughness of the first region P1 is 2nm or less.

The nano roughening treatment method comprises the steps of adopting metal nano particles, polystyrene particles, siO2 nano particles and the like as mask structures, carrying out etching process treatment on the area, and then removing the mask structures to form a large number of nano columns in the area.

(4) A first electrode 21 and a second electrode 22 are fabricated on the first semiconductor layer 123 and the second semiconductor layer 125, respectively.

Referring to fig. 1 and3, the first electrode 21 is located on the first semiconductor layer 123. The first electrode 21 may be made of a metal material, which may be a single-layer metal structure, a double-layer metal structure, or a multi-layer metal structure, and in some embodiments, the first electrode 21 may be directly formed on the mesa of the first semiconductor layer 123 to form a good ohmic contact with the first semiconductor layer 123. In some embodiments, the first electrode 21 includes a first electrode pad 211 and at least one first electrode extension 212. The first electrode pad 211 is connected to the first electrode extension 212, and the first electrode extension 212 extends from the first electrode pad 211 toward the second electrode 22, so that the current is uniformly diffused.

The second electrode 22 is located over the second semiconductor layer 125. The second electrode 22 may be made of a metal material, the second electrode 22 may be made of the same or similar material as the first electrode 21, and the second electrode 22 may be made of a different material from the first electrode 21. In some embodiments, the second electrode 22 may include a second electrode pad 221 and a second electrode extension 222. The second electrode pad 221 is connected to the second electrode extension 222, and the second electrode extension 222 extends from the second electrode pad 221 toward the first electrode pad 211, so that the current is uniformly diffused.

The invention also provides a light-emitting device which adopts the light-emitting diode provided by any embodiment. The light emitting diode may be of a size of Micro LED, mini LED or conventional LED. The light emitting diode can be applied to a backlight display or an RGB display screen, and the small-sized flip-chip light emitting diode can be integrally mounted on an application substrate or a package substrate in the number of hundreds or thousands or tens of thousands to form a light emitting source part of the backlight display device or the RGB display device.

It should be noted that the method for measuring roughness according to the present invention includes: the line width of the microstructure is measured to be the roughness of the microstructure by photographing with a high power microscope, measuring with a roughness measuring instrument, scanning with an SEM scanning electron microscope, scanning with a FIB focusing ion beam microscope, and the like, for example, under the condition that the image magnification is 200 times to 1000 times, and the coarsened microstructure expressed by the invention comprises a regular columnar shape, a regular cone shape, a regular hemispherical shape, a regular spheroid shape, or a coarsened shape such as an irregular columnar shape, an irregular cone shape, an irregular hemispherical shape, an irregular spheroid shape, and the like.

In summary, according to the light emitting diode and the light emitting device provided by the embodiment of the invention, the roughened microstructure is selectively arranged on the mesa of the N-type semiconductor layer, so that on one hand, the roughening of the surface of the electrode can be prevented, and the reliability of the LED chip is ensured; on the other hand, the influence on the current conduction can be avoided, and the voltage rise can be prevented. In addition, the coarsened microstructures are distributed on a part of the table top, so that more photons can be emitted from the chip, total reflection is reduced, and the brightness is improved. Therefore, the light-emitting diode has good photoelectric performance while increasing light extraction efficiency.

In addition, it should be understood by those skilled in the art that although there are many problems in the prior art, each embodiment or technical solution of the present invention may be modified in only one or several respects, without having to solve all technical problems listed in the prior art or the background art at the same time. Those skilled in the art will understand that nothing in one claim should be taken as a limitation on that claim.

Finally, it should be noted that: the above embodiments are only for illustrating the technical solution of the present invention, and not for limiting the same; although the invention has been described in detail with reference to the foregoing embodiments, it will be understood by those of ordinary skill in the art that: the technical scheme described in the foregoing embodiments can be modified or some or all of the technical features thereof can be replaced by equivalents; such modifications and substitutions do not depart from the spirit of the invention.

Claims

1. A light emitting diode, comprising:

A semiconductor laminate including a first semiconductor layer, a light emitting layer, and a second semiconductor layer stacked in this order, and a mesa structure exposing a portion of the first semiconductor layer;

The micro-structure comprises a first mesa and a second mesa, wherein the second mesa comprises a roughened micro-structure, the roughness of the first mesa is smaller than that of the second mesa, and the first electrode is formed on part of the first mesa.

2. A light emitting diode according to claim 1 wherein: the roughness of the first mesa is not more than 10nm.

3. A light emitting diode according to claim 1 wherein: the roughness of the first mesa is not more than 2nm.

4. A light emitting diode according to claim 1 wherein: the first mesa does not include a roughened microstructure.

5. A light emitting diode according to claim 1 wherein: the roughness of the second table top comprises 4-600 nm.

6. A light emitting diode according to claim 1 wherein: the roughness ratio of the second mesa to the first mesa is not less than 2 times.

7. A light emitting diode according to claim 1 wherein: the roughness ratio of the second table top to the first table top is 3-2000 times.

8. A light emitting diode according to claim 1 wherein: the light emitting diode further includes a sidewall connecting the second semiconductor layer and the mesa structure, the first mesa including a mesa between the sidewall and the first electrode.

9. A light emitting diode according to claim 1 wherein: the second mesa is formed in a partial region outside the mesa structure covered by the first electrode.

10. A light emitting diode according to claim 9 wherein: the area ratio of the second mesa to the area outside the mesa structure covered by the first electrode is not less than 1.

11. A light emitting diode according to claim 3 wherein: at least a portion of the first mesa includes a roughened microstructure, the first mesa includes a first region having a roughness not greater than a roughness of the second region, the first electrode is formed over the first region, the light emitting diode further includes a sidewall connecting the second semiconductor layer and the mesa structure, and a second region including the sidewall to the mesa between the first electrode.

12. A light emitting diode according to claim 11 wherein: the first region does not include a roughened microstructure.

13. A light emitting diode according to claim 11 wherein: the roughness of the second region is not greater than 10nm.

14. A light emitting diode according to claim 11 wherein: and the roughness ratio of the second area to the first area is 1-100 times.

15. A light emitting diode, comprising:

The mesa structure is characterized by comprising a first region, a second region and a third region, wherein the third region comprises a roughened microstructure, the roughness of the first region and the second region is smaller than that of the third region, the first electrode is formed on the first region, and the second region comprises a mesa between the side wall and the first electrode.

16. A light emitting diode according to claim 15 wherein: the roughness of the first region is not greater than the roughness of the second region, and the first region does not include a roughened microstructure.

17. A light emitting diode according to claim 15 wherein: the first and second regions do not include roughened microstructures.

18. A light emitting diode according to claim 15 wherein: the roughness of the first region is not more than 2nm, and the roughness of the second region is not more than 10nm.

19. A light emitting diode according to claim 15 wherein: the roughness of the third region comprises 4-600 nm.

20. A light emitting diode according to claim 15 wherein: the roughness ratio of the third area to the first area is 15-2000 times, and the roughness ratio of the third area to the second area is 3-2000 times.

21. A light emitting diode according to claim 18 wherein: and the roughness ratio of the second area to the first area is 1-100 times.

22. A light emitting diode according to claim 1 or 15 wherein: the roughened microstructure pattern includes columnar or tapered shapes.

23. A method of manufacturing a light emitting diode, comprising the steps of:

(4) And manufacturing a first electrode and a second electrode on the first semiconductor layer and the second semiconductor layer respectively.

24. The method of claim 23, wherein the nano-roughening treatment comprises etching the region using metal nanoparticles, polystyrene particles, siO2 nanoparticles, etc. as a mask structure, and removing the mask structure to form a plurality of nano-pillars in the region.

25. A light emitting device, characterized in that: the light-emitting device employs the light-emitting diode according to any one of claims 1 to 24.