CN118278336A

CN118278336A - Time sequence adjustment method, device, equipment and medium

Info

Publication number: CN118278336A
Application number: CN202410390194.4A
Authority: CN
Inventors: 李贤佳; 曾昭贵; 高旭; 周颖; 冯凯丽; 张宇
Original assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Current assignee: Shandong Yunhai Guochuang Cloud Computing Equipment Industry Innovation Center Co Ltd
Priority date: 2024-03-31
Filing date: 2024-03-31
Publication date: 2024-07-02

Abstract

The invention discloses a time sequence adjusting method, a time sequence adjusting device and a time sequence adjusting medium, and relates to the technical field of integrated circuits. The scheme provides a useful deviation execution mode of bidirectional sequential continuous borrowing, and the sequential allowance of the front and rear paths of a critical path with a sequential violation is considered, so that the sequential allowance is borrowed from the front and rear paths when the sequential violation of the critical path is corrected, and the convergence of the sequential is quickened. In addition, when the timing margin of the front-stage path and the rear-stage path is insufficient, the scheme can continuously borrow the timing margin of the front-stage path and the rear-stage path, so that the timing margin in the integrated circuit design is fully utilized, the iteration time and the stronger dependence of rear-end staff on EDA tools are reduced, and the timing convergence efficiency is greatly improved.

Description

Time sequence adjustment method, device, equipment and medium

Technical Field

The present invention relates to the field of integrated circuits, and in particular, to a timing adjustment method, apparatus, device, and medium.

Background

In integrated circuit (INTEGRATED CIRCUIT, IC) design (design), sequential logic becomes the basis for chip operation because it can memorize and implement pipelining. The most important in the chip design is to ensure that the register collects correct data, namely, the time sequence requirement is met, and the time sequence convergence is ensured.

For the current large-scale and high-frequency IC design, the situation that the timing cannot be converged often occurs, and the logic total delay of most critical paths is larger. Among the plurality of timing optimization methods, the method for optimizing the timing of the critical path based on the useful deviation (useful skew) is an effective and relatively easy-to-implement method, and specifically determines the critical path with the timing violation, and borrows the timing margin to the previous stage path or the next stage path of the critical path, thereby correcting the timing violation of the critical path. However, in the above manner, when there is a timing margin in both the former-stage path and the latter-stage path of the critical path, the critical path borrows only the timing margin of one of the stages, resulting in insufficient timing margin borrowing; in addition, when the timing margin of the previous stage path or the next stage path of the critical path is insufficient, the repair of the critical path timing violation cannot be realized.

In view of the above, how to solve the problem that the critical path timing cannot be corrected due to insufficient borrowing of the timing margin by the current useful deviation function is a urgent problem for those skilled in the art.

Disclosure of Invention

The invention aims to provide a time sequence adjusting method, a device, equipment and a medium, which are used for solving the problem that the time sequence of a critical path cannot be corrected due to insufficient borrowing of time sequence allowance by the current useful deviation function.

In order to solve the above technical problems, the present invention provides a timing adjustment method, including:

determining a time sequence allowance of a connecting path among all data triggers in the integrated circuit design, and determining a time sequence violation value of a critical path;

Acquiring the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path, and determining the time sequence allowance sum of the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path; wherein N is a positive integer;

Judging whether the time sequence allowance sum is not smaller than the time sequence violation value;

If yes, borrowing the time sequence allowance of the front N-level connecting paths and the time sequence allowance of the rear N-level connecting paths to the critical paths according to a preset borrowing proportion so as to correct the time sequence of the critical paths;

If not, the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path are all borrowed to the critical path, the rest time sequence violation value is determined, N is set to be N plus 1, and the step of obtaining the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path is returned.

In one aspect, the determining the timing margin of the connection paths between the data flip-flops in the integrated circuit design and determining the timing violation value of the critical path includes:

Acquiring a clock cycle of an integrated circuit design, and acquiring clock delay of each data trigger; the clock delay represents the time sequence value from the clock definition point to the clock pin of the corresponding data trigger;

acquiring a time sequence value of a connecting path corresponding to each data trigger;

Respectively summing the clock delay and the clock period of each data trigger to obtain a plurality of first time sequence amounts;

Respectively summing the time sequence value of the connecting path corresponding to each data trigger with the clock delay of the previous data trigger corresponding to each data trigger to obtain a plurality of second time sequence amounts;

Respectively obtaining the difference value of each first time sequence quantity and the corresponding second time sequence quantity to obtain the time sequence allowance of the connecting path between each data trigger;

And taking a connection path with a negative timing margin as the critical path, and taking the absolute value of the corresponding timing margin as the timing violation value of the critical path.

In another aspect, before the determining whether the timing margin sum is not less than the timing violation value, after the determining the timing margin sum of the timing margin of the front N-stage connection path and the timing margin sum of the timing margin of the rear N-stage connection path, further includes:

Judging whether the sum of the time sequence allowance is not less than 0;

If the time sequence allowance sum is not smaller than 0, the step of judging whether the time sequence allowance sum is not smaller than the time sequence violation value is carried out;

And if the time sequence allowance sum is less than 0, setting N as N plus 1, and returning to the step of acquiring the time sequence allowance of the front N-stage connecting path and the time sequence allowance of the rear N-stage connecting path of the critical path.

Judging whether the time sequence allowance sum is not smaller than the time sequence reservation total amount; the total time sequence reservation amount is the sum of the time sequence reservation amount of the front N-stage connecting paths and the time sequence reservation amount of the rear N-stage connecting paths;

if the time sequence allowance sum is not smaller than the time sequence reservation total amount, the step of judging whether the time sequence allowance sum is not smaller than the time sequence violation value is carried out;

And if the time sequence allowance sum is confirmed to be smaller than the time sequence reservation total amount, setting N to be N plus 1, and returning to the step of acquiring the time sequence allowance of the front N-stage connecting paths and the time sequence allowance of the rear N-stage connecting paths of the critical path.

In another aspect, the determining whether the timing margin sum is not less than the timing violation value includes:

judging whether the time sequence allowance sum is not smaller than the sum of the time sequence violation value and the time sequence reservation total amount;

If yes, entering a step of borrowing the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path to the key path according to a preset borrowing proportion;

If not, entering a step of borrowing all the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path to the critical path and determining the rest time sequence violation value;

Correspondingly, the borrowing the timing sequence margin of the front N-level connection path and the timing sequence margin of the rear N-level connection path to the critical path according to the preset borrowing proportion comprises the following steps:

determining the quotient of the timing violation value, the timing allowance and the sum of the timing violation value and the timing allowance to obtain a preset borrowing proportion;

Determining the difference value between the time sequence allowance of the front N-stage connecting path and the corresponding time sequence reservation amount to obtain borrowable time sequence allowance of the front N-stage connecting path;

Determining the difference value between the time sequence allowance of the rear N-level connecting path and the corresponding time sequence reservation amount to obtain borrowable time sequence allowance of the rear N-level connecting path;

Determining the product of the preset borrowing proportion and the borrowable time sequence allowance of the previous N-level connecting paths to obtain borrowed time sequence quantity of the previous N-level connecting paths;

Determining the product of the preset borrowing proportion and the borrowable time sequence allowance of the rear N-level connecting path to obtain the borrowed time sequence quantity of the rear N-level connecting path;

Borrowing the borrowed time sequence quantity of the front N-level connecting paths and the borrowed time sequence quantity of the rear N-level connecting paths to the key paths.

In another aspect, the borrowing the borrowed timing quantity of the front N-level connection path and the borrowed timing quantity of the rear N-level connection path to the critical path includes:

Determining a first clock delay adjustment value of a data trigger corresponding to the previous N-stage connecting path according to the borrowing time sequence quantity of the previous N-stage connecting path;

Determining a second clock delay adjustment value of the data trigger corresponding to the rear N-level connection path according to the borrowed time sequence quantity of the rear N-level connection path;

And adjusting the clock delay of the data trigger corresponding to the front N-level connecting path according to the first clock delay adjustment value, and adjusting the clock delay of the data trigger corresponding to the rear N-level connecting path according to the second clock delay adjustment value so as to borrow the borrowed time sequence quantity of the front N-level connecting path and the borrowed time sequence quantity of the rear N-level connecting path to the critical path.

On the other hand, after setting N to N plus 1, it further includes:

Monitoring the value of N, and judging whether N is larger than a threshold value;

If the N is confirmed to be larger than the threshold value, stopping the time sequence borrowing process of the current critical path;

And outputting an error prompt and generating a time sequence borrowing log.

In order to solve the above technical problem, the present invention further provides a timing adjustment device, including:

the determining module is used for determining the time sequence allowance of the connecting paths among the data triggers in the integrated circuit design and determining the time sequence violation values of the critical paths;

The acquisition module is used for acquiring the time sequence allowance of the front N-level connection path and the time sequence allowance of the rear N-level connection path of the critical path and determining the time sequence allowance sum of the time sequence allowance of the front N-level connection path and the time sequence allowance sum of the time sequence allowance of the rear N-level connection path; wherein N is a positive integer;

The judging module is used for judging whether the time sequence allowance sum is not smaller than the time sequence violation value; if yes, triggering a first execution module; if not, triggering a second execution module;

The first execution module is configured to borrow, according to a preset borrowing proportion, a timing sequence allowance of a front N-stage connection path and a timing sequence allowance of a rear N-stage connection path to the critical path, so as to correct the timing sequence of the critical path;

the second execution module is configured to borrow all the timing sequence allowance of the first N-stage connection path and the timing sequence allowance of the second N-stage connection path to the critical path, determine the remaining timing sequence violation value, set N to N plus 1, and trigger the acquisition module.

In order to solve the above technical problem, the present invention further provides a timing adjustment apparatus, including:

a memory for storing a computer program;

And the processor is used for realizing the steps of the time sequence adjustment method when executing the computer program.

To solve the above technical problem, the present invention further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the timing adjustment method described above.

The time sequence adjusting method provided by the invention is characterized in that the time sequence allowance of the connecting paths among all data triggers in the integrated circuit design is determined, and the time sequence violation value of the critical path is determined; acquiring the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path, and determining the time sequence allowance sum of the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path; wherein N is a positive integer; judging whether the time sequence allowance sum is not smaller than the time sequence violation value; if yes, borrowing the time sequence allowance of the front N-level connecting paths and the time sequence allowance of the rear N-level connecting paths to the critical paths according to a preset borrowing proportion so as to correct the time sequence of the critical paths; if not, the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path are all borrowed to the critical path, the rest time sequence violation value is determined, N is set to be N plus 1, and the step of obtaining the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path is returned. The invention has the beneficial effects that a useful deviation mode of bidirectional sequential continuous borrowing is provided, and the sequential allowance is borrowed from the front and rear paths when the sequential violations of the critical paths are corrected by simultaneously considering the sequential allowance of the front and rear paths of the critical paths, so that the convergence of the sequential is quickened. In addition, when the timing margin of the front-stage path and the rear-stage path is insufficient, the scheme can continuously borrow the timing margin of the front-stage path and the rear-stage path, so that the timing margin in the integrated circuit design is fully utilized, the iteration time and the stronger dependence of rear-end staff on EDA tools are reduced, and the timing convergence efficiency is greatly improved.

In addition, the invention also provides a time sequence adjusting device, equipment and medium, and the effects are the same as the above.

Drawings

For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.

FIG. 1 is a schematic diagram of a register timing diagram before a useful bias process according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a register timing sequence after the useful deviation processing according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a connection path of a data flip-flop in an integrated circuit design according to an embodiment of the present invention;

FIG. 4 is a flowchart of a timing adjustment method according to an embodiment of the present invention;

FIG. 5 is a flowchart of a timing adjustment apparatus according to an embodiment of the present invention;

fig. 6 is a schematic diagram of a timing adjustment apparatus according to an embodiment of the present invention.

Wherein 5 is a first register, 6 is a second register, 7 is a third register, and 8 is a data trigger.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.

The core of the invention is to provide a time sequence adjusting method, a device, equipment and a medium, so as to solve the problem that the time sequence of a critical path cannot be corrected due to insufficient borrowing of the time sequence allowance by the current useful deviation function.

In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.

For the current large-scale and high-frequency IC design, the situation that the timing cannot be converged often occurs, and the logic total delay of most critical paths is very large. Among the many timing optimization methods, the method of optimizing critical path timing using useful skew is a very efficient and relatively easy to implement method, and is often used in timing optimization. Useful skew is described below.

Bias (skew) is a basic concept of timing analysis. Since the path delays of the clocks to each register are different, resulting in different times when the signals arrive at the clock pins (clock pins), the time offset of the clock signals arriving at the different registers is referred to as skew.

Further, the types of skew are classified into a wide variety, and the skew may be classified into global skew (global skew) and local skew (local skew) according to clock domains and path relationships. global skew refers to: within the same clock domain, the maximum skew of any two paths (paths). It should be noted that whether or not the timing path (TIMING PATH) is the object of the global skew calculation. When Clock tree synthesis (Clock TREE SYNTHESIS, CTS), the electronic design automation (Electronic Design Automation, EDA) tool is more concerned with global skew, and in particular, the global skew will be reduced as much as possible. And local skew refers to: and in the same clock domain, the maximum skew of any two paths with logic association relation is provided. It should be noted that a logical skew must be calculated for a path that has a logical relationship, that is, the path is specifically a timing path. skew is an important parameter that measures the performance of a clock tree, and the purpose of conventional CTS is to reduce skew. Generally, the skew will deteriorate the timing results, but if properly used, the skew can also serve as a repair timing, and this more specific skew is useful skew.

FIG. 1 is a schematic diagram of a register timing before a useful bias process according to an embodiment of the present invention. FIG. 2 is a schematic diagram of a register timing sequence after the useful deviation processing according to an embodiment of the present invention. As shown in fig. 1, with a clock period of 4ns, it can be seen that there is a timing violation (slot=t3+t2-4 ns= -1 ns) in the path between the second register 6 and the third register 7. While the first 1 stage path has a 2ns timing margin (slot=t2+t-T1-2 ns=2 ns) for the path between the first register 5 and the second register 6. Therefore, the clock delay (clock latency) of the second register 6 can be shortened from 2ns to 1ns, i.e. useful skew is used to borrow 1ns from the first 1 stage path of the third register 7 with a timing margin, as shown in fig. 2, so that both paths meet the timing requirement.

Currently, optimized timing by useful skew has been integrated into EDA tools, often requiring only commands to use the tool to turn on useful skew functions. In a practical project, the timing of design can be optimized using the useful skew functions of the EDA tool itself. However useful skew optimisation has the following problems: some critical paths have timing sequence allowance in front of and behind 1 level of paths, but when the timing sequence allowance of the front and behind 1 level of paths cannot correct the timing sequence violation of the critical paths, the critical paths are difficult to borrow from the front and behind level simultaneously; some critical paths only borrow a part of timing sequence allowance, a large amount of timing sequence allowance still exists, and timing sequence violations are caused by insufficient borrowing; some critical paths have no timing margin for the front and rear 1-stage paths, while the front and rear multi-stage paths have timing margins that are difficult to use. In view of the above, the present invention provides a timing adjustment method, which aims to solve the problem that the timing of a critical path cannot be corrected due to insufficient borrowing of a timing margin by a current useful deviation function.

It should be noted that the method provided by the present solution is applied to an integrated circuit design composed of a plurality of Data Flip-flops (DFFs). The data flip-flop is a data trigger type register, i.e. a D flip-flop. Fig. 3 is a schematic diagram of a connection path of a data flip-flop in an integrated circuit design according to an embodiment of the present invention. As shown in fig. 3, in the integrated circuit design, the data flip-flops 8 are sequentially connected through the input terminal of each data flip-flop 8 and the output terminal of each data flip-flop 8, and these paths are connection paths between the data flip-flops 8.

Fig. 4 is a flowchart of a timing adjustment method according to an embodiment of the present invention. As shown in fig. 4, the method includes:

S10: and determining the time sequence allowance of a connecting path between all data triggers in the integrated circuit design, and determining the time sequence violation value of a critical path.

Specifically, first, the timing margin (slot) of the connection path between the data flip-flops in the integrated circuit design is determined, and the timing violation value of the critical path is determined. When the timing margin of the connection path is negative, the connection path is considered to be a critical path, and the absolute value of the corresponding timing margin S is the timing violation value |s|. The specific process of determining the timing margin of the connection paths between the data flip-flops in the integrated circuit design is not limited in this embodiment, and depends on the specific implementation.

S11: and acquiring the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path, and determining the time sequence allowance sum of the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path.

Wherein N is a positive integer.

After determining the critical path in which the timing violation occurs, the timing margin SN _pre of the front N-stage connection path and the timing margin SN _next of the rear N-stage connection path of the critical path are acquired, and the timing margins SN _pre of the front N-stage connection path and the timing margin SN _next of the rear N-stage connection path are both determined, together with SN _sum.

Note that N is a positive integer. That is, after determining the critical path in which the timing violation occurs, the timing margin S1 _pre of the first 1-stage connection path and the timing margin S1 _next of the last 1-stage connection path of the critical path, that is, borrowing the timing margin from the first and last 1-stage paths of the critical path, may be acquired; the timing margin S2 _pre of the first 2-stage connection path and the timing margin S2 _next of the last 2-stage connection path of the critical path, that is, the timing margin borrowed from the first and last 2-stage paths of the critical path, may also be acquired. In this embodiment, the value of N is not limited, and depends on the specific implementation.

S12: judging whether the time sequence allowance sum is not smaller than the time sequence violation value; if yes, go to step S13; if not, the process proceeds to step S14.

S13: and borrowing the time sequence allowance of the front N-level connecting paths and the time sequence allowance of the rear N-level connecting paths to the critical paths according to a preset borrowing proportion so as to correct the time sequence of the critical paths.

S14: and borrowing all the time sequence allowance of the front N-level connecting paths and the time sequence allowance of the rear N-level connecting paths to the critical paths, determining the rest time sequence violation values, setting N as N plus 1, and returning to the step S11.

Further, it is determined whether the obtained timing margin and SN _sum are not smaller than the timing violation value |s| of the critical path. If the confirmed time sequence allowance and the SN _sum are not smaller than the time sequence violation value |S| of the critical path, the time sequence violation of the critical path can be repaired by borrowing the time sequence allowance of the N-stage connecting paths before and after; therefore, according to the preset borrowing ratio, the timing margin SN _pre of the front N-stage connection path and the timing margin SN _next of the rear N-stage connection path are borrowed to the critical path to correct the timing of the critical path.

If the confirmed time sequence allowance and the SN _sum are smaller than the time sequence violation value |S| of the critical path, the time sequence allowance of the N-level connecting path before and after borrowing is considered to be insufficient for repairing the time sequence violation of the critical path; therefore, the timing margin SN _pre of the front N-stage connection path and the timing margin SN _next of the rear N-stage connection path are all borrowed to the critical path. After the timing violations of the critical path are partially corrected, a partial timing violation value |S| remains. In order to further complete the correction, the remaining timing violation value |s| needs to be determined, N is set to be N plus 1, and the process returns to step S11, so that the timing margin sn+1 _pre of the first n+1 stage connection path and the timing margin sn+1 _next of the last n+1 stage connection path of the critical path are borrowed until the correction of the timing violation of the critical path is completed.

It should be noted that the preset borrowing proportion is not limited in this embodiment. In addition, the specific process of borrowing the timing margin SN _pre of the front N-stage connection path and the timing margin SN _next of the rear N-stage connection path to the critical path is not limited in this embodiment, and depends on the specific implementation.

In this embodiment, the timing violation value of the critical path is determined by determining the timing margin of the connection path between the data flip-flops in the integrated circuit design; acquiring the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path, and determining the time sequence allowance sum of the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path; wherein N is a positive integer; judging whether the time sequence allowance sum is not smaller than the time sequence violation value; if yes, borrowing the time sequence allowance of the front N-level connecting paths and the time sequence allowance of the rear N-level connecting paths to the critical paths according to a preset borrowing proportion so as to correct the time sequence of the critical paths; if not, the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path are all borrowed to the critical path, the rest time sequence violation value is determined, N is set to be N plus 1, and the step of obtaining the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path is returned. Therefore, the scheme provides a useful deviation mode of bidirectional sequential continuous borrowing, and the sequential allowance is borrowed from the front and rear paths when the sequential violations of the critical paths are corrected by considering the sequential allowance of the front and rear paths of the critical paths at the same time, so that the convergence of the sequential is quickened. In addition, when the timing margin of the front-stage path and the rear-stage path is insufficient, the scheme can continuously borrow the timing margin of the front-stage path and the rear-stage path, so that the timing margin in the integrated circuit design is fully utilized, the iteration time and the stronger dependence of rear-end staff on EDA tools are reduced, and the timing convergence efficiency is greatly improved.

Based on the above embodiments, in some embodiments, determining the timing margin of the connection paths between the data flip-flops in the integrated circuit design and determining the timing violation value of the critical path includes:

s101: the clock period of the integrated circuit design is obtained, and the clock delay of each data flip-flop is obtained.

Wherein the clock delay characterizes a timing value of a clock definition point to a clock pin of a corresponding data flip-flop.

S102: and acquiring a time sequence value of a connection path corresponding to each data trigger.

S103: the clock delays and clock periods of the data flip-flops are summed, respectively, to obtain a plurality of first timing amounts.

S104: and respectively summing the time sequence value of the connecting path corresponding to each data trigger with the clock delay of the previous data trigger corresponding to each data trigger to obtain a plurality of second time sequence amounts.

S105: and respectively obtaining the difference value of each first time sequence quantity and the corresponding second time sequence quantity to obtain the time sequence allowance of the connecting path between each data trigger.

S106: and taking the connection path with the negative timing margin as a critical path, and taking the absolute value of the corresponding timing margin as the timing violation value of the critical path.

In order to obtain the timing margin of each connection path, first, the clock period of the integrated circuit design is obtained, and the clock delay of each data flip-flop is obtained. It will be appreciated that the clock delay characterizes the timing value of the clock definition point to the clock pin of the corresponding data flip-flop.

Further acquiring time sequence values of the connecting paths corresponding to the data triggers, and respectively summing clock delays and clock periods of the data triggers to obtain a plurality of first time sequence amounts. Taking fig. 1 as an example, the connection path between the second register 6 and the third register 7 is the connection path corresponding to the third register 7, and the time sequence value corresponding to the connection path is 4ns. The clock delay of the third register 7 is t3=1ns, and the clock period is 4ns, and the first timing sequence corresponding to the third register 7 is 1ns+4ns=5ns.

And respectively summing the time sequence value of the connecting path corresponding to each data trigger with the clock delay of the previous data trigger corresponding to each data trigger to obtain a plurality of second time sequence amounts. Taking fig. 1 as an example, the timing value of the connection path corresponding to the third register 7 is 4ns; the previous register corresponding to the third register 7 is the second register 6, the clock delay of the second register 6 is t2=2ns, and the second timing sequence corresponding to the third register 7 is 2ns+4ns=6ns.

And finally, respectively obtaining the difference value of each first time sequence amount and the corresponding second time sequence amount to obtain the time sequence allowance of the connecting path between each data trigger. And taking the connection path with the negative timing margin as a critical path, and taking the absolute value of the corresponding timing margin as the timing violation value of the critical path. Taking fig. 1 as an example, a difference between the first timing amount and the second timing amount of the third register 7 is obtained, that is, 5ns-6 ns= -1ns, so that the timing margin of the third register 7 is-1 ns. Since the timing margin of the third register 7 is smaller than 0, the connection path corresponding to the third register 7 is the critical path, and the absolute value 1ns of the timing margin of the third register 7 is the timing violation value of the critical path.

Therefore, the acquisition of the time sequence allowance of the connecting paths among the data triggers and the determination of the time sequence violation values of the critical paths are realized, so that the subsequent time sequence borrowing of the critical paths is facilitated.

In order to improve the timing borrowing efficiency, in some embodiments, before determining whether the timing margin sum is not smaller than the timing violation value, after determining the timing margin sum of the timing margin of the front N-stage connection path and the timing margin sum of the rear N-stage connection path, the method further includes:

s15: judging whether the sum of the time sequence allowance is not less than 0; if yes, go to step S12; if not, the process proceeds to step S16.

S16: setting N to N plus 1, returning to step S11.

In implementations, before determining whether the timing margin and SN _sum are not less than the timing violation value |s| it may first be determined whether the timing margin and SN _sum are not less than 0. If the confirmed time sequence allowance and the SN _sum are not less than 0, and the SN _sum is not less than 0, a certain time sequence allowance exists in the front N-level connecting path and the rear N-level connecting path, and the method can be used for subsequent time sequence borrowing, so that the step of judging whether the time sequence allowance and the time sequence violation value are not less is carried out. If the confirmed timing margin and SN _sum are smaller than 0 and SN _sum is smaller than 0, the front N-level connection path and the rear N-level connection path are considered to have no timing margin and cannot be used for subsequent timing borrowing, so that N is set to be N plus 1, and the step of obtaining the timing margin of the front N-level connection path and the timing margin of the rear N-level connection path of the critical path is returned to, so that the timing margins of the front n+1 connection path and the rear n+1 connection path are obtained for subsequent timing borrowing.

In this embodiment, by determining whether the sum of the timing margins is not less than 0, it is determined whether the timing margins of the connection paths of the preceding and following N stages can be used for subsequent timing borrowing, thereby improving the timing borrowing efficiency.

On the basis of the above-described embodiments, in some embodiments, before determining whether the timing margin sum is not less than the timing violation value, after determining the timing margin sum of the timing margin of the front N-stage connection path and the timing margin sum of the timing margin of the rear N-stage connection path, further comprising:

s17: judging whether the time sequence allowance sum is not smaller than the time sequence reservation total amount; the total time sequence reservation amount is the sum of the time sequence reservation amount of the front N-stage connecting paths and the time sequence reservation amount of the rear N-stage connecting paths; if yes, go to step S12; if not, the process proceeds to step S18.

S18: setting N to N plus 1, and returning to the step S11.

In practice, according to project experience, it is preferable that a certain time sequence retention t is reserved for the connection path between the data triggers, that is, the time sequence retention t cannot be borrowed by the critical path, so as to ensure the time sequence calculation by the subsequent accurate and strict signature tool. In addition, in the integrated circuit design, the timing retention t of the connection paths between the data flip-flops is generally the same, so the timing retention t of the connection path of the first N stages is equal to the timing retention t of the connection path of the last N stages, and the corresponding total amount of timing retention is 2t.

Therefore, in the present embodiment, before judging whether or not the timing margin and SN _sum are not smaller than the timing violation value |s| it is judged whether or not the timing margin and SN _sum are not smaller than the timing reservation total amount 2t. If the confirmed time sequence allowance and the SN _sum are not less than the total time sequence reservation amount 2t, and the SN _sum is more than or equal to 2t, the time sequence allowance existing in the front N-level connecting path and the rear N-level connecting path is considered to not only meet the time sequence reservation, but also be used for the subsequent time sequence borrowing, so that the step of judging whether the time sequence allowance and the time sequence violation value are not less is entered;

If the confirmed time sequence allowance and the SN _sum are smaller than the total time sequence reservation amount 2t and the SN _sum is smaller than 2t, the time sequence allowance existing in the front N-level connection path and the rear N-level connection path cannot meet the time sequence reservation, and cannot be used for subsequent time sequence borrowing. Therefore, N is set to be N plus1, and the process returns to the step of acquiring the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path, so that the time sequence allowance of the front and rear N+1 connecting paths is acquired for subsequent time sequence borrowing.

It should be noted that the value of the time-series reserved t is not limited in this embodiment, and depends on the specific implementation.

In this embodiment, by determining whether the sum of the timing margins is not smaller than the total reserved timing, it is determined whether the timing margins of the connection paths of the preceding and subsequent N stages can be used for subsequent timing borrowing, thereby improving the timing borrowing efficiency.

Based on the above embodiments, in some embodiments, determining whether the timing margin sum is not less than the timing violation value includes:

S121: judging whether the sum of the time sequence allowance is not smaller than the sum of the time sequence violation value and the total time sequence reservation; if yes, step S13; if not, the process proceeds to step S14.

Since a certain time sequence retention t is preferably reserved in the connection path between the data triggers, when the time sequence is borrowed from the critical path, the time sequence retention t and the time sequence violation value |s| need to be considered at the same time, which is specifically as follows:

It is determined whether or not the timing margin sum SN _sum is not smaller than the sum of the timing violation value |s| and the timing reservation total amount 2 t. If the timing margin and SN _sum are not less than the sum of the timing violation value |s| and the total timing reservation amount 2t, i.e., SN _sum is not less than |s|+2t, it is indicated that the timing margin existing in the front N-stage connection path and the rear N-stage connection path simultaneously satisfies the timing reservation and the timing borrowing, and the step of borrowing the timing margin of the front N-stage connection path and the timing margin of the rear N-stage connection path to the critical path according to the preset borrowing ratio may be entered.

If the timing margin sum SN _sum is smaller than the sum of the timing violation value |s| and the total amount of timing reservations 2t, i.e., SN _sum < |s|+2t, it is indicated that the timing margin existing in the front N-stage connection path and the rear N-stage connection path satisfies the timing reservations, but the remaining timing margin does not satisfy the timing borrowing. Therefore, the step of borrowing the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path to the key path and determining the residual time sequence violation value is carried out, so that the time sequence allowance of the front and rear N+1 connecting paths is obtained for the subsequent time sequence borrowing.

In addition, considering the timing reservation of the connection path, in the implementation, if the timing margin sum SN _sum is smaller than the sum of the timing violation value |s| and the timing reservation total amount 2t, i.e., SN _sum < |s|+2t, it is also possible to choose not to enter step S14, i.e., not to borrow the timing margin SN _pre of the front N-stage connection path and the timing margin SN _next of the rear N-stage connection path all to the critical path, but to borrow the same target timing amount from the timing margin SN _pre of the front N-stage connection path and the timing margin SN _next of the rear N-stage connection path, respectively, to the critical path. It should be noted that, after the target timing sequence quantity is borrowed to the critical path, the remaining timing sequence margins of the timing sequence margin SN _pre of the front N-stage connection path and the remaining timing sequence margin SN _next of the rear N-stage connection path are not smaller than the respective timing sequence reserved quantity t, so that the subsequent signoff timing sequence is ensured to pass through, and the reliability of timing sequence borrowing is improved.

In view of the bidirectional equalization of the timing borrowing, when it is confirmed that the timing margin and SN _sum are not less than the sum of the timing violation value |s| and the timing reservation total amount 2t, based on the above-described embodiments, in some embodiments, the timing margin of the front N-stage connection path and the timing margin of the rear N-stage connection path are borrowed to the critical path according to the preset borrowing ratio, including:

S131: and determining the quotient of the timing violation value and the timing allowance to obtain a preset borrowing proportion.

S132: and determining the difference value between the time sequence allowance of the front N-stage connecting path and the corresponding time sequence reservation amount to obtain the borrowable time sequence allowance of the front N-stage connecting path.

S133: and determining the difference value between the time sequence allowance of the rear N-stage connecting path and the corresponding time sequence reservation amount to obtain the borrowable time sequence allowance of the rear N-stage connecting path.

S134: and determining the product of the preset borrowing proportion and the borrowable time sequence allowance of the previous N-stage connecting paths to obtain the borrowed time sequence quantity of the previous N-stage connecting paths.

S135: and determining the product of the preset borrowing proportion and the borrowable time sequence allowance of the rear N-level connecting paths to obtain the borrowed time sequence quantity of the rear N-level connecting paths.

S136: borrowing the borrowed time sequence quantity of the front N-level connecting paths and the borrowed time sequence quantity of the rear N-level connecting paths to the key paths.

Specifically, first, the quotient of the timing violation value |S| and both the timing margin and SN _sum is determined to obtain a preset borrowing proportionI.e. theFurther, a difference between the timing margin SN _pre of the previous N-stage connection path and the corresponding timing reserve t is determined to obtain a borrowable timing margin (SN _pre -t) of the previous N-stage connection path. And determining the difference between the time sequence allowance SN _next of the rear N-level connecting path and the corresponding time sequence reservation t to obtain the borrowable time sequence allowance (SN _next -t) of the rear N-level connecting path.

Further, a preset borrowing proportion is determinedProduct of borrowable timing margin (SN _pre -t) with previous N-stage connection path to obtain borrowed timing quantity of previous N-stage connection pathDetermining a preset borrowing proportionProduct of borrowable timing margin (SN _next -t) with the next N-level connection path to obtain borrowed timing quantity of the next N-level connection path

Finally, borrowing time sequence quantity of the previous N-stage connection pathsBorrowing time sequence quantity borrowing of connection path of last N stagesAnd the timing violations of the critical paths are corrected, the timing margins of the N-stage connecting paths before and after the critical paths are not excessively consumed, and the bidirectional equalization of the timing borrowing is ensured.

Based on the above embodiments, in some embodiments, borrowing the borrowed timing quantity of the front N-level connection path and the borrowed timing quantity of the rear N-level connection path to the critical path includes:

S137: and determining a first clock delay adjustment value of the data trigger corresponding to the previous N-stage connecting path according to the borrowing time sequence quantity of the previous N-stage connecting path.

S138: and determining a second clock delay adjustment value of the data trigger corresponding to the rear N-stage connecting path according to the borrowed time sequence quantity of the rear N-stage connecting path.

S139: and adjusting the clock delay of the data trigger corresponding to the front N-level connecting path according to the first clock delay adjustment value, and adjusting the clock delay of the data trigger corresponding to the rear N-level connecting path according to the second clock delay adjustment value so as to borrow the borrowed time sequence quantity of the front N-level connecting path and the borrowed time sequence quantity of the rear N-level connecting path to the critical path.

The timing borrowing of critical paths is described in the above embodiments. In order to complete the timing correction of the critical path, the first clock delay adjustment value of the data trigger corresponding to the previous N-stage connection path is specifically determined according to the borrowed timing quantity of the previous N-stage connection path. And determining a second clock delay adjustment value of the data trigger corresponding to the rear N-stage connecting path according to the borrowed time sequence quantity of the rear N-stage connecting path. Finally, the clock delay of the data trigger corresponding to the previous N-stage connection path is adjusted according to the first clock delay adjustment value, and the clock delay of the data trigger corresponding to the next N-stage connection path is adjusted according to the second clock delay adjustment value. Thereby borrowing the borrowed timing quantity of the front N-level connection path and the borrowed timing quantity of the rear N-level connection path to the critical path.

On the basis of the foregoing embodiments, in some embodiments, after setting N to N plus 1, the method further includes:

s19: and monitoring the value of N, and judging whether N is larger than a threshold value. If yes, the process proceeds to step S20.

S20: the timing borrowing process for the current critical path is stopped.

S21: and outputting an error prompt and generating a time sequence borrowing log.

In specific implementation, the value of N is monitored in real time, and whether N is larger than a threshold value is judged. If N is not greater than the threshold, proceed to step S11. If N is greater than the threshold, it is considered that the timing margin of the multi-level connection path before and after the critical path cannot meet the correction of the critical path timing violation, whether the EDA tool fails or the integrated circuit design is unreasonable should be considered. Thus, the timing borrowing process for the current critical path is stopped. And outputting an error prompt, thereby prompting the staff that the current time sequence borrowing process possibly has a problem, leading the staff to check and generating a time sequence borrowing log.

It should be noted that, in the timing borrowing log, the timing allowance borrowed from the critical path by each stage of connection path should be explicitly recorded, so that the staff can clearly and accurately know the timing borrowing process.

In the above embodiments, the detailed description is given to the timing adjustment method, and the present invention further provides a corresponding embodiment of the timing adjustment device.

Fig. 5 is a flowchart of a timing adjustment device according to an embodiment of the present invention. As shown in fig. 5, the apparatus includes:

The determining module 10 is configured to determine a timing margin of a connection path between data flip-flops in an integrated circuit design, and determine a timing violation value of a critical path.

An obtaining module 11, configured to obtain a timing margin of a front N-stage connection path and a timing margin of a rear N-stage connection path of the critical path, and determine a timing margin sum of the timing margin of the front N-stage connection path and the timing margin of the rear N-stage connection path; wherein N is a positive integer.

A judging module 12, configured to judge whether the timing margin sum is not less than the timing violation value; if yes, triggering the first execution module 13; if not, the second execution module 14 is triggered.

The first execution module 13 is configured to borrow the timing margin of the front N-level connection path and the timing margin of the rear N-level connection path to the critical path according to a preset borrowing ratio, so as to correct the timing of the critical path.

The second execution module 14 is configured to borrow the timing margin of the first N-stage connection path and the timing margin of the second N-stage connection path to the critical path, determine the remaining timing violation value, set N to N plus 1, and trigger the acquisition module.

In some embodiments, the determining module 10 includes:

The first acquisition submodule is used for acquiring clock cycles of the integrated circuit design and clock delay of each data trigger; the clock delay represents the time sequence value from the clock definition point to the clock pin of the corresponding data trigger;

The second acquisition sub-module is used for acquiring the time sequence value of the connecting path corresponding to each data trigger;

the first calculation sub-module is used for respectively summing the clock delay and the clock period of each data trigger so as to obtain a plurality of first time sequence amounts;

The second calculation sub-module is used for respectively summing the time sequence value of the connecting path corresponding to each data trigger with the clock delay of the previous data trigger corresponding to each data trigger so as to obtain a plurality of second time sequence amounts;

a third calculation sub-module, configured to obtain a difference value between each first timing sequence amount and a corresponding second timing sequence amount, so as to obtain a timing sequence allowance of a connection path between each data trigger;

The first determining submodule is used for taking a connecting path with a negative timing margin as a critical path and taking an absolute value of a corresponding timing margin as a timing violation value of the critical path.

In some embodiments, further comprising:

A first judging sub-module for judging whether the sum of the time sequence allowance is not less than 0; if the sum of the confirmed time sequence allowance is not less than 0, triggering the judging module 12; if the sum of the confirmed time sequence margins is less than 0, setting N as N plus 1, and returning to the trigger acquisition module 11.

In some embodiments, further comprising:

The second judging submodule is used for judging whether the time sequence allowance sum is not smaller than the time sequence reservation total amount; the total time sequence reservation amount is the sum of the time sequence reservation amount of the front N-stage connecting paths and the time sequence reservation amount of the rear N-stage connecting paths; if the sum of the confirmed time sequence allowance is not smaller than the time sequence reservation total, triggering the judging module 12; if the sum of the confirmed time sequence allowance is smaller than the total time sequence reservation amount, setting N as N plus 1, and returning to the trigger acquisition module 11.

In some embodiments, the determining module 12 includes:

a third judging sub-module for judging whether the sum of the time sequence allowance is not less than the sum of the time sequence violation value and the total time sequence reservation; if yes, triggering the first execution module 13; if not, the second execution module 14 is triggered.

Correspondingly, the first execution module 13 comprises:

The second determining submodule is used for determining a time sequence violation value, a time sequence allowance and a quotient value of the time sequence violation value and the time sequence allowance to obtain a preset borrowing proportion;

A third determining submodule, configured to determine a difference between a timing margin of the previous N-stage connection path and a corresponding timing reserve, so as to obtain a borrowable timing margin of the previous N-stage connection path;

a fourth determining submodule, configured to determine a difference between a timing margin of the subsequent N-level connection path and a corresponding timing reserve, so as to obtain a borrowable timing margin of the subsequent N-level connection path;

a fifth determining submodule, configured to determine a product of a preset borrowing proportion and a borrowable timing margin of a previous N-stage connection path, so as to obtain a borrowed timing quantity of the previous N-stage connection path;

a sixth determining submodule, configured to determine a product of a preset borrowing proportion and a borrowable timing margin of the N-stage connection path to obtain a borrowed timing quantity of the N-stage connection path;

And the first execution sub-module is used for borrowing the borrowing time sequence quantity of the front N-level connecting paths and the borrowing time sequence quantity of the rear N-level connecting paths to the key paths.

In some embodiments, the first execution sub-module includes:

a seventh determining submodule, configured to determine a first clock delay adjustment value of a data trigger corresponding to a previous N-stage connection path according to the borrowed time sequence amount of the previous N-stage connection path;

an eighth determining submodule, configured to determine a second clock delay adjustment value of the data trigger corresponding to the last N-stage connection path according to the borrowed time sequence amount of the last N-stage connection path;

And the adjusting sub-module is used for adjusting the clock delay of the data trigger corresponding to the front N-level connecting path according to the first clock delay adjusting value and adjusting the clock delay of the data trigger corresponding to the rear N-level connecting path according to the second clock delay adjusting value so as to borrow the borrowed time sequence quantity of the front N-level connecting path and the borrowed time sequence quantity of the rear N-level connecting path to the critical path.

In some embodiments, further comprising:

The monitoring submodule is used for monitoring the value of N and judging whether N is larger than a threshold value or not; if the N is greater than the threshold value, triggering a stopping sub-module;

a stopping sub-module, configured to stop a timing borrowing process of the current forward critical path;

and the output generation sub-module is used for outputting error prompt and generating a time sequence borrowing log.

In this embodiment, the timing adjustment device includes a determining module, an acquiring module, a judging module, a first executing module, and a second executing module. The timing adjustment device is capable of implementing all the steps of the timing adjustment method described above when running. Determining the time sequence allowance of a connecting path among all data triggers in the integrated circuit design, and determining the time sequence violation value of a critical path; acquiring the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path, and determining the time sequence allowance sum of the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path; wherein N is a positive integer; judging whether the time sequence allowance sum is not smaller than the time sequence violation value; if yes, borrowing the time sequence allowance of the front N-level connecting paths and the time sequence allowance of the rear N-level connecting paths to the critical paths according to a preset borrowing proportion so as to correct the time sequence of the critical paths; if not, the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path are all borrowed to the critical path, the rest time sequence violation value is determined, N is set to be N plus 1, and the step of obtaining the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path is returned. Therefore, the scheme provides a useful deviation mode of bidirectional sequential continuous borrowing, and the sequential allowance is borrowed from the front and rear paths when the sequential violations of the critical paths are corrected by considering the sequential allowance of the front and rear paths of the critical paths at the same time, so that the convergence of the sequential is quickened. In addition, when the timing margin of the front-stage path and the rear-stage path is insufficient, the scheme can continuously borrow the timing margin of the front-stage path and the rear-stage path, so that the timing margin in the integrated circuit design is fully utilized, the iteration time and the stronger dependence of rear-end staff on EDA tools are reduced, and the timing convergence efficiency is greatly improved.

Fig. 6 is a schematic diagram of a timing adjustment apparatus according to an embodiment of the present invention. As shown in fig. 6, the timing adjustment apparatus includes:

A memory 20 for storing a computer program.

A processor 21 for implementing the steps of the timing adjustment method as mentioned in the above embodiments when executing a computer program.

The timing adjustment device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.

Processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The Processor 21 may be implemented in at least one hardware form of a digital signal Processor (DIGITAL SIGNAL Processor, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 21 may also include a main processor and a coprocessor, the main processor being a processor for processing data in an awake state, also referred to as a central processor (Central Processing Unit, CPU); a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 21 may integrate a graphics processor (Graphics Processing Unit, GPU) for rendering and drawing of content required to be displayed by the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor for processing computing operations related to machine learning.

Memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing a computer program 201, which, when loaded and executed by the processor 21, is capable of implementing the relevant steps of the timing adjustment method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may further include an operating system 202, data 203, and the like, where the storage manner may be transient storage or permanent storage. Operating system 202 may include Windows, unix, linux, among other things. The data 203 may include, but is not limited to, data related to a timing adjustment method.

In some embodiments, the timing adjustment device may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.

Those skilled in the art will appreciate that the structure shown in fig. 6 does not constitute a limitation of the timing adjustment device and may include more or less components than those illustrated.

In this embodiment, the timing adjustment apparatus includes a memory and a processor. The memory is used for storing a computer program. The processor is adapted to implement the steps of the timing adjustment method as mentioned in the above embodiments when executing the computer program. Determining the time sequence allowance of a connecting path among all data triggers in the integrated circuit design, and determining the time sequence violation value of a critical path; acquiring the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path, and determining the time sequence allowance sum of the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path; wherein N is a positive integer; judging whether the time sequence allowance sum is not smaller than the time sequence violation value; if yes, borrowing the time sequence allowance of the front N-level connecting paths and the time sequence allowance of the rear N-level connecting paths to the critical paths according to a preset borrowing proportion so as to correct the time sequence of the critical paths; if not, the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path are all borrowed to the critical path, the rest time sequence violation value is determined, N is set to be N plus 1, and the step of obtaining the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path is returned. Therefore, the scheme provides a useful deviation mode of bidirectional sequential continuous borrowing, and the sequential allowance is borrowed from the front and rear paths when the sequential violations of the critical paths are corrected by considering the sequential allowance of the front and rear paths of the critical paths at the same time, so that the convergence of the sequential is quickened. In addition, when the timing margin of the front-stage path and the rear-stage path is insufficient, the scheme can continuously borrow the timing margin of the front-stage path and the rear-stage path, so that the timing margin in the integrated circuit design is fully utilized, the iteration time and the stronger dependence of rear-end staff on EDA tools are reduced, and the timing convergence efficiency is greatly improved.

Finally, the invention also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.

It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

In this embodiment, a computer program is stored on a computer readable storage medium, and when the computer program is executed by a processor, the steps described in the above method embodiments are implemented. Determining the time sequence allowance of a connecting path among all data triggers in the integrated circuit design, and determining the time sequence violation value of a critical path; acquiring the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path, and determining the time sequence allowance sum of the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path; wherein N is a positive integer; judging whether the time sequence allowance sum is not smaller than the time sequence violation value; if yes, borrowing the time sequence allowance of the front N-level connecting paths and the time sequence allowance of the rear N-level connecting paths to the critical paths according to a preset borrowing proportion so as to correct the time sequence of the critical paths; if not, the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path are all borrowed to the critical path, the rest time sequence violation value is determined, N is set to be N plus 1, and the step of obtaining the time sequence allowance of the front N-level connecting path and the time sequence allowance of the rear N-level connecting path of the critical path is returned. Therefore, the scheme provides a useful deviation mode of bidirectional sequential continuous borrowing, and the sequential allowance is borrowed from the front and rear paths when the sequential violations of the critical paths are corrected by considering the sequential allowance of the front and rear paths of the critical paths at the same time, so that the convergence of the sequential is quickened. In addition, when the timing margin of the front-stage path and the rear-stage path is insufficient, the scheme can continuously borrow the timing margin of the front-stage path and the rear-stage path, so that the timing margin in the integrated circuit design is fully utilized, the iteration time and the stronger dependence of rear-end staff on EDA tools are reduced, and the timing convergence efficiency is greatly improved.

The method, the device, the equipment and the medium for adjusting the time sequence provided by the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that the present invention may be modified and practiced without departing from the spirit of the present invention.

It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

Claims

1. A timing adjustment method, comprising:

2. The timing adjustment method of claim 1, wherein determining the timing margin of the connection paths between the data flip-flops in the integrated circuit design and determining the timing violation value of the critical path comprises:

3. The timing adjustment method according to claim 1, characterized by further comprising, before said determining whether the timing margin sum is not less than the timing violation value, after said determining the timing margin sum of the timing margin of the front N-stage connection path and the timing margin sum of the rear N-stage connection path:

Judging whether the sum of the time sequence allowance is not less than 0;

4. The timing adjustment method according to claim 1, characterized by further comprising, before said determining whether the timing margin sum is not less than the timing violation value, after said determining the timing margin sum of the timing margin of the front N-stage connection path and the timing margin sum of the rear N-stage connection path:

5. The timing adjustment method of claim 4, wherein the determining whether the timing margin sum is not less than the timing violation value comprises:

6. The timing adjustment method according to claim 5, wherein borrowing the borrowed timing amount of the front N-level connection path and the borrowed timing amount of the rear N-level connection path to the critical path includes:

7. The timing adjustment method according to any one of claims 1 to 6, characterized by further comprising, after setting N to N plus 1:

And outputting an error prompt and generating a time sequence borrowing log.

8. A timing adjustment device, comprising:

9. A timing adjustment apparatus, characterized by comprising:

a memory for storing a computer program;

a processor for implementing the steps of the timing adjustment method according to any one of claims 1 to 7 when executing the computer program.

10. A computer-readable storage medium, on which a computer program is stored, which, when being executed by a processor, implements the steps of the timing adjustment method according to any one of claims 1 to 7.