CN118251583A

CN118251583A - High-sensitivity thermoelectric-based infrared detector with high CMOS (complementary metal oxide semiconductor) integration level

Info

Publication number: CN118251583A
Application number: CN202280075300.9A
Authority: CN
Inventors: 洪婉嘉; 彼得·科普尼奇
Original assignee: Meridian Innovation Pte Ltd
Current assignee: Meridian Innovation Pte Ltd
Priority date: 2021-11-16
Filing date: 2022-11-16
Publication date: 2024-06-25
Also published as: WO2023091084A1

Abstract

A CMOS-MEMS integrated device and method for forming such a device are disclosed. The integrated device includes a dual release MEMS infrared sensor. The dual release MEMS sensor is a stand alone sensor over a lower sensor cavity that is etched into the substrate of the device. The freestanding MEMS sensor does not have a supporting dielectric film supporting the MEMS sensor, resulting in the MEMS sensor being suspended above the lower sensor cavity. The supporting dielectric is removed by a second release process. The second release process may also remove the protective dielectric layer over the MEMS sensor. MEMS sensors without protective dielectric layers enhance sensor sensitivity. In other cases, the stand-alone MEMS sensor may include an absorber located above it. The absorber enhances the sensor sensitivity.

Description

High-sensitivity thermoelectric-based infrared detector with high CMOS (complementary metal oxide semiconductor) integration level

Cross Reference to Related Applications

The present application claims the benefit of U.S. provisional application Ser. No. 63/279,682, filed 11/16 of 2021. The present application is also a continuation of the section of U.S. patent application Ser. No. 17/612,200 filed 11/17 of 2021; part of the continuation of U.S. patent application Ser. No. 17/440,784 filed 9/2021; part of the continuation of U.S. patent application Ser. No. 17/440,175 filed on 9/16 of 2021; U.S. patent application Ser. No. 17/439,797, filed on 9 and 15 of 2021, is a partial continuation of U.S. patent application Ser. No. 17/156,639, filed on 25 of 2021. The disclosures of the above-mentioned applications are incorporated herein by reference in their entirety for all purposes.

Technical Field

The present disclosure relates generally to monolithically integrated CMOS-MEMS devices. More particularly, the present disclosure relates to monolithically integrated CMOS-MEMS devices with high sensitivity MEMS sensors. The high sensitivity MEMS sensor is a stand-alone MEMS sensor, such as a stand-alone MEMS infrared sensor.

Background

The demand for uncooled infrared detectors continues to grow due to the increasing demand for numerous applications. These applications include air conditioning systems, cell phones, autopilot cars, internet of things (IoT), fire protection and traffic safety, to name a few.

Conventional uncooled infrared detectors have been implemented using microbolometers. However, microbolometers require mechanical components for calibration purposes. As one example, microbolometers require a mechanical shutter for offset correction. The mechanical components required for microbolometers add to the complexity of manufacturing. This complexity increases the cost. Furthermore, the need for mechanical parts for microbolometers makes it difficult to produce small or compact devices and is more susceptible to reliability problems.

The present disclosure relates to cost-effective and compact infrared detectors integrated with CMOS components with high sensitivity and response time.

Disclosure of Invention

Embodiments of the present disclosure generally relate to devices and methods of forming the same. In one embodiment, an apparatus is disclosed. The device includes a substrate having a Complementary Metal Oxide Semiconductor (CMOS) region and a microelectromechanical system (MEMS) region. The CMOS region includes a transistor region having a transistor. The MEMS region includes a lower sensor cavity and a separate sensor disposed above the lower sensor cavity. The independent sensor has no supporting dielectric between the sensor and the lower sensor cavity. The independent sensor improves response time and sensor sensitivity. A pre-metal dielectric layer having a pre-metal contact is disposed on the substrate over the CMOS region and the MEMS region. A back end of line (BEOL) dielectric is disposed on the pre-metal dielectric layer. The BEOL dielectric includes a plurality of inter-metal dielectric (IMD) layers, with metal levels and via levels disposed above the pre-metal dielectric. The metal level includes metal lines and the via level includes via contacts to interconnect components of the device via the pre-metal dielectric layer.

In another embodiment, a method of forming a device is disclosed. The method includes providing a substrate that is prepared with a Complementary Metal Oxide Semiconductor (CMOS) region and a microelectromechanical system (MEMS) region. The CMOS region is processed to form transistors of the first type and the second type in the first transistor region and the second transistor region. The MEMS region is processed to form a lower sensor cavity trench filled with a cavity trench filler. A sensor support dielectric layer is formed over the lower sensor cavity on top of the trench fill. The sensor is formed on the sensor support dielectric layer. A pre-metal dielectric layer is formed on the substrate with pre-metal contacts connected to the CMOS and MEMS components of the device. A back-end-of-line (BEOL) dielectric is formed on the pre-metal dielectric layer. The BEOL dielectric includes a plurality of inter-metal dielectric (IMD) layers having metal levels and via levels, the metal levels including metal lines and the via levels including via contacts to interconnect CMOS and MEMS components of the device via the pre-metal dielectric layers. The BEOL dielectric and the pre-metal dielectric are patterned to form a sensor opening in the dielectric layer. Patterning of the dielectric layer also forms relief openings to expose the cavity trench fills. A first release is performed to remove the cavity trench fill, thereby forming a lower sensor cavity, followed by a second release to remove the sensor support dielectric. This results in the sensor being a stand-alone sensor. The independent sensor improves sensor sensitivity and response time.

These and other advantages and features of the embodiments disclosed herein will become apparent by reference to the following description and accompanying drawings. Furthermore, it is to be understood that the features of the various embodiments described herein are not mutually exclusive and may exist in various combinations and permutations.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate preferred embodiments of the disclosure and together with the description, serve to explain the principles of various embodiments of the disclosure.

Fig. 1 shows a top view of a semiconductor wafer;

FIG. 2a shows a simplified cross-sectional view of one embodiment of a device;

FIG. 2b shows a simplified cross-sectional view of another embodiment of the device;

FIG. 3a shows a simplified top view of one embodiment of a sensor;

FIGS. 3B to 3c show simplified cross-sectional views along A-A 'and B-B' of the sensor of FIG. 3 a;

FIG. 3d shows a simplified cross-sectional view along B-B' of an alternative embodiment of the sensor of FIG. 3 a;

FIG. 4a shows a simplified top view of another embodiment of a sensor;

FIG. 4b shows a simplified cross-sectional view along A-A' of the sensor of FIG. 4 a;

FIG. 4c shows a simplified cross-sectional view along A-A' of an alternative embodiment of the sensor of FIG. 4 a;

FIG. 5a shows a simplified top view of another embodiment of a sensor;

FIGS. 5B to 5c show simplified cross-sectional views along A-A 'and B-B' of the sensor of FIG. 5 a;

FIG. 5d shows a simplified cross-sectional view along B-B' of an alternative embodiment of the sensor of FIG. 5 a;

FIG. 6a shows a simplified top view of another embodiment of a sensor;

FIG. 6b shows a simplified cross-sectional view along A-A' of the sensor of FIG. 6 a;

FIG. 6c shows a simplified cross-sectional view along A-A' of an alternative embodiment of the sensor of FIG. 6 a;

FIG. 7a shows a simplified cross-sectional view along B-B' of one embodiment of a sensor;

FIG. 7B shows a simplified cross-sectional view along B-B' of another embodiment of a sensor;

FIG. 8a shows a simplified cross-sectional view along B-B' of another embodiment of a sensor;

FIG. 8B shows a simplified cross-sectional view along B-B' of another embodiment of a sensor;

9 a-9 q illustrate cross-sectional views of one embodiment of a process for forming a device;

10 a-10 b show top views of layouts of sensor regions corresponding to different metal levels, showing etchant flow paths during a second release of a dual release process;

FIGS. 11a to 11b show simplified cross-sectional views along A-A' of FIGS. 10a to 10b of the sensor area of the device after a first release process and after a second release process;

Fig. 12a to 12B show simplified cross-sectional views along B-B' of fig. 10a to 10B of the sensor area of the device after a first release process and after a second release process;

Fig. 13a to 13b show simplified cross-sectional views along C-C' of fig. 10a to 10b of the sensor area of the device after a first release process and after a second release process; and

Fig. 14 shows graphs of thermal conductivity, temperature increase, and response speed of the respective thermal sensors.

Detailed Description

Embodiments relate generally to devices, such as semiconductor devices or Integrated Circuits (ICs), having a pyroelectric based infrared detector. For example, the IC is a Complementary Metal Oxide Semiconductor (CMOS) device. As far as infrared detector is concerned, it is for example a microelectromechanical system (MEMS) detector. The MEMS detector is embedded in an IC with high CMOS integration. Furthermore, MEMS detectors are compatible with CMOS processing. These devices may be incorporated into products such as thermal imagers. For example, the apparatus may include a plurality of MEMS sensors that may be configured to form a sensor array for a thermal imager. The sensor may be used in other types of applications such as single pixel or line array temperature or motion sensors.

Fabrication of the device may involve forming features, such as transistors, resistors, capacitors, and MEMS sensors, on a substrate that form circuit components. These components are interconnected so that the device can perform the desired functions. To form features and interconnects, the layers are repeatedly deposited on the substrate using photolithographic techniques and patterned as desired. For example, a wafer is patterned by exposing a photoresist layer with an exposure source using a reticle containing the desired pattern. After exposure, the photoresist layer is developed, thereby transferring the pattern of the reticle to the photoresist layer. This forms a photoresist etch mask. Etching is performed using an etch mask to replicate a pattern on the underlying wafer, which pattern may include one or more layers, depending on the stage of the process. In the formation of the device, a number of photomasks may be used for different patterning processes. Furthermore, a plurality of devices may be formed in parallel on a wafer.

Figure 1 illustrates a simplified plan view of one embodiment of a semiconductor wafer 101. For example, the semiconductor wafer may be a silicon wafer. The wafer may be a lightly doped p-type wafer. Other types of wafers, such as silicon-on-insulator (SOI) or silicon-germanium wafers, as well as doping with other types of dopants or dopant concentrations may also be useful.

The wafer includes an active surface 111 on which devices 115 are formed. Multiple devices may be formed in parallel on a wafer. For example, the devices are arranged in rows along a first (x) direction and in columns along a second (y) direction. The cutting channel separates the devices. After the processing is completed, the wafer is diced along dicing lanes to singulate the devices into individual chips.

Fig. 2a shows a simplified embodiment of an apparatus 200. For example, the device is a CMOS device with embedded MEMS structures or components. In one embodiment, the device is a CMOS device embedded with a pyroelectric-based infrared sensor. As shown, the device incorporates a pyroelectric-based infrared sensor. It should be appreciated that the apparatus may include a plurality of sensors configured to form a sensor array. For example, the device may be an infrared imager, wherein each sensor may be a pixel of the infrared imager. Other types of MEMS structures or applications may also be useful.

The device includes a substrate 205. For example, the device may be part of a wafer, as depicted in fig. 1. Common elements may not be described or depicted in detail. For example, the substrate may be a semiconductor substrate, such as a silicon substrate. For example, the substrate may be a lightly doped p-type silicon substrate. Other types of substrates or wafers may also be useful. In one embodiment, the substrate includes a first device region 204 and a second device region 206. The first device region is a CMOS region and the second region is a sensor region. The CMOS region includes CMOS components and the sensor region includes MEMS sensors, such as CMOS compatible infrared sensors.

As shown, the CMOS area includes first and second CMOS component areas 220. The first component area may be a first type component area and the second component area may be a second type component area. The first type component region may be a p-type component region and the second type component region may be an n-type component region. For example, the component area accommodates a metal oxide field effect transistor (MOSFET) 222. For example, the component region is a transistor region. It may also be useful to provide component areas for other types of components. In one embodiment, the first transistor region is a p-type transistor region for a p-type transistor and the second transistor region is an n-type transistor region for an n-type transistor.

The transistor region includes a transistor well 221. The transistor well is an oppositely doped well. For example, if the transistor region is a p-type (first type) transistor region, the well is an n-type (second type) doped well. The transistor well serves as the body of the transistor. The transistor includes a gate disposed over the substrate between first and second heavily doped source/drain (S/D) regions 224, 224 _1-2 of the first type disposed in the transistor well.

The gate of the transistor may include a gate electrode 234 over the gate dielectric 232. The gate electrode may be polysilicon and the gate dielectric may be thermal silicon oxide. Other types of materials or gate configurations may also be useful. For a p-type MOS transistor, the device well is an n-type well and the S/D region is a heavily doped p-type region. N-type transistors, on the other hand, have p-type device wells and heavily doped n-type S/D regions. The S/D regions may include lightly doped extension regions. The lightly doped extension regions are lightly doped with the same polarity type dopant as the heavily doped S/D regions. The sidewalls of the gate may include dielectric spacers. Spacers facilitate alignment of the S/D and lightly doped extension regions. The transistor well may include a well contact 228 that is heavily doped with a dopant of the same polarity type as the transistor well.

As shown, the CMOS region may be a logic region including a first transistor and a second transistor. However, the logic region may include many transistors. Further, the logic region may include regions for transistors having different operating characteristics or voltages. For example, a low voltage transistor may be disposed in a Low Voltage (LV) region, an intermediate or medium voltage transistor may be disposed in a Medium Voltage (MV) region, and a high voltage transistor may be disposed in a High Voltage (HV) region. Other types of device areas may also be included. For example, a memory region in which a memory array is disposed may be included.

Isolation regions 280 are provided to isolate the component regions. For example, isolation regions are provided to isolate the first and second transistor regions and the sensor region. Furthermore, isolation regions may be provided to isolate the well contacts from the S/D contacts. The isolation region may be a Field Oxide (FOX) isolation region. Other types of isolation regions, such as Shallow Trench Isolation (STI) regions, may also be useful.

As shown, the sensor region includes a sensor 250, such as a CMOS compatible sensor. For example, the sensor area is configured for one sensor. In one embodiment, the sensor is a MEMS infrared sensor. Other types of sensors may also be useful. As shown, the lower sensor cavity 260 is disposed in the substrate below the sensor. In one embodiment, the lower sensor cavity is disposed below the surface of the substrate. For example, the lower sensor cavity is a trench that has been etched into the substrate. The lower sensor cavity may have a square or rectangular footprint or shape. Other shapes of the lower sensor cavity may also be useful. The bottom and sides of the lower sensor cavity are defined by the substrate.

A reflector 262 is provided at the bottom of the lower sensor cavity. The reflector reflects infrared radiation. The reflector may be formed of a conductive material. In one embodiment, the reflector is a conductive metal silicide reflector. The metal silicide reflector may be a titanium silicide (TiSi _x), tungsten silicide (WSi _x), or aluminum silicide (AlSi _x) reflector. Other types of metal silicide reflectors may also be useful. Alternative types of reflectors may also be useful. For example, the reflector may be a conductive reflector layer. The conductive reflector layer may be a doped reflector layer, such as a doped polysilicon layer. The doped reflector layer may be heavily doped with a p-type or n-type dopant. For example, the dopant concentration of the doped reflector layer may be about 10 ²¹ dopants/cm ³. The conductive nature of the surface of the doped region is due to the high concentration of the applied dopant, thereby being able to reflect incoming infrared radiation. In other embodiments, the reflector may be a non-conductive reflector, such as a photonic crystal reflector. The photonic crystal layer is formed, for example, by etching the surface of the underlying sensor cavity. The photonic crystal layer may include a grating pattern configured to reflect incident infrared radiation. For example, different grating patterns of different depths may be etched from the surface of the photonic crystal layer to adjust the wavelength and nature of the reflected infrared radiation. Other types of reflectors may also be useful.

In one embodiment, the sensor is a stand-alone infrared MEMS sensor suspended above a lower sensor cavity. In one embodiment, the infrared MEMS sensor is a thermopile infrared sensor. The stand-alone MEMS sensor does not have a supporting dielectric layer disposed thereunder. For example, the supporting dielectric layer and the protective dielectric layer are removed during the second release process. The individual sensors define the top of the lower sensor cavity.

In some embodiments, the stand-alone sensor includes an absorber layer (not shown) on its surface. In this case, the individual sensor comprises an absorber layer located above it. For example, the absorber layer is configured to absorb incident infrared radiation. In one embodiment, the absorber layer is disposed on a central portion of the sensor body. The absorber layer is thermally coupled to the center of the sensor body. The absorber layer may be a silicon nitride (SiN) layer. Other types of absorber layers may also be useful. For example, the absorber layer may be a doped polysilicon layer, a nickel chromium (NiCr) layer, or a titanium nitride (TiN) layer. In the case of a conductive absorber layer, it is electrically and thermally coupled to the hot side of the sensor. A protective layer may be provided to protect the absorber layer. The protective layer may be removed by a second release process.

In one embodiment, the absorber is part of an interference absorbing system. For example, the absorber may be integrated as part of an interference system to improve absorption efficiency or performance. In one embodiment, the interference absorbing system is configured or tuned to efficiently absorb incident infrared radiation of a desired wavelength. For example, the absorption system may be tuned to absorb greater than 80% of incident infrared radiation having a wavelength of 8-14 μm. It may also be useful to provide any other configuration. In other embodiments, the absorber is configured to absorb incident radiation having a wavelength of 2-5 μm. For example, another harmonic of the interference absorber may be used. In one embodiment, the interference absorbing system includes an absorber and a reflector with a 1/4 wavelength separation disposed therebetween. For example, the desired wavelength is the center wavelength of the desired wavelength range to be absorbed. The high efficiency interference absorber layer improves sensor sensitivity.

In one embodiment, the depth of the lower sensor cavity is selected to achieve optimal reflection of infrared radiation by the reflector. For example, the lower sensor cavity is part of an interferometric absorption system. In one embodiment, the depth of the cavity is sufficient to ensure a 1/4 wavelength optical distance between the absorber and the reflector. For example, for infrared radiation having a detection wavelength of 8-12 μm, the optical distance may be about 2-3 μm. Other distances may also be useful depending on the wavelength to be detected. For example, infrared radiation having smaller or larger wavelengths may be detected by decreasing or increasing the optical distance, respectively. The optical distance is defined as the distance that the infrared radiation wave has an optical path through several layers.

In one embodiment, the sensor includes a sensor body having a first body segment 251 _P and a second body segment 251 _N. In one embodiment, the first body segment and the second body segment are doped with a first polarity type dopant and a second polarity type dopant. For example, the first body segment is doped with a p-type dopant and the second body segment is doped with an n-type dopant. For example, the sensor body is patterned to form a first body segment and a second body segment. The sheet resistance of the sensor body was adjusted to match the ambient sheet resistance (about 377 Ω/square). This advantageously enables the sensor body to also act as an absorber. For example, no additional absorber layer is required. In one embodiment, the sensor body is a polysilicon sensor body. Other types of materials with thermoelectric properties that are stable at high temperatures may also be used as the sensor body. For example, such materials may include silicon germanium (SiGe), gallium nitride (GaN), or 2D materials such as graphene, black phosphorus, or molybdenum sulfide.

In one embodiment, the sensor body is configured to resist a second release process (second release etchant). In case an absorber layer is provided above the sensor body, the absorber layer should also be resistant to the second release etchant. If not, a protective layer is provided over the absorber layer.

Patterning and doping of the sensor body may be achieved using, for example, masking and doping and masking and patterning techniques. As for the doping of the body segments, it can be integrated with the S/D doping process of p-type and n-type transistors. Other techniques for doping the body segments may also be useful.

Patterning of the sensor body forms a sensor body segment having a main segment and a lead segment. For example, patterning of the sensor body forms a p-doped body segment having a p-doped main segment and a p-doped lead segment and an n-doped body segment having an n-doped main segment and an n-doped lead segment. The ends of the first and second lead segments serve as first and second sensor terminals. For example, the first and second terminals are the cold ends or terminals of the pyroelectric sensor. Patterning of the sensor body also forms openings or spaces 254 within the sensor body. For example, a space is provided between the sensor body main section and the lead section. Other configurations of spaces, sensor body main segments, and lead segments may also be useful. The opening facilitates a release process for forming the lower sensor cavity. In one embodiment, the patterning also forms undoped body spacers (not shown) in contact with both the first body segment and the second body segment. The spacer enhances the mechanical stability of the individual sensor body.

In one embodiment, the first body section and the second body section have substantially the same surface area to create substantially symmetrical heat dissipation between the sections. There may be machining differences resulting in differences in the surface areas of the first and second body segments. Preferably, the difference is less than about + -5%. Other differences that create acceptable heat dissipation differences between the body segments may also be useful. For example, the surface area difference may be less than about ±20%. In one embodiment, the first body section and the second body section are substantially mirror images of each other. Other configurations of the body segments may also be useful.

In one embodiment, the sensor is a dual release sensor. For example, a first release process is used to create the lower sensor cavity, while a second release process is used to create the stand-alone sensor by removing the supporting and protective dielectric layer. The second release forms a step 268 in the contact dielectric layer 271.

In one embodiment, the sensor body contact 255 couples the first body segment and the second body segment. The body contacts may be provided at the interface of the first body section and the second body section, thereby interconnecting them. As shown, the sensor body contacts include a sensor body via contact 257 connected to the body segment and a second body interconnect 256 interconnecting the sensor body via contacts. In one embodiment, the sensor body contacts should be high temperature contacts. For example, the sensor body contacts may maintain a subsequent process temperature. The components of the sensor body contacts may be formed of titanium (Ti), aluminum (Al), or a combination thereof. Other types of high temperature metals compatible with CMOS processes may also be used to form the components of the sensor body contacts. In one embodiment, the sensor body via contacts are closed loop sensor body via contacts. For example, the closed loop via contact traps dielectric within the closed loop even after the second release process. This provides additional mechanical stability to the individual sensor bodies.

A pre-metal interlayer dielectric (ILD) layer 271 is disposed on the substrate over the CMOS components. As shown, the pre-metal ILD layer includes a pre-metal contact 272 that is connected to a contact area of the feature. For example, a metal front contact is connected to the S/D region, transistor gate and well contact. For example, the metal front contact may be a tungsten (W) contact. Other types of contacts may also be useful. The pre-metal ILD layer may be formed of a plurality of dielectric layers. Various dielectric materials, such as silicon oxide (SiO ₂), may be used to form the premetal ILD layer. The metal front contact may be formed by a single damascene process. Other techniques for forming the metal front contact may also be useful.

The formation of CMOS components, such as transistors, sensors, and ILD layers with metal front contacts may be considered part of a front end of line (FEOL) process. After FEOL processing, subsequent process processing begins. Other configurations of FEOLs and BEOLs may also be useful.

A back end of line (BEOL) dielectric layer 270 is disposed over the ILD layer. In one embodiment, the BEOL dielectric is formed by BEOL processing. In one embodiment, the BEOL dielectric layer includes a plurality of inter-metal dielectric (IMD) layers 274 disposed over the pre-metal ILD layer. IMD layers include a metal dielectric level or layer 274 _M below via dielectric level 274 _V. The dielectric layer of the IMD layer may be SiO ₂. Other types of dielectric materials or combinations of dielectric materials or layers may also be used to form IMD layers. The metal level includes metal lines 277 in the metal dielectric layer, and the via level includes via contacts 273 in the via dielectric layer. The metal lines and via contacts may be formed using damascene techniques, such as single damascene or dual damascene processes. In the case of a single damascene process, the contacts and metal lines are formed in different processes. In the case of a dual damascene process, the metal lines and contacts are formed in the same process.

In some embodiments, a Reactive Ion Etching (RIE) process may be used to form the metal lines. For example, a metal layer is formed and patterned by RIE using an etching mask to form metal lines. Different IMD layers may employ different processes. For example, one IMD layer may use a different single damascene process to form contacts and metal lines, another IMD layer may use a dual damascene process to form contacts and metal lines, and yet another IMD layer may use a single damascene process to form contacts followed by a RIE process to form metal lines.

The IMD layer may be planarized to form a planar top surface over the CMOS region and the MEMS region. For example, CMP is performed on a substrate. It may also be useful to provide any other planarization technique, such as spin-on glass (SOG), to fill the gap or planarize the surface of the substrate. The total thickness of the IMD layer over the structure may be 100-400nm. It may also be useful to provide any other thickness for IMD layers over the structure to define the depth of the via for subsequent standard CMOS processes.

A passivation layer 278 is disposed over the top metal level of the BEOL dielectric layer. The passivation layer may be a silicon nitride layer. Other types of passivation layers may be used. The passivation layer may serve as an etch stop and top protection layer. In some embodiments, the passivation layer may be a passivation stack having multiple passivation layers, such as a combination of silicon oxide and silicon nitride layers. As shown, a dielectric layer is provided over the top metal dielectric layer. The dielectric layer may be considered a top via dielectric layer below the passivation layer. In some cases, the dielectric layer may be considered part of the passivation stack. In other cases, the dielectric layer may be disposed over the passivation layer, but removed during processing. Other configurations of passivation layers may also be useful. The passivation layer serves as a protective layer for the BEOL dielectric layers during the dual release process used to form the sensor.

The top metal level of the top BEOL dielectric serves as the pad level. A bond opening 276 is provided in the passivation layer to expose an underlying bond pad. For example, the top metal level of the BEOL dielectric layer is covered by a passivation stack. The top metal level does not include a via level. The bond pads provide external channels for internal components of the device. For example, input, output, and power signals may be provided via bond pads. Bond pads are provided at the periphery of the device. As shown, the bond pads are provided on one side of the device, which is the opposite side of the sensor area. Bond pads may also be provided on one or more other sides of the device.

As shown, the BEOL dielectric layer includes 2 IMD layers including metal layers M1 and M2. A top metal level M3 is provided above V2. The top metal level is covered by a passivation stack. Metal level M1 is the bottom metal level and metal level M3 is the top metal level. It may also be useful to provide other numbers of IMD layers. The number of IMD layers may depend on the CMOS process employed. Typically, a single damascene process is used to form the pre-metal ILD level. For example, a pre-metal contact is formed in a contact opening of the pre-metal ILD layer to couple to each terminal of the component. The metal front contact may contact the S/D area of the transistor, the well contact, and the terminal of the sensor. The first metal level of the first IMD layer may employ a single damascene or RIE process. As for the M2 metal line of the second metal dielectric layer and the V1 via contact of the first via dielectric layer, they may be formed by a dual damascene process. Likewise, the M3 metal lines and V2 via contacts may be formed by dual damascene techniques. Other configurations of the process for forming the various IMD layers may also be useful.

BEOL provides interconnections between CMOS components and sensor regions to operate the sensor. For example, CMOS components provide power to the sensor, thereby switching the sensor. Furthermore, the CMOS components are capable of storing information and reading information from the sensor. CMOS components may also be configured to perform other functions.

In some embodiments, the sensor area includes a sensor array having a plurality of sensors arranged in a matrix having a plurality of rows and columns of sensors. Each sensor corresponds to a pixel in the pixel array. For example, the CMOS components may include select switches, row and column decoders and readout circuits. Other CMOS components may also be included. The CMOS components are configured to read out each pixel of the array. Once the entire sensor array is read out, an image can be reconstructed. For example, an image is a frame corresponding to a sensor in an array.

In one embodiment, the BEOL and pre-metal dielectric material in the sensor region are removed to expose the sensor. For example, removal of the dielectric over the sensor forms an upper sensor or BEOL cavity 264. In one embodiment, metal lines and vias may be provided in the BEOL to facilitate the configuration of the cavity profile. For example, the metal lines and vias may form a dam structure around the sensor region, thereby preventing erosion of the dielectric layer from the release process into the CMOS region.

Cap 240 is disposed on the substrate, encapsulating the CMOS area and the sensor area. The cap is disposed on the periphery of the device within the bond pad. For example, the bond pads are disposed outside of the CMOS and sensor regions of the package. This enables access to the bond pads. The cap includes an upper cap portion and a lower cap portion. The cap portion may be integrated. For example, the cap portion is formed from a single cap material. As shown, the upper and lower portions of the sides of the cap are aligned. Alternatively, the upper portion may protrude above the bond pad such that the upper and lower portions on the sides are not aligned with the bond pad. Other configurations of caps may also be useful.

A cap cavity 265 is provided in the lower portion of the cap and is located above the CMOS area and the sensor area with the upper cavity 264. The cap cavity and the upper sensor cavity may be collectively referred to as a cap cavity. In one embodiment, the cap cavity is vacuum. The cap is formed of a material transparent to infrared radiation. For example, the cap can transmit infrared radiation to the sensor. The cap may be a silicon (Si) cap. Other types of materials, such as germanium (Ge), silicon germanium (SiGe), or zinc sulfide (ZnS), may also be used to form the cap. It may also be useful to provide caps formed from other types of materials that transmit infrared radiation.

In one embodiment, the cap includes an anti-reflective region 244. The anti-reflection region facilitates transmission of infrared radiation through the cap. In one embodiment, the anti-reflective region includes a bottom grating on the inner (bottom) surface of the cap and a top grating on the outer (top) surface of the cap. The grating may have a moth-eye grating pattern or structure to facilitate transmission of infrared radiation. The grating may have other patterns that facilitate transmission of infrared radiation. The grating may be formed by etching the surface of the cap. The antireflective regions are described in co-pending U.S. patent application Ser. No. 17/612,200, filed on, for example, 11/2021, which application has been incorporated by reference herein for all purposes.

In another embodiment, the anti-reflective region includes an anti-reflective coating disposed on the front and rear sides of the cap. Alternatively, materials having different reflectivities may be deposited on the surface of the anti-reflective regions. For example, the material for the anti-reflective coating may be zinc sulfide (ZnS) or germanium (Ge). It may also be useful to provide any other materials and deposition techniques for the anti-reflective coating. An anti-reflective coating may be deposited on the surface of the cap and patterned to remain in the anti-reflective region.

A getter (not shown) may be provided on the inner surface of the cap. For example, the getter may be disposed in a recessed region on the inner surface of the cap adjacent to the anti-reflective region. The getter absorbs moisture and outgassing within the packaged device. For example, the getter may be a zirconium (Zr) alloy, titanium (Ti), nickel (Ni), aluminum (Al), barium (Ba), or magnesium (Mg). Other types of getter materials, such as rare earth elements including cerium (Ce) or lanthanum (La), may also be useful. The getter facilitates maintaining the integrity of the vacuum within the cavity, thereby improving reliability.

In one embodiment, a seal ring 282 is employed to facilitate bonding of the cap to the substrate. For example, the seal rings include a cap seal ring 282b and a substrate seal ring 282a. In one embodiment, a cap seal ring surrounds the sensor region and the CMOS region. The cap seal ring and the substrate seal ring cooperate to bond the cap to the substrate. In one embodiment, the seal ring may be a metal or metal alloy. The seal ring may be a gold-based seal ring, such as gold, gold tin, or a combination thereof. It may also be useful to provide other materials and structures for the seal ring. In one embodiment, the sealing ring is by a heat press fit. Other techniques for bonding the cap to the substrate by forming a thermocompression bond or a eutectic bond may also be useful.

The cap may be part of a cap wafer that is processed to form a plurality of caps. The cap wafer may be bonded to a wafer having a plurality of devices. For example, wafer level vacuum packaging bonds caps to devices. The cap wafer and the device wafer are diced to separate the devices into individual vacuum packaging devices.

As described above, the sensor area includes 1 sensor. However, it should be understood that the sensor area may include a plurality of sensors. For example, the sensors may be configured in a matrix form, wherein a plurality of rows and columns of sensors form a sensor array. For example, each sensor may correspond to a pixel of an image (such as a thermal image).

In one embodiment, as shown in FIG. 2b, each sensor 250 is configured with its corresponding lower sensor cavity 260. For example, a matrix of sensor cavities is provided for the sensor matrix. The sensor cavities may be separated by a substrate wall. In one embodiment, a dielectric spacer is provided on top of the substrate wall between the sensor cavities. For example, the dielectric spacers are part of ILD layer 271 and BEOL dielectric layer 270. For example, the dielectric spacer includes via contacts and interconnects for connection to the sensor. The cap cavity may be a common cavity of the sensor above the dielectric spacer.

Fig. 3a shows a simplified top view of one embodiment of a sensor 350. Fig. 3B to 3c show simplified cross-sectional views of the sensor along A-A 'and B-B'. FIG. 3d shows a simplified cross-sectional view along B-B' of an alternative embodiment of the sensor. The sensor is a CMOS compatible sensor. In one embodiment, the sensor is a thermo-electric based Infrared (IR) detector. The sensor is disposed within a sensor region of a CMOS device having an embedded sensor. As shown, the sensor includes a sensor body. The sensor body includes a first sensor segment 351 _P and a second sensor segment 351 _N. In one embodiment, the first body segment is doped with a p-type dopant and the second body segment is doped with an n-type dopant. The body section includes a main section and a lead section. For example, the first body segment includes a first main segment 353 _PM and a first lead segment 353 _PL; the second body segment includes a second main segment 353 _NM and a second lead segment 353 _NL.

In one embodiment, the first body section and the second body section are configured to have substantially the same surface area. For example, the first body segment (first main segment and first lead segment) has approximately the same surface area as the second body segment (second main segment and second lead segment). For example, the first body section and the second body section are substantially symmetrical. There may be machining differences resulting in differences in the surface areas of the first and second body segments. Preferably, the difference is less than about + -5%. It may also be useful to provide other differences between the surface areas of the body segments. For example, the surface area difference may be less than about ±20%.

In other embodiments, the body segments may not be symmetrical. For example, body segment symmetry is not critical or necessary. In some cases, it may be desirable to have an asymmetric body segment. For example, where p-doped polysilicon is more efficient in terms of IR absorption, the p-doped body may be configured to be larger than the n-doped body segment to increase IR absorption efficiency. Other configurations of the body segments may also be useful.

In one embodiment, the sensor body is rectangular. For example, when the first body section and the second body section are combined, the first body section and the second body section form a rectangular sensor body. In one embodiment, the first main section and the second main section together form a rectangular main section portion of the sensor body. The first and second lead segments extend from the first and second main segments. The first lead segment and the second lead segment are configured to form a rectangular sensor body. In one embodiment, the first body section and the second body section have similar shapes, except that they are flipped vertically and horizontally. Other configurations of the sensor body segments and/or shaped sensor bodies may also be useful. The lead segments or extension segments also advantageously function as absorbers (e.g., doped polysilicon absorbers).

As shown, the main section is a substantially right isosceles triangle member and the lead section is an elongated member extending from one end of the main section between the base of the isosceles triangle member and one of the sides. Other shapes of the main section may also be useful. For example, the shape of the sensor body may depend on design requirements, such as available space. The lead segments are connected to the main segment and extend outwardly along the sides of the isosceles shaped member. The main and lead segments are separated by an L-shaped gap 389 (e.g., a main-lead gap) therebetween. The first and second main sections are similarly shaped sections, except that one is flipped vertically and horizontally relative to the other. In one embodiment, the first main section and the second main section are isolated sections. In some cases, the segments may be connected by undoped anchor points. In other cases, the segments are completely isolated from each other. A gap is provided to avoid dopant diffusion.

Anchor points 352 may be disposed within the base gaps between the bases. For example, the anchor point is the connecting portion of the first main segment and the second main segment within the base gap, as shown in fig. 3 b. The anchor point provides additional mechanical support for the independent sensor body. As shown, the first anchor point and the second anchor point are disposed proximate opposite ends of the base gap. Other configurations of anchor points may also be useful. For example, a greater or lesser number of anchor points may be provided.

In one embodiment, the sensor body is a polysilicon sensor body. Other types of materials with thermoelectric properties that are stable at high temperatures may also be used as the sensor body. For example, such materials may include silicon germanium (SiGe), gallium nitride (GaN), or 2D materials such as graphene, black phosphorus, or molybdenum sulfide.

In one embodiment, the sensor body is doped with a p-type dopant and an n-type dopant to form a p-region and an n-region. For example, doping may be achieved using ion implantation with a mask. For example, to form a p-region of the sensor body, a p-type dopant is implanted into the sensor body where the n-region is masked, such as with a resist or implantation mask. Similarly, to form an n-region of the sensor body, n-type dopants are implanted into the sensor body where the p-region is masked. For example, the doping of the body segments may be integrated into the S/D doping process of the p-type transistor and the n-type transistor. Other techniques for doping the body segments may also be useful. For example, different doping processes may be employed to form doped body segments.

In one embodiment, the sensor body is patterned prior to doping. For example, after a patterning process that forms the sensor body (e.g., first and second body segments and first and second anchor points), it is doped to form n-regions and p-regions. The ends of the first and second lead segments serve as first and second sensor terminals. For example, the first and second terminals are cold ends of the sensor. The sensor body also includes spaces or gaps, such as a main-lead gap and a base gap. Other configurations of gaps may also be useful. The gap facilitates a release process for forming the lower sensor cavity and creates thermal isolation between the main section and the lead section. The patterning process may include masking and etching processes, such as a patterned resist mask used as an etching mask for a Reactive Ion Etching (RIE) process.

In the case of a polysilicon based sensor body, it may be formed from a polysilicon layer for forming the gate electrode. For example, a CMOS process may include a gate electrode layer of a gate electrode, and may also be used as a polysilicon sensor. Where the CMOS process includes more than one polysilicon gate electrode layer, a thinner polysilicon gate electrode layer may be preferably selected as the polysilicon sensor. Alternatively, a gate electrode layer is preferably selected that matches or closely matches the desired thickness of the sensor body thickness. In another embodiment, a separate layer may be employed as the sensor body. Other configurations of forming the gate and sensor body may also be useful.

In one embodiment, the sensor body contacts 355 couple the first body section and the second body section. As shown, the sensor body contacts are disposed on the top surface of the sensor body. For example, the sensor body contacts are disposed on a top surface opposite a bottom surface facing the downward sensor cavity. In one embodiment, the sensor body contact is disposed near the interface of the first main section and the second main section. For example, the sensor body contacts are provided above the base gap between the main sections. As shown, the sensor body contact occupies a central portion of the interface of the first and second main segments between the anchor points. It may be preferable that the body contact be as short as possible. However, a minimum length is required to ensure mechanical strength and adhesion between the contacts and the sensor body. The minimum length depends on, for example, a baseline design rule that accommodates the body contacts. Illustratively, the length of the sensor body is about 1/3 of the total length of the pedestal gap between anchor points. Other configurations including the length of the sensor body contacts may also be useful.

As shown, the sensor body contacts include a first sensor body through-hole contact 357 _P and a second sensor body through-hole contact 357 _N that are connected to the first body section and the second body section. The bottom surfaces of the first and second body via contacts are coupled to the first and second main sections. The sensor body interconnect 356 interconnects the top surfaces of the first and second via contacts. For example, a sensor body interconnect electrically connects the first body segment and the second body segment together. In one embodiment, the sensor body via contacts are closed loop via contacts. For example, the closed-loop via contact includes a metal contact configured as a metal ring forming a closed loop. As shown, the via contacts are configured as rectangular metal rings. As shown in fig. 3c, dielectric fill 386 is located within the closed loop. For example, the dielectric filler may be silicon oxide. Other types of dielectric materials may also be useful. The dielectric filler provides additional mechanical support for the individual sensor bodies.

In one embodiment, the sensor body contacts comprise high temperature contacts. For example, the sensor body contacts may maintain a subsequent process temperature. The components of the sensor body contacts may be formed of titanium (Ti), aluminum (Al), copper (Cu), or a combination thereof. Other types of high temperature metals may also be used for the components forming the sensor body contacts. The type of material used for the contacts may depend on the technology node. For example, mature technology nodes may employ Al, while advanced technology nodes may employ Cu.

In some embodiments, silicide contacts 358 are provided on the main section, as shown in fig. 3 d. The first and second silicide contacts 358 _P and 358 _N are disposed in contact regions of the first and second main segments 351, _P and 351, _N. As shown, the silicide contacts are disposed on the surface portions of the main segments where the body via contacts are disposed. For example, first sensor body via contact 357 _P and second sensor body via contact 357 _N are disposed over the first silicide contact and the second silicide contact. The silicide contacts reduce the contact resistance between the main segment and the via contacts. Silicide contacts may be formed by providing metal over the contact areas of the sensor body and then annealing.

As discussed, the first and second body segments are doped with first and second dopants, such as p-type dopants and n-type dopants. In one embodiment, the sheet resistance of the body segment is adjusted to match the ambient (atmospheric) sheet resistance (about 377 Ω/square). Adjusting the sheet resistance of the body segment to the atmospheric sheet resistance advantageously enables the body sensor to function as an absorber, obviating the need to use a separate absorber layer. An additional absorber such as TiN or SiN may be provided on the body segment even though the body sensor is already used as an absorber. This further enhances IR absorption.

In other embodiments, if the sensor body is not used as an absorber, a separate absorber (not shown) is provided on the main section. Examples of configurations of absorbers are shown and described in fig. 7a, 7b, 8a and 8 b. The absorber may be disposed on the first main section and the second main section. For example, an absorber may be formed over the patterned sensor body. The absorber layer is then patterned, followed by formation of the sensor body contacts.

The absorber may be provided when the sensor body sheet resistance is not tuned to the ambient sheet resistance. In other embodiments, an absorber is provided in addition to having the sensor body adjusted to match the ambient sheet resistance. This may further enhance absorption.

For example, the absorber is configured to absorb incident infrared radiation. The absorber may be a silicon nitride layer. Other types of absorbers, such as titanium nitride (TiN), nickel chromium (NiCr), or other materials, may also be useful. In one embodiment, the absorber is configured as part of an interference system that absorbs a majority of incident infrared radiation. For example, the absorber interference system may be configured to absorb greater than 80% of incident infrared radiation having a wavelength of 8-14 μm. It may also be useful to provide any other configuration of absorbers. In other embodiments, the absorber is configured to absorb incident radiation having a wavelength of 2-5 μm.

A sensor protection layer (not shown) may be provided over the absorber layer. Examples of different configurations of the sensor protection layer are shown and described in fig. 7b and 8 b. The sensor protection layer is used to protect the sensor from the subsequent etching process. For example, the protective layer is used to protect the sensor body and absorber from etchants such as XeF ₂/SF₆ and VHF used in the first and second release processes. In one embodiment, a multi-layer protective layer may be employed. For example, the outer layer or exposed layer may be removed during the second release process, leaving the inner layer protecting the absorber after the outer layer is removed. For example, the remaining protective layer is transparent to infrared radiation and selective to the second release process.

The absorber may have various configurations. For example, the absorber may be separated from the sensor body by a dielectric liner (such as silicon oxide). Alternatively, the absorber may be embedded in a dielectric layer (such as silicon oxide) that is encapsulated by a sensor protection layer (such as SiN). Other configurations of absorbers may also be useful.

Fig. 4a shows a simplified top view of one embodiment of a sensor 450. Fig. 4b shows a simplified cross-sectional view of the sensor along A-A'. FIG. 4c shows a simplified cross-sectional view along A-A' of an alternative embodiment of the sensor. The sensor is a CMOS compatible sensor. The sensor is similar to the sensor described in fig. 3a to 3 d. Common elements may not be described or depicted in detail.

As shown, the sensor includes a sensor body having a first sensor segment 451 _P and a second sensor segment 451 _N. For example, the first body segment is doped with a p-type dopant and the second body segment is doped with an n-type dopant. The first body section includes a first main section 453 _PM and a first lead section 453 _PL; the second body section includes a second main section 453 _NM and a second lead section 453 _NL.

Sensor body contacts 455 are provided to electrically connect the first body section and the second body section. The sensor body contacts include a first sensor body via contact 457 _P and a second sensor body via contact 457 _N connected to the first body section and the second body section. The sensor body interconnect 456 interconnects the body via contacts. For example, the sensor body via contacts are closed loop via contacts.

Unlike the embodiment of fig. 3a to 3d, the sensor body contacts occupy a major central portion of the interface of the first and second main sections. As shown, the length of the sensor body contacts occupy about 80-90% of the base gap at the interface of the main section. By having such a long body contact it provides sufficient mechanical stability and adhesion, thereby obviating the need for an anchor point. By eliminating the need for anchor points, dopant interdiffusion between the first and second body segments is avoided. For example, without an anchor point, the first body segment and the second body segment are completely isolated from each other. However, it will be appreciated that although an anchor point is not required, an anchor point may still be provided. In addition, larger contacts reduce contact resistance. However, this comes at the cost of reduced absorber area. Even if the absorber area is reduced, the sensor should still have sufficient absorption. Other configurations of the sensor body contacts may also be useful. In addition, to further reduce contact resistance, silicide contacts 458 may be provided on the main section, as shown in fig. 4 c.

Fig. 5a shows a simplified top view of another embodiment of a sensor 550. Fig. 5B to 5c show simplified cross-sectional views of the sensor along A-A 'and B-B'. FIG. 5d shows a simplified cross-sectional view along B-B' of an alternative embodiment of the sensor. The sensor is a CMOS compatible sensor. The sensor is similar to the sensor described in fig. 3a to 3d and fig. 4a to 4 d. Common elements may not be described or depicted in detail.

As shown, the sensor includes a sensor body having a first sensor segment 551 _P and a second sensor segment 551 _N. The first body segment includes a first main segment 553 _PM and a first lead segment 553 _PL; the second body segment includes a second main segment 553 _NM and a second lead segment 553 _NL. The sensor body may include an anchor point 552 within the base gap between the main segments. In one embodiment, the first anchor point and the second anchor point are disposed proximate opposite ends of the base gap 588. Other configurations of anchor points may also be useful. For example, a greater or lesser number of anchor points may be provided.

The sensor body contacts 555 electrically connect the first body section and the second body section. The sensor body contacts include a first sensor body via contact 557 _P and a second sensor body via contact 557 _N connected to the first body segment and the second body segment. The sensor body interconnect 556 interconnects the body via contacts. For example, the sensor body via contacts are closed loop via contacts. As shown, the sensor body contact occupies a central portion of the interface of the first and second main segments between the anchor points. The sensor contacts should have a minimum length to ensure sufficient mechanical stability of the individual sensor bodies. Anchor points may be provided to provide additional support. In case the sensor body contacts are long enough, the anchor points can be eliminated. It will be appreciated that the larger the sensor body contacts, the lower the contact resistance. Moreover, the larger the sensor body contact, the smaller the absorber. This reduces the absorption efficiency. As shown, the length of the sensor body is about 1/3 of the total length of the pedestal gap between anchor points. Other configurations of the sensor body contacts may also be useful. In some embodiments, as shown in fig. 5d, silicide contacts 558 are provided on the main segment to reduce contact resistance.

Unlike the embodiment of fig. 3 a-3 d, the main section includes an opening or gap 585. For example, the main section includes a main section gap. When patterned to form a sensor body, the first and second main segments may include a main segment gap pattern. For example, the first main segment is patterned to form a first main segment gap pattern having a first segment gap; the second main segment is patterned to form a second main segment gap pattern having a second segment gap. The first main segment gap pattern and the second main segment gap pattern may be similar. For example, the first and second sections have the same shape, except that one is flipped vertically and horizontally relative to the other.

The gap reduces or minimizes the heat capacity of the sensor body. An absorber may be provided for the sensor body. In one embodiment, in the case of a metal absorber, the sheet resistance should be configured to have an ambient sheet resistance to enhance or maximize IR absorption or reduce or minimize reflection. Other configurations of absorbers may also be useful.

In one embodiment, the gap pattern includes a plurality of slots or elongated openings along the first direction. As shown, the slot is in the x-direction. Alternatively, the slot may be in the second direction or y-direction. Other configurations that provide a gap pattern may also be useful. The pattern, in particular the size and spacing, should be chosen to improve absorption. For example, the spacing or gap or opening should be less than 1/4 wavelength to avoid affecting absorption. For example, the openings may be a matrix of openings, such as square, rectangular, circular, oval, other geometric shapes, or combinations thereof. For example, it may also comprise a combination of differently shaped openings, as well as a combination of elongated openings and isolated openings in the first direction or in the second direction. In a preferred embodiment, the gap pattern is configured to maximize the surface area of the openings or gaps within the body segment. The gap pattern should still provide the necessary mechanical stability.

Fig. 6a shows a simplified top view of another embodiment of a sensor 650. Fig. 6b shows a simplified cross-sectional view of the sensor along A-A'. FIG. 6c shows a simplified cross-sectional view along A-A' of an alternative embodiment of the sensor. The sensor is a CMOS compatible sensor. The sensor is similar to the sensor described in fig. 3a to 3d, fig. 4a to 4d and fig. 5a to 5 d. Common elements may not be described or depicted in detail.

As shown, the sensor includes a sensor body having a first sensor segment 651 _P and a second sensor segment 651 _N. The first body segment includes a first main segment 653 _PM and a first lead segment 653 _PL; the second body segment includes a second main segment 653 _NM and a second lead segment 653 _NL.

The sensor body contacts 655 electrically connect the first body section and the second body section. The sensor body contacts include a first sensor body via contact 657 _P and a second sensor body via contact 657 _N that are connected to the first body segment and the second body segment. Sensor body interconnect 656 interconnects the body via contacts. For example, the sensor body via contacts are closed loop via contacts. As shown, similar to fig. 4 a-4 c, the sensor body contacts occupy a major central portion of the interface of the first and second main sections. As shown, the length of the sensor body contacts occupy about 80-90% of the base gap at the interface of the main section. The mechanical stability provided by the body contact eliminates the need for an anchor point. Other configurations of the sensor body contacts may also be useful. In some embodiments, silicide contacts 658 are provided on the main segment to reduce contact resistance, as shown in fig. 6 c.

Similar to fig. 5 a-5 d, the main section includes an opening or gap 685. For example, the main section includes a main section gap. When patterned to form a sensor body, the first and second main segments may include a main segment gap pattern. For example, the first main segment is patterned to form a first main segment gap pattern having a first segment gap; the second main segment is patterned to form a second main segment gap pattern having a second segment gap. The first main segment gap pattern and the second main segment gap pattern may be similar. For example, the first and second sections have the same shape, except that one is flipped vertically and horizontally relative to the other.

The gap reduces or minimizes the heat capacity of the sensor body. An absorber may be provided to enhance IR absorption. In the case where the absorber is metal, it should be configured to have an ambient sheet resistance to optimize absorption or minimize reflection.

In one embodiment, the gap pattern includes a plurality of slots or elongated openings in the second direction. As shown, the slot is in the y-direction. Alternatively, the slot may be along the x-direction. Other configurations that provide a gap pattern may also be useful. For example, the openings may be a matrix of openings, such as square, rectangular, circular, oval, other geometric shapes, or combinations thereof. For example, combinations of differently shaped openings may be included, as well as combinations of elongated openings and isolated openings in the first direction or the second direction. The pattern (such as size and spacing) should be selected to improve absorption. For example, the spacing or gap or opening should be less than 1/4 wavelength to avoid affecting absorption. In a preferred embodiment, the gap pattern is configured to provide sufficient mechanical stability to keep the individual sensor bodies physically intact without affecting absorption and to maximize the surface area of the openings or gaps within the body segments.

FIG. 7a shows a simplified cross-sectional view along B-B' of one embodiment of a sensor. The sensor is similar to the sensor described in fig. 3a to 3d and fig. 4a to 4 d. Common elements may not be described or depicted in detail.

A portion of the illustrated sensor body includes a first main section 753 _PM and a second main section 753 _NM. The main section includes a base gap 788 separating them. The sensor body contact 755 electrically connects the first main section and the second main section. The sensor body contacts include a first sensor body via contact 757 _P and a second sensor body via contact 757 _N that are connected to the first main section and the second main section. The sensor body interconnect 756 interconnects the body via contacts. For example, the sensor body via contacts are closed loop via contacts. To reduce contact resistance, silicide contacts (not shown) may be provided on the main section.

In one embodiment, absorber 790 is disposed over the sensor body. As shown, the absorber is disposed above the main section of the sensor body. As previously discussed, the absorber may also be disposed over the lead segment of the sensor body. For example, the absorber is configured to absorb incident infrared radiation. The absorber may be a SiN layer. Other types of absorbers may also be useful. The absorber layer should resist the etchant of the second release process. The absorber thickness may be about 30-100nm. Other thicknesses may also be useful.

In one embodiment, a dielectric liner 791 may be disposed between the absorber and the sensor body. For example, the dielectric liner may be silicon oxide. Other types of dielectric liners may also be useful. A dielectric liner may be provided to reduce film stress and improve adhesion between the sensor body and the absorber layer. For example, a silicon oxide liner layer may reduce stress and improve adhesion between the polysilicon sensor body and the silicon nitride absorber layer. The dielectric liner and absorber may be referred to as an absorber stack. As shown, the absorber includes absorber studs to protect the sidewalls of the dielectric liner. For example, a dielectric liner is encapsulated within the absorber. This prevents the dielectric liner from being eroded during the release process that forms the separate sensor and lower sensor cavity. The stud may be formed by patterning a dielectric liner to form a stud trench. For example, a stud groove surrounds the main section and the lead section. For example, first and second stud grooves are formed for the first and second sensor body segments. An absorber is formed on the dielectric liner filling the stud trench and the top of the dielectric liner. The absorber stack is patterned to cover the patterned sensor body. For example, the absorber stack is patterned to cover the main section of the sensor body. As shown, the dielectric liner under the absorber above the pedestal gap 788 is removed during the release process.

FIG. 7B shows a simplified cross-sectional view along B-B' of another embodiment of a sensor. The sensor is similar to the sensor described in fig. 3a to 3d, fig. 4a to 4d and fig. 7 a. Common elements may not be described or depicted in detail.

The portion of the sensor body shown includes a first main section 753 _PM and a second main section 753 _NM that are electrically coupled by sensor body contacts 755. In one embodiment, absorber 790 is disposed over the sensor body. As shown, the absorber is embedded within the absorber protective laminate. In one embodiment, the absorber is embedded in an inner protective layer 792 that is encapsulated by an outer protective layer 796. In one embodiment, the inner and outer protective layers are dielectrics. The inner dielectric layer may be silicon oxide and the outer protective layer may be SiN. Other configurations of the protective absorber stack may also be useful. As for the absorber layer, it may be TiN. Other types of absorbers, such as NiCr, may also be useful. In the case of a metal absorber, its thickness can be adjusted so that the absorber has a sheet resistance that matches the ambient sheet resistance. As for the protective absorber stack, the thickness of the inner dielectric layer may be about 100nm, while the thickness of the outer protective layer may be about 50-100nm. Other thicknesses of the layers may also be useful.

To form the protected absorber stack, a first dielectric layer may be formed on the sensor body, followed by forming an absorber thereon. After the absorber is formed, it is patterned to define the absorber over the sensor segment. A second dielectric layer is formed over the absorber. This forms, for example, a dielectric absorber stack. The dielectric absorber stack may be patterned to form stud trenches, followed by the formation of a sensor protection layer. The sensor protection layer covers the stud trench and the surface of the dielectric absorber stack. The protected absorber stack is patterned to be located over the sensor body. As shown, the dielectric layer under the absorber above the base gap 788 is removed during the release process.

FIG. 8a shows a simplified cross-sectional view along B-B' of another embodiment of a sensor. The sensor is similar to the sensor described in fig. 3a to 3d, fig. 4a to 4d, fig. 5a to 5d, fig. 6a to 6d and fig. 7a to 7 b. Common elements may not be described or depicted in detail.

A portion of the sensor body is shown to include a first main section 853 _PM and a second main section 853 _NM that are electrically coupled by sensor body contacts 855. The main section includes a section gap 858.

In one embodiment, absorber 890 is disposed above the sensor body. As shown, the absorber is disposed above the main section of the sensor body. In one embodiment, a dielectric liner 891 may be disposed between the absorber and the sensor body. The dielectric liner and absorber may be referred to as a liner absorber stack. In one embodiment, the liner absorber stack is a conformal stack. For example, the liner absorber stack conforms to the topography of the sensor body. The liner absorber stack may be formed after the sensor body is defined. For example, the dielectric liner may be silicon oxide. For example, the dielectric liner is configured to reduce film stress and improve adhesion between the sensor body and the absorber layer. Other types of dielectric liners may also be useful.

As shown, the absorber includes absorber studs to protect the sidewalls of the dielectric liner above the sensor body. For example, a dielectric liner on the top surface of the sensor body is encapsulated within the absorber. This prevents the dielectric liner from being eroded during the release process that forms the separate sensor and lower sensor cavity. The studs may be formed by patterning a dielectric liner conformal to the sensor body to form first and second stud grooves of the first and second sensor body segments. An absorber is formed on the patterned dielectric liner to fill the stud trench and the top surface of the dielectric liner. The liner absorber stack is patterned to be disposed over the sensor body. As shown, the dielectric liner outside the absorber stud and below the absorber above the base gap 888 is removed during, for example, a second release process.

FIG. 8B shows a simplified cross-sectional view along B-B' of another embodiment of a sensor. The sensor is similar to the sensor described in fig. 3a to 3d, fig. 4a to 4d, fig. 5a to 5d, fig. 6a to 6d, fig. 7a to 7b and fig. 8 a. Common elements may not be described or depicted in detail.

In one embodiment, the protected absorber stack is disposed over the sensor body. The protected absorber stack conforms to the topography of the sensor body. As shown, the protected absorber stack is disposed over the sensor body. In one embodiment, the protected absorber stack includes an absorber 890 embedded in a dielectric layer 892 that is completely encapsulated by the sensor protective layer 896. For example, the dielectric layer is encapsulated by an upper and lower sensor protection layer and a sensor protection stud. In one embodiment, a dielectric liner 891 is disposed between the sensor body and the protected absorber stack.

To form the protected absorber stack, a dielectric liner is conformally formed over the sensor body. The dielectric liner is patterned to form a first or liner stud trench on the sensor body. The lower sensor protective layer is formed on the dielectric liner. The lower sensor protective layer fills the liner stud trench and the surface of the liner. After forming the lower sensor protection layer, a lower dielectric layer is formed thereon. For example, the lower dielectric layer fills the gaps between the segment gaps and covers the top surface of the lower sensor protection layer. The absorber is formed on the lower dielectric layer. The absorber is patterned to be located over the sensor body. An upper dielectric layer is formed over the lower dielectric layer and the absorber. The dielectric absorber stack is patterned to form second or upper stud trenches for the upper dielectric layer and the lower dielectric layer. An upper sensor protection layer is formed to fill the upper stud trench and cover the upper dielectric layer. The protected absorber stack and the dielectric liner are patterned to overlie the sensor body. As shown, the dielectric liner outside the lower stud and above the base gap 888 is removed during, for example, a second release process.

Fig. 9 a-9 q illustrate cross-sectional views of one embodiment of a process for forming an apparatus 900. For example, the device is similar to the device described in fig. 2a to 2 b. For example, the device includes a sensor region having a sensor, such as those described in fig. 3 a-3 d, 4 a-4 d, 5 a-5 d, 6 a-6 d, 7 a-7 b, and 8 a-8 b. Common elements may not be described or depicted in detail.

Referring to fig. 9a, a substrate 905 is provided. For example, the substrate may be a semiconductor substrate, such as a silicon substrate. Other types of substrates or wafers may also be useful. For example, the substrate may be a silicon germanium, gallium arsenide, or a Crystal On Insulator (COI) substrate, such as Silicon On Insulator (SOI). The substrate may be a doped substrate. For example, the substrate may be lightly doped with a p-type dopant. It may also be useful to provide the substrate with other types of dopants or dopant concentrations, as well as with undoped substrates. The substrate includes a top surface 905 _T and a bottom surface 905 _B. The top surface may be referred to as an active surface and the bottom surface may be referred to as an inactive surface.

As shown in fig. 9b, a substrate 905 is prepared with a first device region 904 and a second device region 906. The first region is a CMOS region and the second region is a MEMS region. The CMOS region is configured to include CMOS components and the MEMS region is configured to include MEMS components. For example, the MEMS component is a sensor. For example, the sensor may be a pyroelectric based infrared sensor, such as a thermopile sensor. Other types of MEMS components may also be useful.

In one embodiment, the lower sensor cavity 960 is formed in a sensor region of the substrate. The lower sensor cavity may be formed by etching the substrate using a mask. In one embodiment, the mask may be a patterned photoresist mask having openings corresponding to the lower sensor cavity. Alternatively, the mask may be a hard mask, such as silicon oxide, silicon nitride, or metal lines in the ILD layer, that is patterned with a photoresist mask to include openings corresponding to the lower sensor cavities. An anisotropic etch such as a Reactive Ion Etch (RIE) etches the substrate to form a lower sensor cavity.

A reflector 962 is formed at the bottom of the lower sensor cavity. In one embodiment, the reflector is a metal silicide layer formed at the bottom of the lower sensor cavity. The metal silicide reflector may be a TiSi _x、WSi_x or AlSi _x reflector. Other types of metal silicide reflectors may also be useful.

To form the reflector, a conductive metal layer is formed on the substrate. A conductive metal layer may line the surface of the substrate and the bottom of the lower sensor cavity. In one embodiment, a mask for forming the substrate is reserved. Thus, the conductive metal layer covers the mask on the surface of the substrate. In the case of a photoresist mask, the conductive metal layer is removed after it is deposited. This removes the conductive metal layer above the mask, leaving a portion of the conductive metal layer covering the bottom of the underlying sensor cavity. Annealing is performed to cause a reaction between the conductive metal and the silicon substrate at the bottom of the cavity, thereby forming a metal silicide layer. In the case of a hard mask, the metal layer over the substrate is not removed. The hard mask prevents reaction with the substrate. Unreacted metal and hard mask are removed after the annealing process. Removal of unreacted metal and hard mask may be achieved using a first wet etch.

Alternative types of reflectors may also be formed at the bottom of the lower sensor cavity. In another embodiment, the reflector is a doped region at the bottom of the cavity. For example, implantation may be performed using a mask that forms the lower sensor cavity. The implant injects reflector dopants to form a reflector at the bottom of the lower sensor cavity. The reflector dopant may be n-type or p-type. The dopant concentration of the reflector is selected accordingly so as to reflect infrared radiation at a desired degree of reflectivity. For example, the dopant concentration of the doped reflector layer may be about 10 ²¹ dopants/cm ³. The conductive nature of the surface of the doped region is due to the high concentration of the applied dopant, thereby being able to reflect incoming infrared radiation. After implanting the dopant, the implantation mask is removed.

In other embodiments, the reflector may be a non-conductive reflector, such as a photonic crystal reflector. The photonic crystal layer is formed, for example, by etching the surface of the underlying sensor cavity. The photonic crystal layer may include a grating pattern configured to reflect incident infrared radiation. For example, different grating patterns of different depths may be etched from the surface of the photonic crystal layer to adjust the wavelength and nature of the reflected infrared radiation. The photonic crystal layer may include a grating pattern configured to reflect incident radiation. It may also be useful to form other types of reflectors.

Referring to fig. 9d, after forming the reflector, a reflector protective liner 912 is formed on the substrate. For example, a protective liner is used to protect the reflector from an etchant (such as XeF ₂) that is used to form the lower sensor cavity during release, but is structured and etched away at the CMOS area. The protective liner may be a silicon oxide liner. Other types of protective liners may also be used. The protective liner may be formed by, for example, chemical Vapor Deposition (CVD). Other formation techniques or other types of protective liners may also be useful. A protective liner lines the sides and bottom of the substrate and lower sensor cavity, covering the reflector. For example, the protective liner may have a thickness of about 150-200nm. Other thicknesses may also be useful.

A sacrificial layer 964 is formed over the substrate as shown in fig. 9 e. The sacrificial layer covers the substrate and fills the lower sensor cavity. In one embodiment, the sacrificial layer is a polysilicon layer. Other types of sacrificial materials may also be used for the sacrificial layer. The sacrificial layer may be formed by CVD. Excess sacrificial material over the substrate is removed. For example, polishing such as Chemical Mechanical Polishing (CMP) is employed to remove excess sacrificial material. In one embodiment, the CMP removes excess sacrificial material. For example, the protective liner acts as a CMP stop layer. After the CMP process, the protective liner is removed. The process utilizes a sacrificial layer in the substrate and cavity to form a planar or substantially planar top surface. It may also be useful to provide any other technique for forming a planar surface between the sacrificial fill and the substrate surface. For example, a fabrication without CMP would require performing a structured and isotropic etch-back process to planarize the surface, which may rely on RIE or deep RIE etch-back.

A dielectric layer 914 is formed over the substrate as shown in fig. 9 f. The dielectric may be a silicon oxide layer. Other types of dielectric layers may also be formed. The dielectric layer is patterned so that it remains over the lower sensor cavity with the sacrificial fill. The dielectric layer protects the sensor region while the CMOS region is being processed. The dielectric layer defines the top of the lower sensor cavity and serves as a membrane for the sensor in the sensor area. The dielectric layer may be formed by CVD and patterned using a mask and etch process. Furthermore, the dielectric layer may serve as a sacrificial support upon which the sensor is formed. For example, the dielectric layer or sensor support is removed during the release process. In one embodiment, the sensor support is removed during a second release process that forms an independent sensor.

Referring to fig. 9g, the cmos area is processed. For example, a front end of line (FEOL) process is performed on the substrate. The CMOS region of the substrate is processed to include a first transistor region and a second transistor region 920. In one embodiment, the first and second transistor wells 921 are formed in the first and second transistor regions. The first transistor well may be a p-type well for an n-type MOS transistor and the second transistor well may be an n-type well for a p-type MOS transistor. For example, the well may be formed by ion implantation using an implantation mask. The implantation mask may be a photoresist implantation mask patterned to provide openings for the implantation regions. Different implantation processes are used to form the p-type well and the n-type well.

As shown, isolation regions 980 are formed on the substrate to isolate different regions of the substrate. For example, isolation regions may also be provided for the well contact regions. For example, the isolation region is a Field Oxide (FOX) isolation region. The FOX region may be formed by performing selective thermal oxidation on the substrate using a nitride mask. Other types of isolation regions may also be useful. For example, the isolation region may be a Shallow Trench Isolation (STI) region. STI regions are trenches formed in the substrate and are filled with a dielectric material, such as silicon oxide. The STI region may have a top surface coplanar with a substrate produced by CMP. In one embodiment, the STI regions are formed prior to the dopant implantation so as not to be affected by the silicon doping on its growth.

A gate layer is formed on a substrate. In one embodiment, the gate layer includes a gate dielectric layer and a gate electrode layer. The gate dielectric layer may be a thermal oxide layer and the gate electrode layer may be a polysilicon layer. The gate electrode layer may be formed by CVD. For example, the gate electrode layer covers the substrate in the CMOS region and the sensor region. In one embodiment, the gate layer is patterned to form gates 923 in the transistor region. For example, the gate layer is patterned to form a gate in the CMOS region and removed in the sensor region. Patterning of the gate layer may be achieved using masking and etching techniques. The gate layer is patterned by RIE, for example, using a patterned resist mask. The gate includes a gate electrode 923 over a gate dielectric 913. Other processes or process configurations may also be employed to form the gate.

In fig. 9h, the MEMS area is machined. For example, the CMOS region is masked, protecting it from the processing of the MEMS region. A hard mask layer such as a silicon oxide layer or a silicon nitride layer may be employed. The hard mask layer may be patterned to expose the sensor region, thereby leaving the CMOS region protected. The hard mask layer may be used as an etch stop layer. Other types of hard mask layers may also be useful. The hard mask layer enables processing of the MEMS region while protecting the CMOS region.

In one embodiment, the sensor body 950 is formed on a dielectric layer over the filled lower sensor cavity in the MEMS region. For example, a sensor body layer (such as polysilicon) is formed. The sensor body layer is patterned to form a sensor body, such as those previously described. Other types of sensor body layers may also be useful. For example, the sensor body layer may be silicon germanium (SiGe), gallium nitride (GaN), or a 2D material, such as graphene, black phosphorus, or molybdenum sulfide. As shown, the sensor body includes a gap or space 954, as previously described, to facilitate a subsequently performed release process. Other techniques or processes for forming the sensor body may also be useful. After the sensor body is formed, the mask protecting the CMOS area is removed.

As described, the gate and transistor gates are formed using different processes. In other embodiments, the gate and the sensor body may be formed in the same process. For example, a gate layer is deposited over the CMOS region and the sensor region. The same etch mask can be used to pattern the gate layer to form the gate in the transistor region and the sensor body in the sensor region. For example, the gate electrode and the sensor body are formed from the same gate electrode layer and patterned using the same etching process.

Source/drain (S/D) regions 924 _1-2 are formed adjacent to the gate as shown in fig. 9 i. The S/D regions are heavily doped regions. For example, the first transistor includes heavily doped n-type S/D regions, and the second transistor includes p-type S/D regions. Using an implant mask, such as a photoresist mask, different implants may be used to form different types of S/D regions. After implantation, the implantation mask is removed.

In one embodiment, a lightly doped extension region is formed adjacent to the gate. A p-type lightly doped extension region is formed adjacent to the gate of the p-type transistor and an n-type lightly doped extension region is formed adjacent to the gate of the n-type transistor. Dielectric sidewall spacers may be formed on the sidewalls of the gate to facilitate the formation of lightly doped extension regions. When forming gate sidewall spacers, spacers may also be formed on the dielectric layer or sensor support 914. After forming the spacers, lightly doped extension regions are formed. Using an implant mask, such as a photoresist mask, different implants may be used to form different types of lightly doped extension regions. After implantation, the implantation mask is removed.

After forming the extension regions, a spacer dielectric layer is formed on the substrate. The spacer dielectric layer may be a silicon oxide layer. Other types of spacer dielectric layers may also be useful. An anisotropic etch is performed to remove horizontal portions of the spacer dielectric layer and leave spacers on the sidewalls of the gate. A p-type S/D region is formed adjacent to the gate of the p-type transistor and an n-type S/D region is formed adjacent to the gate of the n-type transistor. Using an implant mask, such as a photoresist mask, different implants may be used to form different types of S/D regions.

After the S/D regions are formed, a sensor implantation process may be performed. For example, dopants are implanted to form n-doped and p-doped sensor segments of the sensor body. The implant may dope the sensor segment to adjust the sensor body to have an ambient sheet resistance to also act as an absorber. Different implantation processes may be employed for the n-doped sensor segment and the p-doped sensor segment.

As noted, the implant used to form the S/D regions is different from the implant used to form the sensor. For example, the S/D implant mask protects the sensor during S/D implant and the sensor implant mask protects the transistor during sensor implant. In alternative embodiments, implants for forming S/D regions of the transistor may be integrated into the process for forming the segments of the sensor body. For example, the p-type sensor segment or the n-type sensor segment is doped with the same implantation process as the p-type S/D region or the n-type S/D region, or the body layer may be the same as the gate electrode layer. Other configurations of forming the sensor body and S/D regions may also be useful.

Metal silicide contacts may be formed on the substrate. For example, metal silicide contacts may be formed on the S/D regions, gate, well contacts, and sensor via contact regions and sensor terminal contact regions on the sensor body. A metal layer such as Ti, W, co or Al may be deposited on the substrate and annealed to cause a reaction between the metal and silicon to form a metal silicide contact. Unreacted metal is removed, such as by wet etching, leaving behind metal silicide contacts. In other embodiments, the metal silicide contacts of the CMOS region and the sensor region may be different processes.

In some embodiments, the absorber is formed on the sensor body after the sensor body is formed. The absorber layer may comprise an absorber protective layer or layer stack as described for example in fig. 7a to 7b and fig. 8a to 8 b. It may also be useful to form other types of absorbers and absorber protective layers or laminates.

In fig. 9j, a first dielectric layer 972 is formed over the substrate. In one embodiment, the dielectric layer covers the CMOS region and the sensor region. For example, a dielectric layer covers the transistor and MEMS structure. The dielectric layer serves as a contact level (C0 dielectric) or pre-metal interlayer dielectric (ILD) layer. The ILD layer may be a silicon oxide layer formed by CVD. Other types of dielectric layers may also be useful. For example, the ILD layer may be a dielectric stack comprising a plurality of dielectric layers, such as BPSG, PETEOS, siON and PECVD oxide. Other configurations of ILD layers or stacks may also be useful. A polishing process, such as CMP, may be performed to create a planar top surface of the ILD layer. The planar top surface is located above the sensor and the transistor. It may also be useful to provide any other planarization technique, such as spin-on glass (SOG), to fill the gap or planarize the surface of the substrate.

Referring to fig. 9k, the process continues to form via contacts 923 in the ILD layer. The via contacts are coupled to the underlying contact areas. For example, via contacts are formed to connect to the S/D regions in the CMOS region, the gate and well contacts, and the sensor via contact region and the sensor terminal via contact region of the sensor body in the MEMS region. Further, via contacts are formed in the BEOL protection wall regions. In one embodiment, the protection wall region surrounds the sensor region and protects the BEOL dielectric layer from damage within the CMOS region during the release process. In one embodiment, the sensor via contacts, the sensor terminal via contacts, and the BEOL protection wall sensor via contacts are closed loop contacts. Other configurations of contacts may also be useful.

Contacts are formed, for example, by single damascene techniques. Single damascene techniques include forming vias, filling the vias with a contact layer, and polishing (such as CMP) to remove excess contact material. It may also be useful to form contacts using other techniques.

In fig. 9l, the process continues to form BEOL dielectric layer 970. For example, a first metal level (M1) forming a first IMD level and via levels and metal levels of additional IMD level 974. As discussed, the via level includes via contacts 973 and the metal level includes metal lines 977. The metal lines and vias form the interconnections of the device. As shown, the BEOL dielectric includes 2 IMD levels and a passivation stack over the highest metal level. For example, BEOL dielectrics include the M1, V1, M2, V2, and M3 metal levels and via levels of IMD levels (M3 above IMD1, IMD2, and V2). BEOL dielectric layers are formed over ILD levels with C0 or metal front contacts. Other configurations of IMD levels or other numbers of IMD levels may be provided for the BEOL dielectric. As previously discussed, ILD contacts and C0 contacts may be considered to be formed as part of FEOL processing, and IMD levels and other levels above may be considered to be formed as part of BEOL processing.

A passivation layer is formed over the uppermost metal level or pad level. For example, a passivation layer is formed over M3 serving as a pad level. For example, the passivation layer is part of the BEOL dielectric layer. In one embodiment, the passivation layer is a passivation stack PS having a plurality of passivation layers. In one embodiment, the passivation stack includes a first passivation dielectric layer 976, a second passivation dielectric layer 978, and a third passivation dielectric layer 979. The passivation stack is configured to protect the BEOL from damage during the release process. For example, the second passivation layer protects the BEOL dielectric during a second release process that removes the third passivation layer. In one embodiment, the passivation stack comprises a silicon oxide/silicon nitride/silicon oxide stack. For example, the first passivation layer is a silicon oxide layer, the second passivation layer is a silicon nitride layer, and the third passivation layer is a silicon oxide layer. Other configurations of the passivation stack may also be useful. The passivation layer may be formed by CVD.

In one embodiment, the BEOL dielectric layer includes BEOL protection walls 981 surrounding the sensor region. BEOL protection walls are formed with via contacts and metal lines at the metal level and via level (including the C0 level). In some embodiments, the BEOL protection wall may also include undoped polysilicon, such as polysilicon used to form gates. The BEOL protection wall is configured to prevent BEOL dielectric damage within the active CMOS area during the release process. The BEOL protection wall is also used to define a sensor area, thereby enabling a release process to be performed. For example, the BEOL protection wall prevents etchant, particularly etchant from the second release process, from penetrating the BEOL dielectric in the active CMOS area. For example, the active CMOS area is an area outside the BEOL protection wall and includes active or functional CMOS interconnect features. In one embodiment, the BEOL protection wall comprises a double wall configuration having wall discontinuities to accommodate connections. The dual wall configuration extends the etchant path from the sensor region to the BEOL dielectric in the active CMOS region. Preferably, the double-wall configuration maximizes the etchant path from the sensor region to the BEOL dielectric in the active CMOS region.

Referring to fig. 9m, the process continues to define an upper sensor cavity in the BEOL dielectric. In one embodiment, a patterned etch mask is provided over the BEOL dielectric. For example, the etch mask is a photoresist mask. The mask is exposed and developed to form openings corresponding to the sensor regions and pad openings 976. An isotropic etch, such as RIE, is performed. Other types of etching processes may also be useful. In one embodiment, the pad openings and the sensor openings are formed in different etching processes due to their thickness therebetween. For example, different etches and etch masks are used to form the pad openings and the sensor openings. For example, etching is selective to metals. For example, etching removes materials other than metals. As shown, the pad openings and the upper sensor cavity are defined in the BEOL dielectric. Since the pattern of M1 metal over the sensor is used as a secondary etch or hard mask, the etch also forms release openings 954 corresponding to the gaps of the sensor body.

As shown in fig. 9n, the M1 metal in the sensor region is patterned. In one embodiment, the M1 metal is patterned to form the interconnects of the sensor body contacts 955. For example, an interconnect connecting the first sensor body segment and the second sensor body segment together is formed during the patterning process. Patterning the M1 metal in the sensor region to form the sensor body contacts may be a self-aligned RIE etch. For example, the same mask used to form the sensor openings may also be used, except that the chemical reaction is to remove the M1 metal. In one embodiment, M2 in the sensor region is used as a hard mask over M1 in the sensor region to form the sensor body contacts. For example, the M2 metal hard mask is etched away and the M1 metal in the sensor region is patterned to form the sensor body contacts. This completes the formation of the sensor body contacts. After which the mask is removed.

The process continues to perform the first release of the dual release process. The first release process removes the sacrificial fill in the lower cavity. This forms the lower sensor cavity 960. In one embodiment, a dry etch is performed to remove the sacrificial fill. The etchant etches the sacrificial layer at a high etch rate compared to the metal and dielectric materials of the BEOL dielectric, protective liner, and sensor support. For example, etchants have high selectivity to metals and silicon oxides. In one embodiment, a xenon difluoride (XeF ₂) etchant is used to perform the first release process. In another embodiment, an isotropic sulfur hexafluoride (SF ₆) etchant is used as a replacement etchant for XeF ₂. Other types of etchants or etching processes may also be useful.

In fig. 9p, a second release of the dual release procedure is performed. The second release removes the dielectric material that encapsulates the sensor to form a stand-alone sensor. In one embodiment, a dry etch is performed to remove the dielectric material that encapsulates the sensor. Dry etching removes silicon oxide at a high etch rate compared to metal, silicon, and silicon nitride. For example, etchants have high selectivity to metals, silicon, and silicon nitride. The second release process also removes the silicon oxide passivation layer and protective liner lining the trench walls and bottom and attacks the BEOL dielectric in the sensor region. However, the BEOL protection walls prevent erosion of the BEOL dielectric in the active CMOS region. In one embodiment, the second release employs a Vapor HF (VHP) etchant. Other types of etchants may also be useful.

Referring to fig. 9q, the process continues. As shown, cap 990 is bonded to a substrate. For example, a seal ring 982 is employed to bond the cap to the BEOL dielectric. The seal ring may include a cap portion and a substrate portion. For example, a cap seal ring may be disposed on the cap in the cap seal region, and a substrate seal ring may be disposed on top of the BEOL dielectric in the substrate seal region. The cap seal ring and the substrate seal ring may be metal seal rings. The metal seal ring may comprise a metal seal ring stack having a plurality of metal layers. Other configurations of seal rings or other types of seal rings may also be useful.

In another embodiment, the substrate portion of the seal ring may be formed of the uppermost metal level. For example, the metal pattern of the uppermost metal level may include a substrate portion of the seal ring. The substrate portion of the seal ring is exposed by patterning the passivation stack. For example, the passivation stack may be patterned to form a seal ring opening, exposing a substrate portion of the seal ring and the pad opening to expose the bond pad.

The caps may be bonded using, for example, heat pressing. For example, the cap seal ring and the substrate seal ring are bonded together by thermocompression. The hot pressing may be performed at the wafer level. For example, wafer level vacuum packaging may be employed to form the cap. The caps are bonded before dicing the wafer to separate the devices.

In one embodiment, the cap is formed of a material transparent to infrared radiation. For example, the cap can transmit infrared radiation to the sensor. For example, the cap may be a silicon cap. Other types of materials that transmit infrared radiation may also be useful.

In one embodiment, the cap includes an anti-reflective region 944. The anti-reflection region facilitates transmission of infrared radiation through the cap. The anti-reflection region may include a bottom grating (not shown) on the inner (bottom) surface of the cap and a top grating (not shown) on the outer (top) surface of the cap. The grating may have a moth-eye grating pattern or structure to facilitate transmission of infrared radiation. Other grating patterns of the grating may also be useful. Other types of anti-reflective regions may also be useful.

In some embodiments, the anti-reflective region includes an anti-reflective coating disposed on the front and rear sides of the cap. Alternatively, materials having different reflectivities may be deposited on the surface of the anti-reflective regions. For example, the material for the anti-reflective coating may be zinc sulfide or germanium (Ge) and deposited in the same manner as the moth-eye grating pattern or structure. It may also be useful to provide any other materials and deposition techniques for the anti-reflective coating.

A getter (not shown) may be provided on the inner surface of the cap. For example, the bottom surface of the cap may include a recess 941 over the CMOS area. The getter may be disposed in a recess on the bottom surface of the cap. The getter absorbs moisture and outgassing within the packaged device. For example, the getter may be zirconium alloy, titanium (Ti), nickel (Ni), aluminum (Al), barium (Ba), or magnesium (Mg). Other types of getter materials, such as rare earth elements including cerium (Ce) or lanthanum (La), may also be useful. The getter facilitates maintaining a vacuum, thereby improving reliability. Other configurations of caps may also be useful. After the wafer level packaging is completed, the wafer is diced to singulate the wafer into individual device packages.

Fig. 10 a-10 b show top views of layouts of sensor areas corresponding to different metal levels, showing etchant flow paths during the second release of the dual release process. In particular, fig. 10a shows the layout of M1, and fig. 10b shows the layout of M2 and above. As for M3, it is not shown. M3 may be similar to M2 or may be different. For example, the discontinuity in M3 may be provided at a location different from M2. The sensor area includes a sensor 1050. The sensor areas and sensors are similar to those previously described. Common elements may not be described or depicted in detail.

As shown, the sensor area includes a sensor 1050. The sensor includes a sensor body first body section and a second body section. The first body section includes a first main section 1053 _PM and a first lead section 1053 _PL, and the second body section includes a second main section 1053 _NM and a second lead section 1053 _NL. At one end of the first and second lead segments, first and second terminal via contacts 1032, _P, 1032 _N are provided. For example, a first terminal via contact is disposed near one end of the first lead segment and a second terminal via contact is disposed near one end of the second lead segment. The first sensor via contact 1057 _P and the second sensor via contact 1057 _N are disposed near the interface of the first main section and the second main section.

In one embodiment, the via contact is a closed loop via contact. Providing a closed loop via contact improves the mechanical stability of the individual sensor after the second release process. Other types of via contacts may also be useful. For example, the terminal via contacts and the sensor via contacts may be disposed within a pre-metal dielectric level or a C0 dielectric level. For example, the via contact provides an interconnect with an interconnect on the first metal (M1) dielectric level.

In one embodiment, the BEOL protection wall 1081 surrounds the sensor region. As shown, the protective wall is a rectangular protective wall. Other shapes of the protective wall may also be useful. BEOL protection walls include metal level and via level via contacts and metal lines or interconnects of BEOL dielectrics (including C0 level). The BEOL protection wall may also include polysilicon (e.g., gate layer) patterned on the surface of the substrate. The BEOL protection wall is configured to prevent BEOL dielectric damage within the active CMOS area during the release process. For example, the BEOL protection wall prevents etchant from the release process from penetrating the BEOL dielectric within the active CMOS area.

As shown, sensor terminal interconnect 1030 is coupled to the sensor via contacts, and sensor contact interconnect 1056 couples the sensor via contacts together. In one embodiment, first sensor terminal interconnect 1030 _P is connected to a first sensor via contact; the second sensor terminal interconnect 1030 _N is connected to a second sensor via contact. For example, the sensor terminal interconnect and the sensor contact interconnect are M1 interconnects.

In one embodiment, the BEOL protection wall comprises a double wall configuration. As shown, the BEOL protection walls include an inner protection wall 1081 _I and an outer protection wall 1081 _O. The dual wall configuration extends the etchant path from the sensor region to the BEOL dielectric in the active CMOS region. Preferably, the double-wall configuration maximizes the etchant path from the sensor region to the BEOL dielectric in the active CMOS region. Other configurations of BEOL protection walls may also be useful.

Discontinuities are provided in the BEOL protection wall. In one embodiment, discontinuities are provided to accommodate the metal interconnections of the sensor. Preferably, discontinuities are provided to accommodate the metal interconnections of the sensor and extend the etchant path of the release process to the CMOS active area as long as possible.

In one embodiment, the C0, M1, and V1 levels of the outer protective wall include terminal interconnect discontinuities 1083 _O to accommodate sensor terminal interconnects 1030. The C0, M1, and V1 levels of the protective walls include a first outer wall terminal interconnect discontinuity 1083 _OP to accommodate a first sensor terminal interconnect and a second outer wall terminal interconnect discontinuity 1083 _ON to accommodate a second sensor terminal interconnect. For example, the C0 contacts 1033 _C0, M1 interconnect 1034 _M1, and V1 of the outer protective wall include a first outer wall terminal interconnect discontinuity and a second outer wall terminal interconnect discontinuity. The outer wall terminal interconnection discontinuities avoid shorting of the sensor terminals. As for the layers above V1, the outer protective wall does not have any discontinuities.

In one embodiment, the sensor terminal interconnect is part of an M1 metal layer. For example, the first sensor terminal interconnect of the first lead segment of the first body segment is part of the M1 metal layer and the second sensor terminal interconnect of the second lead segment of the second body segment is part of the M1 metal layer. Other configurations of sensor terminal interconnections may also be useful.

In one embodiment, the inner protective wall 1081 _i does not include a first terminal interconnect discontinuity and a second terminal interconnect discontinuity as does the outer protective wall. For example, the inner protective wall does not have an inner wall discontinuity at the location of the outer wall terminal interconnection discontinuity. Instead, the inner protective wall includes first and second inner wall discontinuities 1083 _i at other portions of the inner protective wall to avoid shorting the first and second terminal interconnects. For example, each layer of the inner protective wall includes a first inner wall discontinuity and a second inner wall discontinuity. The first and second inner wall discontinuities avoid shorting of the first and second terminal interconnects. In one embodiment, the inner wall discontinuity is configured to provide a long travel path for the etchant of the dual release process to the active CMOS area of the BEOL dielectric. Preferably, the inner wall discontinuity provides the longest possible travel path for the etchant of the dual release process to the active CMOS area of the BEOL dielectric.

As shown, the inner protective wall includes a first inner protective wall break and a second inner protective wall break. The first inner protective wall discontinuity and the second inner protective wall discontinuity are disposed at opposite diagonal portions of the inner protective wall. For example, the first inner protective wall discontinuity and the second inner protective wall discontinuity are disposed at opposite diagonal portions of all levels. The opposite diagonal portions are discontinuous away from the outer protection wall terminal interconnection. For example, the first inner protective wall break and the second inner protective wall break are positioned away from the first outer protective wall terminal interconnect break and the second outer protective wall terminal interconnect break. Preferably, the first inner protection wall discontinuity and the second inner protection wall discontinuity are located as far as possible from the first outer protection wall terminal interconnection discontinuity and the second outer protection wall terminal interconnection discontinuity.

In one embodiment, the M1 terminal interconnect is coupled to the C0 via contact. The first inner wall discontinuity and the second inner wall discontinuity enable a long etchant path for the second release process to prevent damage to the active CMOS BEOL dielectric, as indicated by the arrows. This prevents the etchant from damaging the BEOL dielectric in the active CMOS area from the second release process.

Fig. 11a to 11b show simplified cross-sectional views along A-A' of fig. 10a to 10b of the sensor area of the device after a first release process and after a second release process. Common elements may not be described or depicted in detail.

Referring to fig. 11a, the device is shown after a first release procedure. The first release process is selective to BEOL dielectric 1170 and the metal of the M1 metal level. For example, the first release process removes the lower sensor cavity filler, leaving behind the protective liner 1112, the dielectric layer that encapsulates the sensor, and the upper passivation layer 1179.

In fig. 11b, a second release procedure is performed. The second release process removes dielectric material such as silicon oxide at a high etch rate compared to silicon, silicon nitride, polysilicon, and metal. For example, the second release process removes the dielectric material that encapsulates the sensor, thereby forming an independent sensor. In addition, the second release process removes the protective liner lining the lower sensor cavity and attacks the BEOL dielectric 1170.BEOL protection wall 1181 prevents the etchant of the second release process from damaging the BEOL dielectric in the active CMOS area.

Fig. 12a to 12B show simplified cross-sectional views along B-B' of fig. 10a to 10B of the sensor area of the device before and after the first release process and after the second release process. Common elements may not be described or depicted in detail.

Referring to fig. 12a, the device is shown after a first release procedure. The first release process is selective to BEOL dielectric 1270 and metal of the M1 metal level. For example, the first release process removes the lower sensor cavity filler, leaving behind the protective liner 1212, the dielectric layer encapsulating the sensor, and the upper passivation layer 1279. As shown, the M1 level of terminal interconnects are connected to terminal via contacts 1232, which are connected to the sensor 1250.

In fig. 12b, a second release procedure is performed. As discussed, the second release process removes dielectric material such as silicon oxide at a high etch rate compared to silicon, silicon nitride, polysilicon, and metal. The second release process removes the dielectric material that encapsulates the sensor, thereby forming a stand-alone sensor. In addition, the second release process removes the protective liner lining the lower sensor cavity, the upper passivation layer of the protective stack, and attacks the BEOL dielectric 1270.BEOL protection wall 1281 prevents the etchant of the second release process from damaging the BEOL dielectric in the active CMOS area.

Fig. 13a to 13b show simplified cross-sectional views along C-C' of fig. 10a to 10b of the sensor area of the device before and after the first release process and after the second release process. Common elements may not be described or depicted in detail.

Referring to fig. 13a, the device is shown after a first release procedure. For example, the first release process removes the lower sensor cavity fill, leaving behind a protective liner, dielectric layer encapsulating the sensor, and upper passivation layer 1379.

As shown in fig. 13b, a second release procedure is performed. The second release process removes the dielectric material that encapsulates the sensor, thereby forming a stand-alone sensor. In addition, the second release process removes the protective liner lining the lower sensor cavity, the upper passivation layer of the protective stack, and attacks the BEOL dielectric. The BEOL protection wall prevents the etchant of the second release process from damaging the BEOL dielectric in the active CMOS area.

Fig. 14 shows graphs of thermal conductivity, temperature increase, and response speed for different thermal sensors. In particular, the first sensor and the second sensor are tested. The first sensor comprises a first variant and a second variant (version ii), the first variant being non-independent (version i) in that only one release procedure is performed; this second variant is independent due to the double release procedure. Likewise, the second sensor is tested with the first variant (dependent or version i ') and the second variant (independent or version ii'). It is clear from the test data that the independent version has a higher temperature increment and a shorter response time than the corresponding non-independent version. This proves that the stand-alone sensor is more efficient than the non-stand-alone sensor.

The present disclosure may be embodied in other specific forms without departing from its spirit or essential characteristics. The foregoing embodiments are, therefore, to be considered in all respects illustrative rather than limiting on the invention described herein. The scope of the invention is, therefore, indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are intended to be embraced therein.

Claims

1. An apparatus, the apparatus comprising:

A substrate, the substrate comprising

A Complementary Metal Oxide Semiconductor (CMOS) region, wherein the CMOS region includes a transistor region having a transistor, and

A microelectromechanical system (MEMS) region, wherein the MEMS region comprises

The lower part of the sensor cavity is provided with a plurality of sensors,

A stand-alone sensor disposed above the lower sensor cavity, wherein the stand-alone sensor has no supporting dielectric between the sensor and the lower sensor cavity, wherein the stand-alone sensor improves response time and sensor sensitivity;

a back end of line (BEOL) dielectric disposed on the substrate, the dielectric having

A pre-metal dielectric layer having a pre-metal contact, and

A plurality of inter-metal dielectric (IMD) layers disposed over the pre-metal dielectric layer, wherein the IMD layers include a metal level and a via level, the metal level including a metal line and the via level including a via contact to interconnect components of the device via the pre-metal dielectric layer.

2. The apparatus of claim 1, wherein the stand-alone sensor comprises an infrared imaging sensor.

3. The apparatus of claim 2, wherein the standalone infrared imaging sensor comprises a sensor body comprising:

a first body segment, the first body segment being a first polarity type body segment;

a second body segment, the second body segment being a second polarity type body segment;

A body segment gap separating the first body segment and the second body segment, the body segment gap disposed between adjacent edges of the first body segment and the second body segment; and

A sensor body contact electrically coupling the first body section and the second body section.

4. The apparatus of claim 3, wherein the sensor body contact comprises:

A sensor body contact plate disposed above the sensor body gap;

the first sensor body through hole contact and the second sensor body through hole contact, the first through hole contact and the second through hole contact are disposed between the first body section and the second body section and the sensor body contact plate.

5. The apparatus of claim 2, wherein the standalone infrared imaging sensor comprises a sensor body comprising:

a first body segment that is a first polarity type body segment, wherein the first body segment includes

The first body section is configured to be coupled to the first body section,

A first lead body segment extending from the first main body segment, wherein one end of the first lead body segment serves as a first sensor terminal;

a second body segment, the second body segment being a second polarity type body segment, wherein the second body segment comprises

The second body section is configured to be coupled to the first body section,

A second lead body segment extending from the first main body segment, wherein one end of the second lead body segment serves as the second sensor terminal;

A body segment gap separating the first and second body segments, the body segment gap disposed between adjacent edges of the first and second body segments; and

6. The apparatus of claim 5, wherein the sensor body contact comprises:

A sensor body contact plate disposed above the sensor body gap;

7. The apparatus of claim 6, wherein the first and second body via contacts comprise ring contacts, wherein a ring contact comprises an electrically conductive outer ring filled with a dielectric filler, the ring contacts providing mechanical support for the stand-alone sensor.

8. The apparatus of claim 1, wherein the pre-metal dielectric layer and the BEOL dielectric comprise a protective wall surrounding the MEMS region, the protective wall configured to protect the pre-metal dielectric layer and the BEOL dielectric in the CMOS region from damage by an etchant during a second release process that forms the stand-alone sensor.

9. The apparatus of claim 8, wherein the protection wall is a double protection comprising:

an inner protective wall; and

An outer protective wall, wherein the inner protective wall and the outer protective wall are configured with an inner protective wall opening and an outer protective wall opening, the inner protective wall opening and the outer protective wall opening being configured to

Providing electrical connection to the individual sensors without causing short circuits, and

An etchant flow path of the second released etchant is extended to prevent damage to the pre-metal dielectric layer and the BEOL dielectric in the CMOS region.

10. The device of claim 2, wherein the sensor body is doped to create an ambient sheet resistance to act as an absorber.

11. The apparatus of claim 10, wherein:

the bottom of the lower sensor cavity includes a reflector; and

The depth of the absorber, reflector and cavity are part of an interference absorbing system to improve the absorption of infrared radiation.

12. A method for forming a device, the method comprising:

Providing a substrate, the substrate being prepared with Complementary Metal Oxide Semiconductor (CMOS) regions and microelectromechanical system (MEMS) regions;

Processing the CMOS region, wherein processing the CMOS region includes forming transistors of a first type and a second type in a first transistor region and a second transistor region of the CMOS region;

processing the MEMS region, wherein processing the MEMS region comprises

A lower sensor cavity trench filled with a cavity trench filler is formed,

A sensor supporting dielectric layer is formed over the lower sensor cavity on top of the trench fill,

Forming a sensor on the sensor support dielectric layer;

Forming a back end of line (BEOL) dielectric disposed on the substrate, the dielectric having

A pre-metal dielectric layer having a pre-metal contact, and

A plurality of inter-metal dielectric (IMD) layers having a metal level and a via level, the metal level comprising a metal line and the via level comprising a via contact to interconnect components of the device via the pre-metal dielectric layer;

patterning the BEOL dielectric to form a sensor opening in the BOEL dielectric, wherein patterning the BEOL dielectric also forms a relief opening to expose the cavity trench fill;

performing a first release to remove the cavity trench fill, thereby forming the lower sensor cavity; and

A second release is performed to remove the sensor support dielectric, thereby forming an independent sensor, wherein the independent sensor improves sensor sensitivity and response time.

13. The method of claim 12, wherein forming the pre-metal dielectric layer and the BEOL dielectric comprises forming a protective wall surrounding the MEMS region, the protective wall configured to protect the pre-metal dielectric layer and the BEOL dielectric in the CMOS region from damage by an etchant during the second release process forming the stand-alone sensor.

14. The method of claim 13, wherein forming the protective wall comprises:

Forming an inner protective wall and an outer protective wall, the inner protective wall being disposed within the outer protective wall, wherein

Forming the inner protective wall includes forming an inner protective wall opening, and

Forming the outer protective wall includes forming an outer protective wall opening; and

Wherein the inner and outer protective wall openings are formed

Facilitating electrical connection to the sensor without shorting the outer protective wall opening, and

An etchant flow path of the etchant of the second release process is extended to prevent damage to the pre-metal dielectric layer and the BEOL dielectric in the CMOS region.

15. The method of claim 12, wherein forming the sensor comprises forming an infrared sensor comprising an absorber.

16. The method of claim 15, comprising forming a reflector on a bottom surface of the lower sensor cavity.

17. The method of claim 16, wherein the depth of the absorber, reflector, and cavity are part of an interference absorbing system to improve absorption of infrared radiation.

18. The method of claim 12, wherein forming the sensor comprises:

Forming a first body segment that is a first polarity type body segment, wherein the first body segment includes

The first body section is configured to be coupled to the first body section,

forming a second body segment that is a second polarity type body segment, wherein the second body segment includes

The second body section is configured to be coupled to the first body section,

A second lead body segment extending from the first body segment, wherein an end of the second lead body segment serves as the second sensor terminal, wherein a body segment gap separates the first and second body segments, the body segment gap being disposed between adjacent edges of the first and second body segments; and

A sensor body contact is formed that electrically couples the first body section and the second body section.

19. The method of claim 18, wherein forming the sensor body contact comprises:

Forming first and second sensor body through-hole contacts on the first and second body sections; and

A sensor body contact plate is formed on the first body via contact and the second body via contact to electrically couple the first body section and the second body section.

20. The method of claim 19, wherein forming the first and second body via contacts comprises forming first and second body via ring contacts, wherein ring contacts comprise an electrically conductive outer ring filled with a dielectric filler, the ring contacts providing mechanical support for the stand-alone sensor.