CN118248673A

CN118248673A - Structure and method for detecting replacement quality of metal gate

Info

Publication number: CN118248673A
Application number: CN202410330070.7A
Authority: CN
Inventors: 夏禹; 董颖; 王昌锋
Original assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Current assignee: Shanghai Huali Integrated Circuit Manufacturing Co Ltd
Priority date: 2024-03-21
Filing date: 2024-03-21
Publication date: 2024-06-25

Abstract

The invention discloses a detection structure of metal gate replacement quality, which comprises the following components: the first PMOS is in an isolated structure, two sides of a first grid structure of the first PMOS are respectively provided with a parallel first adjacent grid structure, and the distance between the first grid structure and the first adjacent grid structure adopts the maximum grid distance allowed by design rules. The first test chain is provided with a first liner and a second liner at two ends respectively, and a series structure formed by connecting a contact hole, a first metal layer pattern and a corresponding grid structure to be tested is arranged between the first liner and the second liner; each first gate structure is connected in series as a tested gate structure on the first test chain and is part of the first test chain. The invention also discloses a detection method of the metal gate replacement quality. The invention is convenient for detecting the replacement quality problem of the metal gate through an electrical test, and can improve the detection efficiency.

Description

Structure and method for detecting replacement quality of metal gate

Technical Field

The invention relates to the field of semiconductor integrated circuit manufacturing, in particular to a Metal Gate (MG) replacement quality detection structure. The invention also relates to a detection method of the metal gate replacement quality.

Background

With the continued development of the integrated circuit industry, transistors have been advancing toward higher integration (density) and smaller size.

The process of 28nm high dielectric constant (HK) Metal Gate (MG), i.e. HKMG, is basically limited by planar process, and as the size and spacing of devices are made smaller and smaller, the metal gate under various conditions is uniformly averaged, and the performance is good and the difficulty is also increasing.

In the development of the 28nm HKMG process including the GATE-LAST process, the 28nmHKMG process using the G GATE-LAST process, the metal GATE is formed by adding amorphous silicon to a Hard Mask (HM) structure formed by stacking silicon nitride (SiN) and silicon Oxide (OX), and then replacing the amorphous silicon with metal before the interlayer film (ILD) process.

While the HM SiN/OX on amorphous silicon is used to ensure as uniform a height as possible for metal gate replacement. During development, the process of amorphous silicon replacement metal under different surrounding environments and conditions of a metal gate is found to have a lot of height difference, so that process defects are caused. The practical process requirements are that the metal gate needs to be replaced normally, and a certain height is maintained to ensure the metal gate resistance, whatever the circumstances.

As shown in fig. 1A to 1I, a schematic device structure in each step of the conventional metal gate replacement process is shown; the existing metal gate replacement process comprises the following steps:

As shown in fig. 1A, a gate structure 102 is formed on a semiconductor substrate 101, where the gate structure 102 is a dummy gate structure, and is formed by stacking a gate dielectric layer and a polysilicon gate or an amorphous silicon gate, which are generally denoted by PO. A hard mask layer HM formed by stacking a silicon nitride layer 103 and a silicon oxide layer 104 is formed on top of the gate structure 102.

A photoresist back etch (PREB) process is performed comprising:

as shown in fig. 1B, a photoresist layer 105 is coated.

As shown in fig. 1C, photoresist layer 105 is etched such that the top surface of photoresist layer 105 oxidizes the top surface of silicon layer 104.

As shown in fig. 1D, the hard mask layer is etched, and the silicon nitride layer 103 and the silicon oxide layer 104 are removed.

As shown in fig. 1E, deposition of a zeroth layer interlayer (ILD 0) 106 is performed.

As shown in fig. 1F, CMP is performed to planarize the top surface of the zeroth interlayer film 106 and the top surface of the gate structure 102.

As shown in fig. 1G, the gate structure 102 is removed, and in a prior high dielectric constant process (HK-first) only the polysilicon gate or amorphous silicon gate, i.e., PO layer, of the gate structure 102 is typically removed and a gate trench 107 is formed.

As shown in fig. 1H, metal filling of the metal gate 108 is performed, typically including filling of a metal work function layer and a metal conductive material layer.

As shown in fig. 1I, metal grinding is performed so that metal is located only in the gate trench 107 and a metal gate 108 is formed. Thus, the metal gate replacement process is completed.

In the development process of 28nm HKMG, we find that the height of HMOX will be different in different device regions before the PO of the gate structure enters the replacement metal gate process, and three conditions described below are usually needed to be properly and uniformly processed, so that the PO in the three conditions can be smoothly replaced by the metal gate, and the height is kept to ensure that the resistance of the metal gate cannot be too large.

The specific three cases are:

As shown in fig. 2A to 2D, the device structure of different devices on the same wafer in each step of the conventional metal gate replacement process is schematically shown.

In fig. 2A, 3 device regions are shown, region 101a represents the PMOS formation region, and in fig. 2A, region 101a also employs a PMOS table; region 101b represents the formation region of a conventional NMOS, and in fig. 2A, region 101b also employs an NMOS table; region 101c represents the formation region of an NMOS such as an electrostatic protection device (ESD) or an NMOS corresponding to an LDMOS device where metal silicide formation is not required, and region 101c is also represented by ESD in fig. 2A.

In the region 101a, since the PMOS needs to form an embedded epitaxial layer, such as an embedded sige epitaxial layer, in the source and drain regions on both sides of the gate structure, the thickness of the silicon oxide layer 104 on top of the gate structure 102 of the PMOS will be lost during the formation of the embedded epitaxial layer. Thus, the top surface of silicon oxide layer 104 in region 101a will be lower than the top surface of silicon oxide layer 104 in region 101 b.

If etching is performed according to the requirements of the PMOS gate structure 102 during the HM etching, when the hard mask layer on top of the PMOS gate structure 102 is removed, the hard mask layer may remain on top of the gate structure 102 corresponding to the NMOS in the region 101 b. If the etching is performed according to the requirement of the gate structure 102 corresponding to the NMOS in the region 101b, when the hard mask layer on top of the gate structure 102 corresponding to the NMOS is removed, the gate structure 102 corresponding to the PMOS in the region 101a may be over-etched, so that the height of the gate structure 102 is reduced. Therefore, the height of the top surface of the hard mask layer is uneven, the difficulty is brought to the etching process of the hard mask layer, if the etching amount of the hard mask layer is increased, the grid structure of the PMOS is easy to be too short, and finally the resistance of the metal grid of the PMOS is increased; if the etching amount of the hard mask layer is reduced, the hard mask layer on the top of the gate structure of the NMOS is easy to remain, so that the gate structure of the NMOS cannot be replaced by the metal gate.

In fig. 2A, since the metal silicide is not required to be formed in the region 101c, a metal silicide blocking layer (SAB) layer is added on top of the gate structure 102, and the SAB layer is overlapped in the silicon oxide layer 104, so that the thickness of the silicon oxide layer 104 in the region 101c is thicker than that in the region 101b, and thus the problem of hard mask layer residue in the region 101c is more likely to occur.

Fig. 2B shows a step in which the etching of the photoresist layer 105 is completed, i.e., a step corresponding to fig. 1C.

Fig. 2C shows the completion of the etching step of the hard mask layer, i.e., the step corresponding to fig. 1D, while removing the remaining photoresist layer 105. It can be seen that in fig. 2C, the etching of the hard mask layer is performed according to the requirements of the PMOS gate structure 102, so that the hard mask layer remains in both regions 101b and 101C.

As shown in fig. 2D, the process of forming and CMP of the completed ILD0, removal of the gate structure 102, filling and CMP of the metal gate 108 is shown, i.e., all steps of fig. 1E-1I are completed. It can be seen that PMOS achieves normal replacement of metal gate 108; however, in the regions 101b and 101c, the hard mask layer on top of the gate structure 102 is present, so that the gate structure 102 in the regions 101b and 101c cannot be removed in the step of removing the gate structure 102.

Also, if the etching amount is increased in the step of etching the hard mask layer, the height of the metal gate 108 of the PMOS may become very low, so that the resistance of the metal gate 108 may be very high, which also affects the performance of the device.

In the existing methods, the metal gate process has no special monitoring (monitor) method for the problems of the three conditions, and many cases are continuously found in the slices of the chips with device/wafer test (CP) failure (fail), so that the existing monitoring method cannot find the problems in time, and has low efficiency and high cost.

Disclosure of Invention

The invention aims to provide a detection structure for the replacement quality of a metal gate, which is convenient for detecting the replacement quality problem of the metal gate through an electrical test, and can improve the detection efficiency and simultaneously detect the quality problems of various metal gates compared with the detection of the replacement quality problem of the metal gate through slicing, and is convenient for realizing multi-point detection so as to improve the sampling rate. Therefore, the invention also provides a method for detecting the replacement quality of the metal gate.

In order to solve the above technical problems, the detection structure for metal gate replacement quality provided by the present invention includes:

At least one first PMOS formed in a first Active Area (AA) and being an Isolated (ISO) PMOS, a length direction of a first gate structure of the first PMOS extending along a width direction of the first active area.

And the first adjacent gate structures are arranged on two sides of the first gate structure respectively, each first adjacent gate structure is parallel to the first gate structure, and the space between the first gate structure and the corresponding first adjacent gate structure adopts the maximum gate space allowed by the design rule.

The first test chain is provided with a first pad (pad) and a second pad at two ends, a plurality of contact holes (CT), a plurality of first metal layer patterns and a series structure formed by connecting corresponding tested grid structures are arranged between the first pad and the second pad, and two ends of each tested grid structure are connected to the first metal layer patterns corresponding to the top through the corresponding contact holes; and two ends of each first metal layer pattern are respectively connected to the tested gate structure corresponding to the bottom through the corresponding contact hole.

Each first gate structure is used as one tested gate structure connected in series on the first test chain and used as a part of the first test chain, and the first gate structure is used as an analog structure with the height of the metal gate below a target value after the metal gate is replaced.

Further improvement is, the detection structure still includes:

At least one first NMOS formed in a second active region provided with a metal silicide; the length direction of the second gate structure of the first NMOS extends along the width direction of the second active region.

Two sides of the second gate structure are respectively provided with a second adjacent gate structure, each second adjacent gate structure is parallel to the second gate structure, the width of the second gate structure adopts the minimum gate width allowed by the design rule, and the spacing between the second gate structure and the corresponding second adjacent gate structure adopts the minimum gate spacing allowed by the design rule.

Each of the second gate structures is connected in series with and is part of the first test chain as one of the gate structures under test, and the second gate structures are used as a metal gate replacement unfinished analog structure.

Further improvement is, the detection structure still includes:

At least one second NMOS formed in a third active region without metal silicide disposed therein; the length direction of the third gate structure of the second NMOS extends along the width direction of the third active region.

Each third gate structure is used as one tested gate structure connected in series on the first test chain and used as a part of the first test chain, and the third gate structure is used as another metal gate replacement unfinished analog structure.

A further improvement is that one of the second NMOS is disposed on each side of the first PMOS.

Each first adjacent gate structure corresponding to the first PMOS adopts the third gate structure corresponding to the second NMOS.

In a further improvement, each first gate structure and a corresponding second gate structure are aligned and connected and combined into a first integral gate structure, and each first integral gate structure is used as one tested gate structure to be connected in series with the first test chain.

A further improvement is that the number of third active regions comprises a plurality.

Each third active region comprises a plurality of second NMOS, and the third gate structures of the second NMOS are parallel.

And two adjacent second NMOS of each first PMOS are respectively positioned in the third active regions at two sides of the first PMOS.

In a further improvement, one third gate structure in each third active region and one corresponding second gate structure are aligned and connected to be combined into one second integral gate structure, and each second integral gate structure is used as one tested gate structure to be connected in series with the first test chain.

A further improvement is that the length edges of the third active regions are aligned and arranged on the same straight line.

Each of the first active regions is disposed in a spaced region between each of the third active regions.

The length edges of the second active regions and the length edges of the third active regions are parallel and have a distance, and in the extending direction along the length edges of the second active regions, each third active region and a spacing region between the third active regions are located in the extending range of the length edges of the second active regions.

In a further improvement, in each of the third active regions, the third gate structure located at the middle position and a corresponding one of the second gate structures are aligned and connected to be combined into one of the second integral gate structures.

A further improvement is that the number of the first active regions is 2 and the number of the third active regions is 3.

And 5 second NMOS are arranged in each third active region.

And 5 first NMOS are arranged in the second active region.

A further improvement is that the detection structures are arranged at a plurality of positions of the wafer.

A further improvement is that the width of the second adjacent gate structure adopts the maximum gate width allowed by the design rule or more than 1 micron.

In order to solve the technical problems, the method for detecting the replacement quality of the metal gate provided by the invention comprises the following steps:

And testing the resistance of the first test chain through the first pad and the second pad to obtain a test resistance.

And judging the quality of the metal gate according to the test resistor.

In a further improvement, the step of judging the quality of the metal gate according to the test resistor includes:

And if the test resistance indicates that the first test chain is conducted and the test resistance is smaller than or equal to a first target value, judging that the quality of each metal gate is normal and the metal gate replacement process is normal.

And if the test resistor indicates that the first test chain is conducted and the test resistor is larger than a first target value, judging that the height of the metal gate of the first PMOS is lower than the target value, and the quality of the metal gate of the first NMOS and the quality of the metal gate of the second NMOS are normal.

If the test resistor indicates that the first test chain is disconnected, judging that the metal gate of the first NMOS is not replaced or the metal gate of the second NMOS is not replaced.

And detecting the replacement quality of the metal gate in WAT test and performing multipoint detection on each wafer.

A further improvement is that the test resistance is calculated by applying a voltage and a current between the first pad and the second pad.

A further improvement is that the first target value is obtained from a test of the gate resistance of a normal product.

In the invention, by setting the first PMOS as an isolated PMOS structure, the worst condition of the quality problem of the metal gate of the PMOS in the metal gate replacement process can be simulated, namely, as long as the quality problem of the metal gate of the PMOS occurs, the quality of the metal gate of the first PMOS inevitably occurs, because the spacing between the first gate structure and the corresponding first adjacent gate structure is set by adopting the maximum gate spacing allowed by the design rule, the maximum gate spacing is larger than the spacing of the gate structure of the common PMOS, and if the quality problem of the metal gate of the PMOS occurs, namely, the height of the metal gate is reduced, the height reduction amount of the metal gate of the first PMOS can reach the maximum, and therefore, the quality of the metal gate of the PMOS can be detected by connecting the first gate structure of the first PMOS into the first test chain in series and measuring the resistance of the first test chain by an electrical method.

According to the invention, the first NMOS is arranged, the width of the second grid structure of the first NMOS and the distance between two sides of the second grid structure are both the minimum values allowed by the design rule, so that the first NMOS can show the problem that the metal grid is not replaced in the NMOS with the conventional metal silicide, and the metal grid of the first NMOS is always in quality problem as long as the metal grid replacement process of the conventional NMOS is in problem, so that the quality of the metal grid of the conventional NMOS can be detected by connecting the second grid structure of the first NMOS in series to the first test chain and measuring the resistance of the first test chain by an electrical method.

According to the invention, the second NMOS is arranged, the metal silicide is not arranged in the third active region corresponding to the second NMOS, when the NMOS without the metal silicide, such as an NMOS for electrostatic protection (ESD) or an NMOS adopting an LDMOS structure, has the problem that the metal gate is not replaced, the corresponding problem can also occur in the metal gate of the second NMOS, and the probability of detecting the quality problem of the metal gate of the NMOS without the metal silicide can be increased by arranging a plurality of second NMOS.

The invention can simultaneously set the first PMOS, the first NMOS and the second NMOS in the same detection structure, thereby realizing the detection of various difficult problems in the replacement of the metal gate by adopting one detection structure, and not only having small occupied area but also having high test efficiency.

In addition, the detection structure can be arranged at a plurality of positions of the wafer, so that the metal gate quality on the wafer can be subjected to multi-point detection, and the detection sampling rate can be improved.

Drawings

The invention is described in further detail below with reference to the attached drawings and detailed description:

FIGS. 1A-1I are schematic views of a device structure at various steps of a conventional metal gate replacement process;

FIGS. 2A-2D are schematic views of device structures at different devices on the same wafer during various steps of a conventional metal gate replacement process;

FIG. 3 is a top plan view block diagram of a metal gate replacement quality detection structure according to an embodiment of the present invention;

FIGS. 4A-4D are schematic views of device structures of gate structures at a first PMOS and a first NMOS in a photoresist back etch (PREB) process of a metal gate replacement process in a metal gate replacement quality detection structure according to an embodiment of the present invention;

Fig. 5 is a photograph of a gate structure of a metal gate replacement quality detection structure according to an embodiment of the present invention, before a photoresist back etching process of the metal gate replacement process.

Detailed Description

As shown in fig. 3, a top plan view of a structure for detecting the replacement quality of a metal gate according to an embodiment of the present invention is shown; the detection structure of the metal gate replacement quality in the embodiment of the invention comprises the following components:

At least one first PMOS formed in the first active region 201a and being an isolated PMOS, a length direction of the first gate structure 202a of the first PMOS extending along a width direction of the first active region 201 a.

A first adjacent gate structure is disposed on each side of the first gate structure 202a, each of the first adjacent gate structures is parallel to the first gate structure 202a, a space between the first gate structure 202a and the corresponding first adjacent gate structure adopts a maximum gate space allowed by a design rule, and in fig. 3, a space between the first gate structure 202a and the corresponding first adjacent gate structure is denoted by d 101.

A first test chain, two ends of which are respectively provided with a first pad 205a and a second pad 205b, wherein a series structure formed by connecting a plurality of contact holes 203, a plurality of first metal layer patterns 204 and corresponding tested gate structures is arranged between the first pad 205a and the second pad 205b, and two ends of each tested gate structure are respectively connected to the first metal layer patterns 204 corresponding to the top through the corresponding contact holes 203; both ends of each first metal layer pattern 204 are respectively connected to the corresponding tested gate structure at the bottom through the corresponding contact hole 203.

Each of the first gate structures 202a is connected in series with the first test chain as one of the gate structures under test and is a part of the first test chain, and the first gate structures 202a are analog structures with metal gates having heights lower than a target value after metal gate replacement.

In an embodiment of the present invention, the detection structure further includes:

At least one first NMOS formed in the second active region 201b and the second active region 201b is provided with a metal silicide; the length direction of the second gate structure 202b of the first NMOS extends along the width direction of the second active region 201 b.

Two second adjacent gate structures 202d are disposed on two sides of the second gate structure 202b, each second adjacent gate structure 202d is parallel to the second gate structure 202b, the width of the second gate structure 202b adopts the minimum gate width allowed by the design rule, and the spacing between the second gate structure 202b and the corresponding second adjacent gate structure 202d adopts the minimum gate spacing allowed by the design rule. In fig. 3, the spacing of the second gate structure 202b and the corresponding second adjacent gate structure 202d is denoted by d 102.

In an embodiment of the present invention, the width of the second adjacent gate structure 202d is equal to or greater than 1 μm of the maximum gate width allowed by the design rule.

Each of the second gate structures 202b is connected in series as one of the gate structures under test to the first test chain and as part of the first test chain, and the second gate structures 202b are configured as a metal gate replacement unfinished analog structure.

at least one second NMOS formed in the third active region 201c and the third active region 201c is not provided with a metal silicide; the length direction of the third gate structure 202c of the second NMOS extends along the width direction of the third active region 201 c.

Each of the third gate structures 202c is connected in series as one of the gate structures under test on the first test chain and as part of the first test chain, and the third gate structure 202c is used as another analog structure with incomplete metal gate replacement.

In the embodiment of the invention, two sides of the first PMOS are respectively provided with the second NMOS.

Each of the first adjacent gate structures corresponding to the first PMOS employs the third gate structure 202c of the corresponding second NMOS.

Each of the first gate structures 202a and a corresponding one of the second gate structures 202b are aligned and connected to combine into one first integral gate structure 2021, and each of the first integral gate structures 2021 is connected in series as one of the gate structures under test in the first test chain.

The number of the third active regions 201c includes a plurality.

Each of the third active regions 201c includes a plurality of the second NMOS, and the third gate structures 202c of the second NMOS are parallel.

And two adjacent second NMOS of each first PMOS are respectively located in the third active regions 201c on both sides of the first PMOS.

One of the third gate structures 202c in each of the third active regions 201c is aligned with and connected to and combined with a corresponding one of the second gate structures 202b to form a second integral gate structure 2022, and each of the second integral gate structures 2022 is connected in series with the first test chain as one of the gate structures under test.

The length sides of the third active regions 201c are aligned and aligned on the same straight line.

Each of the first active regions 201a is disposed in a space region between each of the third active regions 201 c.

The length sides of the second active regions 201b and the length sides of the third active regions 201c are parallel and have a pitch, and in the extending direction along the length sides of the second active regions 201b, each third active region 201c and the interval region between each third active regions 201c are located within the extending range of the length sides of the second active regions 201 b.

In each of the third active regions 201c, the third gate structure 202c located at the middle position and the corresponding one of the second gate structures 202b are aligned and connected to be combined into one of the second integral gate structures 2022. The number of the third gate structures 202c on the left and right sides of the second global gate structure 2022 is related to the dimension of the second neighboring gate structure 202d along the length direction of the second active region 201b, and the larger the dimension of the second neighboring gate structure 202d is, the larger the number of the third gate structures 202c on the left and right sides of the second global gate structure 2022 is, and the larger the number of the third gate structures 202c provided in each of the third active regions 201c is, the larger the number of the second NMOS is, so as to increase the probability of detecting quality problems of a non-metal silicide formation region, i.e., a metal gate of an NMOS corresponding to an ESD or LDMOS.

In some embodiments, the number of the first active regions 201a is 2, and the number of the third active regions 201c is 3.

5 Second NMOS are disposed in each of the third active regions 201 c.

5 First NMOS are disposed in the second active region 201 b.

In fig. 3, 2 of said first PMOS's are shown, located in dashed boxes 301a and 301b, respectively.

In fig. 3,5 of the first NMOS's are shown, all located in the dashed box 302.

In fig. 3, dashed boxes 303a, 303b and 303c are all forming areas of the second NMOS, and each of the dashed boxes 303a, 303b and 303c includes 5 second NMOS.

In other embodiments, the number of the first active regions 201a and the third active regions 201c can be changed as needed; the number of the second NMOS devices in each of the third active regions 201c can be changed as needed; the number of the first NMOS devices disposed in the second active region 201b can also be changed as needed.

In the embodiment of the invention, the detection structures are arranged at a plurality of positions of the wafer.

In the embodiment of the invention, by setting the first PMOS to be an isolated PMOS structure, the worst case when the quality problem occurs in the metal gate of the PMOS in the metal gate replacement process can be simulated, that is, as long as the quality problem occurs in the metal gate of the PMOS, the quality of the metal gate of the first PMOS will inevitably occur, because the pitches of the first gate structure 202a and the corresponding first adjacent gate structure are set by adopting the maximum gate pitch allowed by the design rule, and the maximum gate pitch will be larger than the pitch of the gate structure of the normal PMOS, so if the quality problem occurs in the metal gate of the PMOS, that is, the height of the metal gate is reduced, the height of the metal gate of the first PMOS will be reduced to the maximum, and therefore, by connecting the first gate structure 202a of the first PMOS in series to the first test chain, the resistance of the first test chain is measured by an electrical method, the quality of the metal gate of the PMOS can be detected.

According to the embodiment of the invention, the first NMOS is arranged, the width of the second gate structure 202b of the first NMOS and the distance between two sides of the second gate structure 202b are both the minimum allowed by the design rule, so that the first NMOS can show the problem that the metal gate is not replaced in the NMOS with the conventional metal silicide, and the metal gate of the first NMOS inevitably has quality problems as long as the metal gate replacement process of the conventional NMOS has problems, so that the quality of the metal gate of the conventional NMOS can be detected by connecting the second gate structure 202b of the first NMOS in series to a first test chain and measuring the resistance of the first test chain by an electrical method.

According to the embodiment of the invention, the second NMOS is arranged, the metal silicide is not arranged in the third active region 201c corresponding to the second NMOS, when the NMOS without the metal silicide, such as an NMOS for electrostatic protection (ESD) or an NMOS adopting an LDMOS structure, has the problem that the metal gate is not replaced, the corresponding problem also occurs in the metal gate of the second NMOS, and the probability of detecting the quality problem of the metal gate of the NMOS without the metal silicide can be increased by arranging a plurality of second NMOS.

The embodiment of the invention can simultaneously set the first PMOS, the first NMOS and the second NMOS in the same detection structure, thereby realizing the detection of various difficult problems in the replacement of the metal gate by adopting one detection structure, and not only having small occupied area, but also having high test efficiency.

In addition, the detection structure provided by the embodiment of the invention can be arranged at a plurality of positions of the wafer, so that the quality of the metal gate on the wafer can be detected at multiple points, and the sampling rate of detection can be improved.

The inspection structure of the embodiment of the present invention is manufactured along with the MOS transistors of the product area on the wafer, so that the problem that the MOS transistors of the product area are prone to occur will first be reflected in the inspection structure of the embodiment of the present invention, and the inspection structure of the embodiment of the present invention is further described below with reference to the metal gate replacement process:

Fig. 4A to fig. 4D are schematic device structure diagrams of gate structures at the first PMOS and the first NMOS in the photoresist back etching process of the metal gate replacement process in the detection structure of metal gate replacement quality according to the embodiment of the present invention; as shown in fig. 4A, a schematic device structure of the first PMOS formation region and the first NMOS formation region after the photoresist coating, which is a mask in the pre process flow, is completed, in fig. 4A, a region 306 represents the first PMOS formation region, a region 307 represents the first NMOS formation region, a region 306 corresponds to a region located in a dashed-line frame 301a in a region indicated by a dashed-line frame 304 in fig. 3, and a region 307 corresponds to a region indicated by a dashed-line frame 305 in fig. 3. The active region 201 is shown in fig. 4A as including a first active region 201a and a second active region 201b.

It can be seen that a hard mask layer is formed on top of each gate structure by superimposing a silicon nitride layer 401 and a silicon oxide layer 402. At this time, the first gate structure 202a, the second gate structure 202b, and the second adjacent gate structure 202d are all polysilicon dummy gates (dummy poly gates).

But an embedded epi layer, such as an embedded sige epi layer, is formed on both sides of the first gate structure 202a, and the thickness of the silicon oxide layer 402 is lost during the formation of the embedded epi layer. The top surface of the hard mask layer on top of the first gate structure 202a is lower. After coating the photoresist layer 403, the top surface of the photoresist layer 403 in region 306 is lower than the top surface of the photoresist layer 403 in region 307.

As shown in fig. 4B, the exposure and development process is performed to expose a large block of polysilicon, i.e., the photoresist layer 403 on top of the second adjacent gate structure 202d, so that the photoresist layer 403 on top of the small block of polysilicon is not opened.

As shown in fig. 4C, the photoresist layer 403 is etched back, and it can be seen that after etching back, the top surface of the photoresist layer 403 in the region 306 is lower than the top surface of the silicon nitride layer 401; the top surface of photoresist layer 403 in region 307 is then higher, substantially level with or slightly lower than the top surface of silicon oxide layer 402.

As shown in fig. 4D, the etching of the hard mask layer is performed, and at this time, the hard mask layer, i.e., the silicon nitride layer 401 and the silicon oxide layer 402 in the region 306 are completely exposed, so that they are completely removed in the etching step, and the bottom first gate structure 202a is also easily damaged.

Meanwhile, since the hard mask layer in the region 306 is not easily completely removed, residues of the hard mask layer such as the silicon nitride layer 401 are easily generated at the second gate structure 202 b.

Since the etching process conditions of the hard mask layer are the same, the loss of the first gate structure 202a may occur in the region 306, and the hard mask layer residue may easily occur in the region 307. The first PMOS in the embodiment of the present invention can simulate the situation that the height of the metal gate is low, and detect the situation through the gate resistance of the first PMOS when the height of the metal gate is low.

However, when the hard mask layer remains on the top surface of the second gate structure 202b of the first NMOS in the region 307, the subsequent metal gate cannot be replaced successfully, that is, the polysilicon dummy gate of the second gate structure 202b cannot be removed, so that the metal gate cannot be filled into the polysilicon dummy gate removal region. At this time, the second gate structure 202b of the first NMOS will be disconnected from the contact hole at the top, so in the embodiment of the present invention, the arrangement of the first NMOS can simulate the situation that the metal gate in the conventional NMOS, that is, the NMOS with metal silicide cannot be replaced, and detect through the disconnection of the gate series section of the first NMOS when the metal gate of the conventional NMOS cannot be replaced.

In addition, as shown in fig. 5, in the detection structure for metal gate replacement quality in the embodiment of the present invention, the gate structures at the first NMOS and the second NMOS are photographs of the gate structures before the photoresist back etching process of the metal gate replacement process; in fig. 5, a region 308 corresponds to a first NMOS formation region, and a region 309 corresponds to a second NMOS formation region; region 308 corresponds to the region between two second adjacent gate structures 202d in dashed box 305 in fig. 3, and region 309 corresponds to the region of one third gate structure 202c and both sides in fig. 3.

In fig. 3, a metal silicide blocking layer (SAB) 206 is also formed in the second NMOS formation region for preventing metal silicide formation in the second NMOS formation region.

As can be seen from the cross-sectional view of fig. 5, the hard mask layer on top of the second gate structure 202b is formed by stacking a silicon nitride layer 401 and a silicon oxide layer 402; the hard mask layer on top of the third gate structure 202c is further stacked with a metal silicide blocking layer 206 on top of the silicon nitride layer 401 and the silicon oxide layer 402. The metal silicide blocking layer 206 thickens the hard mask layer, so that in the pre process, the hard mask layer on top of the third gate structure 202c is also easy to remain in the etching process for removing the hard mask layer; that is, when the hard mask layer cannot be removed in the NMOS of the product region of the wafer, for example, the NMOS of the ESD device and the NMOS of the LDMOS device, the third gate structure 202c of the second NMOS of the embodiment of the present invention also has the situation that the hard mask layer cannot be removed, so by the arrangement of the second NMOS, the situation that the metal gate in the NMOS of the wafer cannot be replaced can be simulated, and the detection can be performed by the gate series section disconnection of the second NMOS when the metal gate of the NMOS of the wafer cannot be replaced.

The detection method of the metal gate replacement quality comprises the following steps:

The resistance of the first test chain is tested by the first pad 205a and the second pad 205b and a test resistance is obtained.

In the method of the embodiment of the present invention, the test resistance is calculated by applying a voltage and a current between the first pad 205a and the second pad 205 b.

And judging the quality of the metal gate according to the test resistor. The step of judging the quality of the metal gate according to the test resistor comprises the following steps:

And if the test resistance indicates that the first test chain is conducted and the test resistance is smaller than or equal to a first target value, judging that the quality of each metal gate is normal and the metal gate replacement process is normal. The first target value is based on testing the gate resistance of a normal product, typically by collecting and trending the gate resistances of a large number of products (TREND CHART).

In the method of the embodiment of the invention, the detection structures are arranged at a plurality of positions of the wafer.

And detecting the replacement quality of the metal gate in WAT test and performing multipoint detection on each wafer. Through multipoint detection, the sampling rate can be increased, which is much higher than the monitoring method for detecting the defects (INLINE DEFECT) on the existing line.

As can be seen from fig. 3, the pattern of the embodiment of the present invention is composed of Active Areas (AA) 201a to 201c, gate structures 202a to 202d, i.e., PO or MG, metal silicide blocking layer 206 (SAB), contact hole 204 (CT), first metal layer pattern 204 (M1), test pads 205a and 205b (TESTPAD), and N/P MOS mark layer (MARKING LAYER). The graphic style and hierarchy name are described in the following figures.

In fig. 3, the first PMOS simulates an ISO PMOS, and the gate structure 202a of the ISO PMOS, i.e., the PO-to-adjacent PO spacing, is designed to be the maximum distance allowed by the PO or dummy gate structure (PO dummy) in the Design Rule (Design Rule) to simulate the PO of the most ISO PMOS in the chip. The test data shows that: in the pre process of ISO POLY, i.e. PO of ISO PMOS, the surrounding photoresist, i.e. photoresist, will be etched to the greatest extent, resulting in the problem of overetching of PO.

The gate structure 202b of the first NMOS is a PO simulating the NMOS small PO sandwiched by the large blocks PO, the large blocks PO being the large block gate structures 202d, and the small PO being the gate structures 202b. The width of the small PO is the narrowest design rule, the spacing between the large block PO and the space of the small PO is the smallest design rule, the width of the large block PO is the largest allowed design rule or larger than 1 um. The test data shows that: the PREB resist on top of the small PO in this structure will be left intact during lithography, resulting in the risk that the HM cannot be cleaned up during subsequent HM etching.

The gate structure 202bNMOS SAB PO region of the second NMOS. Because of design requirements, some of the POs in the chip will be covered with SAB, resulting in almost doubling the thickness of the oxide layer at the top of PO, i.e. as a hard mask layer, affecting the process window (process window) for metal gate replacement. The width of the PO covered by the SAB in FIG. 3 is the maximum width that the ESD/LDMOS in the corresponding process platform allows for the SAB to cover.

The embodiment test method comprises the following steps:

The whole pattern is a PO-CT-M1 serpentine chain (SNAKE CHAIN) structure, namely a first test chain, and the first test chain pattern combines all three types of the PO structures.

In the test, only a voltage is applied between the test pads 205a and 205b, a current is measured, a resistance is finally calculated, and then, whether the metal gate process is OK is judged based on the resistance value.

If the test resistance is small and in a trend graph (TREND CHART) that has long been stable in the collected product versus gate resistance, then the wafer metal gate process is judged to be good.

If the resistance is large, it is suspected that the PMOS PO may be too short. And if the test result shows chain (chain) disconnection (OPEN), more consideration is given to the NMOS PO structure sandwiched by large POs or SAB NMOS PO does not complete metal gate replacement.

The graph of FIG. 3 in the embodiment of the invention integrates and compresses the difficulties of the metal gate manufacturing process, and has small occupied area and high test efficiency. After the Wafer Acceptance Test (WAT) is implanted, each wafer can be subjected to multi-point test, and the sampling rate (SAMPLE RATE) is much higher than that of monitoring methods such as online defect (INLINE DEFECT) detection and the like.

The embodiment of the invention is suitable for detecting the quality of the metal gate of all HKMG manufacturing processes adopting a back gate process.

The present invention has been described in detail by way of specific examples, but these should not be construed as limiting the invention. Many variations and modifications may be made by one skilled in the art without departing from the principles of the invention, which is also considered to be within the scope of the invention.

Claims

1. The utility model provides a detection structure of metal gate replacement quality which characterized in that, detection structure includes:

at least one first PMOS formed in the first active region and being an isolated PMOS, a length direction of a first gate structure of the first PMOS extending along a width direction of the first active region;

each first adjacent gate structure is arranged on two sides of the first gate structure, each first adjacent gate structure is parallel to the first gate structure, and the space between the first gate structure and the corresponding first adjacent gate structure adopts the maximum gate space allowed by design rules;

The first test chain is provided with a first liner and a second liner at two ends, a series structure formed by connecting a plurality of contact holes, a plurality of first metal layer patterns and corresponding tested grid structures is arranged between the first liner and the second liner, and two ends of each tested grid structure are connected to the first metal layer patterns corresponding to the top through the corresponding contact holes; two ends of each first metal layer pattern are connected to the tested gate structure corresponding to the bottom through the corresponding contact holes respectively;

2. The metal gate displacement quality detection structure according to claim 1, further comprising:

At least one first NMOS formed in a second active region provided with a metal silicide; the length direction of the second grid structure of the first NMOS extends along the width direction of the second active region;

two sides of the second gate structure are respectively provided with a second adjacent gate structure, each second adjacent gate structure is parallel to the second gate structure, the width of the second gate structure adopts the minimum gate width allowed by the design rule, and the spacing between the second gate structure and the corresponding second adjacent gate structure adopts the minimum gate spacing allowed by the design rule;

3. The structure for detecting the displacement quality of a metal gate according to claim 2, further comprising:

At least one second NMOS formed in a third active region without metal silicide disposed therein; the length direction of the third gate structure of the second NMOS extends along the width direction of the third active region;

4. A metal gate displacement quality detection structure according to claim 3, wherein: the second NMOS is respectively arranged at two sides of the first PMOS;

5. The metal gate replacement quality detection structure according to claim 4, wherein: each first gate structure and a corresponding second gate structure are aligned and connected to form a first integral gate structure, and each first integral gate structure is used as one tested gate structure to be connected in series with the first test chain.

6. The metal gate replacement quality detection structure according to claim 5, wherein: the number of the third active regions includes a plurality;

Each third active region comprises a plurality of second NMOS, and the third grid structures of the second NMOS are parallel;

7. The metal gate replacement quality detection structure according to claim 6, wherein: one third gate structure in each third active region and one corresponding second gate structure are aligned and connected to be combined into one second integral gate structure, and each second integral gate structure is used as one tested gate structure to be connected in series with the first test chain.

8. The metal gate replacement quality detection structure according to claim 7, wherein: the length edges of the third active areas are aligned and arranged on the same straight line;

each of the first active regions is disposed in a space region between each of the third active regions;

9. The metal gate replacement quality detection structure according to claim 8, wherein: in each third active region, the third gate structure located at the middle position and a corresponding one of the second gate structures are aligned and connected to be combined into one second integral gate structure.

10. The metal gate replacement quality detection structure according to claim 9, wherein: the number of the first active areas is 2, and the number of the third active areas is 3;

5 second NMOS are arranged in each third active region;

and 5 first NMOS are arranged in the second active region.

11. The metal gate replacement quality detection structure according to claim 9, wherein: the detection structures are arranged at a plurality of positions of the wafer.

12. The metal gate replacement quality detection structure according to claim 2, wherein: the width of the second adjacent gate structure adopts the maximum gate width allowed by the design rule or more than 1 micrometer.

13. A detection method for detecting by using the detection structure of the displacement quality of the metal gate according to claim 3, comprising the steps of:

Testing the resistance of the first test chain through the first pad and the second pad to obtain a test resistance;

and judging the quality of the metal gate according to the test resistor.

14. The method for detecting the displacement quality of a metal gate according to claim 13, wherein: the step of judging the quality of the metal gate according to the test resistor comprises the following steps:

If the test resistance indicates that the first test chain is conducted and the test resistance is smaller than or equal to a first target value, judging that the quality of each metal gate is normal and the metal gate replacement process is normal;

If the test resistor indicates that the first test chain is conducted and the test resistor is larger than a first target value, judging that the height of the metal gate of the first PMOS is lower than the target value, and the quality of the metal gate of the first NMOS and the quality of the metal gate of the second NMOS are normal;

15. The method for detecting the displacement quality of a metal gate according to claim 14, wherein: the detection structures are arranged at a plurality of positions of the wafer;

16. The method for detecting the displacement quality of a metal gate according to claim 13, wherein: the test resistance is calculated by applying a voltage and a current between the first pad and the second pad.

17. The method for detecting the displacement quality of a metal gate according to claim 14, wherein: the first target value is obtained by testing the grid resistance of the normal product.