CN118234086A

CN118234086A - LED driving circuit

Info

Publication number: CN118234086A
Application number: CN202410643228.6A
Authority: CN
Inventors: 李育军; 董渊; 庄健
Original assignee: Shanghai Ziying Microelectronics Co ltd
Current assignee: Shanghai Ziying Microelectronics Co ltd
Priority date: 2024-05-23
Filing date: 2024-05-23
Publication date: 2024-06-21

Abstract

The invention belongs to the technical field of integrated circuits, and provides an LED driving circuit, which comprises: a driving main circuit module and a redundant current module; the driving main circuit module comprises an input end, a control end and an output end; the input end is used for inputting control current, the control end is used for inputting a first PWM signal, and the output end is used for outputting load current; the load current is used for driving the LED to work; when the first PWM signal is at a high level, the main circuit module is driven to establish a working point; the driving main circuit module controls the magnitude of the output load current according to the magnitude of the control current and the duty ratio of the first PWM signal; the redundant current module generates redundant current when the first PWM signal is at a low level, and maintains the working point of the driving main circuit module; the redundant current is turned off when the first PWM signal is high. The invention can realize the accurate control of the load current when the PWM duty ratio is smaller.

Description

LED driving circuit

Technical Field

The invention relates to the technical field of integrated circuits, in particular to an LED driving circuit.

Background

With the wide acceptance of the advantages of LED and OLED light sources, the application of LEDs and OLEDs covers various scenes, such as automotive lighting, tail light driving, backlight driving of television and computer screens, and the like. As shown in fig. 1, the simple LED driving circuit controls the gate voltages of the 2 MOS transistors by controlling the magnitude of the current iref, thereby controlling the magnitude of the load current iout.

In addition to controlling the magnitude of the load current by controlling the current iref in fig. 1, some systems also require that the magnitude of the load current iout can be further controlled to increase the dimming contrast (ratio of maximum current to minimum current), as shown in fig. 2, at this time, the magnitude of the load current iout can be controlled by increasing the PWM signal and controlling the duty cycle of the PWM signal.

Although the circuit in fig. 2 can realize that the load current iout is adjusted along with the current iref and PWM, there is a problem that the load current iout varies along with the number of external LEDs, and to solve this problem, it is generally necessary to increase an operational amplifier for controlling the channel voltage of the output terminal, and the circuit in fig. 3 can drive the load current iout, as shown in fig. 3, so that the load current iout varies along with the current iref and the PWM duty ratio, thereby realizing the adjustment of the load current iout.

However, in some applications, the current required varies very widely, such as notebook backlight driving, and the ratio of maximum brightness to minimum brightness is usually millions in order to increase the screen contrast, and the current iref and PWM duty ratio are required to further increase in the variation range. Wherein the PWM signal is exemplified by 200Hz frequency, if the minimum on time of PWM is 5us, the ratio of the maximum and minimum of the current controlled by PWM part is 5ms/5us, namely 1000, if the minimum on time of PWM is reduced to 0.5us under the premise of ensuring the current precision, the ratio of the maximum brightness and the minimum brightness is increased by 10 times, namely 10000. This requirement drives the driver chip to continually reduce the minimum PWM on-time while still maintaining a certain degree of accuracy.

In the driving circuit shown in fig. 3, the load current iout is outputted when the PWM is at a high level; when PWM is low, the load current iout is turned off. Such an operation is not problematic at normal PWM frequencies and duty cycles, but as the PWM frequency decreases, the minimum on-time decreases, and the two op-amps further deviate from the operation when the PWM is low, and it becomes more difficult to reestablish these operating points and generate accurate load current at the PWM high level, i.e., the minimum on-time.

Therefore, how to realize accurate control of the load current even when the PWM duty ratio is small is a problem that needs to be solved at present.

Disclosure of Invention

The invention aims to provide an LED driving circuit which can realize accurate control of load current when PWM duty ratio is smaller.

In order to achieve the above object, the present invention provides an LED driving circuit comprising:

A driving main circuit module and a redundant current module;

the driving main circuit module comprises an input end, a control end and an output end; the input end is used for inputting control current, the control end is used for inputting a first PWM signal, and the output end is used for outputting load current; the load current is used for driving the LED to work;

When the first PWM signal is at a high level, the driving main circuit module establishes a working point; the driving main circuit module controls the output load current according to the control current and the duty ratio of the first PWM signal;

the redundant current module generates redundant current when the first PWM signal is at a low level, and maintains the working point of the driving main circuit module; the redundant current is turned off when the first PWM signal is high.

In an alternative, the driving main circuit module includes: the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the first switch, the second switch, the third switch and the first inverter;

the positive input end of the first operational amplifier is used for inputting the control current; the reverse input end of the first operational amplifier is used for inputting a reference voltage;

The grid electrode of the first MOS tube is connected with the grid electrode of the second MOS tube and is connected with the output end of the first operational amplifier;

The drain electrode of the first MOS tube is connected with the source electrode of the third MOS tube and the reverse input end of the second operational amplifier; the drain electrode of the third MOS tube is connected with the positive input end of the first operational amplifier; the grid electrode of the third MOS tube is connected with the output end of the second operational amplifier;

The positive input end of the second operational amplifier is connected with the drain electrode of the second MOS tube and the source electrode of the fourth MOS tube through the first switch; the drain electrode of the fourth MOS tube is used as the output end of the driving main circuit module;

the third switch is connected between the grid electrode of the fourth MOS tube and the output end of the first inverter, and the input end of the first inverter is used for inputting the first PWM signal;

One end of the second switch is connected with the grid electrode of the fourth MOS tube, and the other end of the second switch is connected with the reference ground or the power supply voltage;

The first PWM signal is used for controlling the on and off of the first switch, the second switch and the third switch.

In an alternative scheme, the first MOS tube and the second MOS tube are low-voltage tubes, and the third MOS tube and the fourth MOS tube are high-voltage tubes.

In the alternative scheme, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are PMOS tubes, the other end of the second switch is connected to the reference ground, and the sources of the first MOS tube and the second MOS tube are connected to the power supply voltage.

In the alternative scheme, the first MOS tube, the second MOS tube, the third MOS tube and the fourth MOS tube are NMOS tubes, the other end of the second switch is connected to the power supply voltage, and the sources of the first MOS tube and the second MOS tube are connected to the reference ground.

In an alternative, the redundant current module includes: the fifth MOS tube, the sixth MOS tube, the fourth switch, the fifth switch, the sixth switch and the second inverter;

The grid electrode of the fifth MOS tube is connected with the grid electrode of the first MOS tube; the drain electrode of the fifth MOS tube is connected with the source electrode of the sixth MOS tube; the drain electrode of the sixth MOS tube generates the redundant current;

the fourth switch is connected between the positive input end of the second operational amplifier and the source electrode of the sixth MOS tube;

The fifth switch is connected between the grid electrode of the sixth MOS tube and the output end of the second inverter, and the input end of the second inverter is used for inputting a second PWM signal;

One end of the sixth switch is connected with the grid electrode of the sixth MOS tube, and the other end of the sixth switch is connected with the reference ground or the power supply voltage;

The second PWM signal is used for controlling the on and off of the third switch, the fourth switch and the fifth switch.

In an alternative scheme, the fifth MOS tube and the sixth MOS tube are PMOS tubes, the other end of the sixth switch is connected to the reference ground, and the source electrode of the fifth MOS tube is connected to the power supply voltage.

In an alternative scheme, the fifth MOS tube and the sixth MOS tube are NMOS tubes, the other end of the sixth switch is connected to the power supply voltage, and the source electrode of the fifth MOS tube is connected to the reference ground.

In an alternative scheme, the fifth MOS tube is a low-voltage tube, and the sixth MOS tube is a high-voltage tube.

In an alternative scheme, when the first PWM signal is at a high level, the second PWM signal is at a low level; and the low level interval width of the second PWM signal covers the high level interval width of the first PWM signal.

The invention has the beneficial effects that:

The invention maintains the working state of the loop through the redundant current module, can increase the PWM dimming ratio, and can realize accurate current control when the duty ratio of the first PWM signal is smaller. The transient response characteristic of the LED driving circuit is improved.

Drawings

The foregoing and other objects, features and advantages of the invention will be apparent from the following more particular descriptions of exemplary embodiments of the invention as illustrated in the accompanying drawings wherein like reference numbers generally represent like parts throughout the exemplary embodiments of the invention.

Fig. 1 shows a simple LED driving circuit.

Fig. 2 shows an LED driving circuit with PWM control.

Fig. 3 shows an LED driving circuit with an operational amplifier.

Fig. 4 is a schematic diagram of an LED driving circuit according to an embodiment of the invention.

Fig. 5 is a waveform diagram illustrating an operation of the LED driving circuit according to an embodiment of the present invention.

Detailed Description

The invention is described in further detail below with reference to the drawings and the specific examples. The advantages and features of the present invention will become more apparent from the following description and drawings, however, it should be understood that the inventive concept may be embodied in many different forms and is not limited to the specific embodiments set forth herein. The drawings are in a very simplified form and are to non-precise scale, merely for convenience and clarity in aiding in the description of embodiments of the invention.

It will be understood that when an element or layer is referred to as being "on," "adjacent," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will be understood that, although the terms first, second, third, etc. may be used herein to describe various elements, components, regions, layers and/or sections, these elements, components, regions, layers and/or sections should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer or section from another element, component, region, layer or section. Thus, a first element, component, region, layer or section discussed below could be termed a second element, component, region, layer or section without departing from the teachings of the present invention.

Spatially relative terms, such as "under," "below," "beneath," "under," "above," "over," and the like, may be used herein for ease of description to describe one element or feature's relationship to another element or feature as illustrated in the figures. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use and operation in addition to the orientation depicted in the figures. For example, if the device in the figures is turned over, elements or features described as "under" or "beneath" other elements would then be oriented "on" the other elements or features. Thus, the exemplary terms "below" and "under" may include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or other orientations) and the spatially relative descriptors used herein interpreted accordingly.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the invention. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. As used herein, the term "and/or" includes any and all combinations of the associated listed items.

Example 1

Referring to fig. 4, the present embodiment provides an LED driving circuit including:

a drive main circuit module and a redundant current module 1;

The driving main circuit module comprises an input end, a control end and an output end; the input end is used for inputting a control current iref, the control end is used for inputting a first PWM signal PWM0, and the output end is used for outputting a load current iout; the load current iout is used for driving the LED to work;

When the first PWM signal PWM0 is at a high level, the driving main circuit module establishes a working point; the driving main circuit module controls the magnitude of the output load current iout according to the magnitude of the control current iref and the duty ratio of the first PWM signal PWM 0;

The redundant current module 1 generates redundant current idummy when the first PWM signal PWM0 is at a low level, and maintains the working point of the driving main circuit module; the redundant current idummy is turned off when the first PWM signal PWM0 is high.

Specifically, the driving main circuit module includes: the first operational amplifier op1, the second operational amplifier op2, the first MOS tube M0, the second MOS tube M1, the third MOS tube Mh0, the fourth MOS tube Mh1, the first switch S1, the second switch S2, the third switch S3 and the first inverter; the positive input end of the first operational amplifier op1 is used for inputting the control current iref; the reverse input end of the first operational amplifier op1 is used for inputting a reference voltage vref; the grid electrode of the first MOS tube M0 is connected with the grid electrode of the second MOS tube M1 and is connected with the output end of the first operational amplifier op 1; the drain electrode of the first MOS tube M0 is connected with the source electrode of the third MOS tube Mh0 and the reverse input end of the second operational amplifier op 2; the drain electrode of the third MOS tube Mh0 is connected to the positive input end of the first operational amplifier op 1; the grid electrode of the third MOS tube Mh0 is connected to the output end of the second operational amplifier op 2; the positive input end of the second operational amplifier op2 is connected to the drain electrode of the second MOS tube M1 and the source electrode of the fourth MOS tube Mh1 through the first switch S1; the drain electrode of the fourth MOS tube Mh1 is used as the output end of the driving main circuit module; the third switch S3 is connected between the gate of the fourth MOS transistor Mh1 and the output end of the first inverter, and the input end of the first inverter is used for inputting the first PWM signal PWM0; one end of the second switch S2 is connected to the grid electrode of the fourth MOS tube Mh1, and the other end of the second switch S is connected to the reference ground or the power supply voltage; the first PWM signal PWM0 is used to control the on and off of the first switch S1, the second switch S2, and the third switch S3.

In this embodiment, the redundant current module includes: the fifth MOS tube Md, the sixth MOS tube Mhd, the fourth switch S4, the fifth switch S5, the sixth switch S6 and the second inverter; the grid electrode of the fifth MOS tube Md is commonly connected with the grid electrode of the first MOS tube M0; the drain electrode of the fifth MOS tube Md is connected with the source electrode of the sixth MOS tube Mhd; the drain electrode of the sixth MOS tube Mhd generates the redundant current idummy, and the drain electrode of the sixth MOS tube Mhd can be connected with a reference ground or other circuits; the fourth switch S4 is connected between the positive input end of the second op2 and the source of the sixth MOS transistor Mhd; the fifth switch S5 is connected between the gate of the sixth MOS transistor Mhd and the output end of the second inverter, where the input end of the second inverter is used to input a second PWM signal PWMd; one end of the sixth switch S6 is connected to the grid electrode of the sixth MOS tube Mhd, and the other end of the sixth switch S6 is connected to the reference ground or the power supply voltage; the second PWM signal PWMd is used to control the on and off of the third switch S3, the fourth switch S4, and the fifth switch S5.

In this embodiment, the first MOS transistor M0, the second MOS transistor M1, and the fifth MOS transistor Md are all low-voltage transistors, and the third MOS transistor Mh0, the fourth MOS transistor Mh1, and the sixth MOS transistor Mhd are all high-voltage transistors. The low-voltage tube refers to a device with VDS withstand voltage less than or equal to 5V; the high-voltage tube refers to a device with VDS withstand voltage not less than 12V.

In this embodiment, the first MOS transistor M0, the second MOS transistor M1, the fifth MOS transistor Md, the third MOS transistor Mh0, the fourth MOS transistor Mh1, and the sixth MOS transistor Mhd are PMOS transistors, the other end of the second switch S2 is connected to the reference ground, and the sources of the first MOS transistor M0 and the second MOS transistor M1 are both connected to the supply voltage Vsupply; the other end of the sixth switch S6 is connected to the ground, and the source of the fifth MOS transistor Md is connected to the supply voltage Vsupply.

In another embodiment, the first MOS transistor M0, the second MOS transistor M1, the fifth MOS transistor Md, the third MOS transistor Mh0, the fourth MOS transistor Mh1, and the sixth MOS transistor Mhd are all NMOS transistors, the other end of the second switch S2 is connected to the supply voltage Vsupply, and the sources of the first MOS transistor M0 and the second MOS transistor M1 are all connected to the reference ground; the other end of the sixth switch S6 is connected to the supply voltage Vsupply, and the source of the fifth MOS transistor Md is connected to the reference ground.

Fig. 5 is a waveform diagram of the operation of the LED driving circuit in the present embodiment. When the first PWM signal PWM0 is at a high level, the second PWM signal PWMd is at a low level; and the low level interval width of the second PWM signal PWMd covers the high level interval width of the first PWM signal PWM 0; the first PWM signal PWM0 corresponds to the output load current iout when it is at a high level.

In this embodiment, the control current iref is a reference current, the load current iout is an LED driving current, the input reference voltage vref is used to ensure that the third MOS transistor Mh0 and the first MOS transistor M0 have sufficient channel voltages, the first op1 is used to drive 3 low-voltage PMOS transistors (the first MOS transistor M0, the second MOS transistor M1 and the fifth MOS transistor Md) to generate gate driving voltages of the low-voltage PMOS transistors, so that the output load current iout can obtain different load currents by adjusting the size of the second MOS transistor M1, and meanwhile, the second op2 is used to ensure that the drain voltages of the 3 low-voltage PMOS transistors are equal.

When the first PWM signal PWM0 is at a high level, the first switch S1 and the second switch S2 on the output driving branch are turned on, the third switch S3 is turned off, the loop establishes a working point, the output current iout is generated, the fourth switch S4 and the sixth switch S6 on the internal branch (the redundant current module 1) are turned off, the fifth switch S5 is turned on, and the redundant current idummy is turned off. When the first PWM signal PWM0 is at a low level, the first switch S1 and the second switch S2 on the output driving branch are turned off, the third switch S3 is turned on, the output load current iout is turned off, and simultaneously the fourth switch S4 and the sixth switch S6 on the internal branch are turned on, the fifth switch S5 is turned off, the redundant current idummy is generated, and the loop maintains the operating point.

When the first PWM signal PWM0 of the loop is turned off (when the falling edge arrives), the redundant current module 1 continues to operate to maintain the operating state of the loop, so that even if the minimum duty ratio of the first PWM signal PWM0 is reduced, since the operating point of the loop is continuously maintained by the redundant current module 1, when the next first PWM signal PWM0 is turned on (when the rising edge arrives), the load current iout can be quickly established, and thus the response speed and the power consumption requirements for the two operational amplifiers are greatly reduced.

According to the embodiment, the working state of the loop is maintained through the redundant current module, so that the PWM dimming ratio can be increased, and accurate current control can be realized when the duty ratio of the first PWM signal PWM0 is smaller. The transient response characteristic of the LED driving circuit is improved.

The above description is only illustrative of the preferred embodiments of the present invention and is not intended to limit the scope of the present invention, and any alterations and modifications made by those skilled in the art based on the above disclosure shall fall within the scope of the appended claims.

Claims

1. An LED driving circuit, comprising:

A driving main circuit module and a redundant current module;

2. The LED driving circuit of claim 1, wherein the driving main circuit module comprises: the first MOS transistor, the second MOS transistor, the third MOS transistor, the fourth MOS transistor, the first switch, the second switch, the third switch and the first inverter;

3. The LED driving circuit of claim 2, wherein the first MOS transistor and the second MOS transistor are low voltage transistors, and the third MOS transistor and the fourth MOS transistor are high voltage transistors.

4. The LED driving circuit of claim 2, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are PMOS transistors, the other end of the second switch is connected to a reference ground, and sources of the first MOS transistor and the second MOS transistor are connected to a supply voltage.

5. The LED driving circuit of claim 2, wherein the first MOS transistor, the second MOS transistor, the third MOS transistor, and the fourth MOS transistor are NMOS transistors, the other end of the second switch is connected to a supply voltage, and sources of the first MOS transistor and the second MOS transistor are connected to a reference ground.

6. The LED driving circuit of claim 2, wherein the redundant current module comprises: the fifth MOS tube, the sixth MOS tube, the fourth switch, the fifth switch, the sixth switch and the second inverter;

7. The LED driving circuit of claim 6, wherein the fifth MOS transistor and the sixth MOS transistor are PMOS transistors, the other end of the sixth switch is connected to the ground, and the source of the fifth MOS transistor is connected to the supply voltage.

8. The LED driving circuit of claim 6, wherein the fifth MOS transistor and the sixth MOS transistor are NMOS transistors, the other end of the sixth switch is connected to a supply voltage, and the source of the fifth MOS transistor is connected to a reference ground.

9. The LED driving circuit of claim 6, wherein the fifth MOS transistor is a low voltage transistor and the sixth MOS transistor is a high voltage transistor.

10. The LED driving circuit of claim 6, wherein when the first PWM signal is high, the second PWM signal is low; and the low level interval width of the second PWM signal covers the high level interval width of the first PWM signal.