CN118232911A - Frequency locking detection circuit and detection method - Google Patents
Frequency locking detection circuit and detection method Download PDFInfo
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Abstract
The invention relates to a frequency lock detection circuit and a detection method. The frequency lock detection circuit includes: the device comprises a first synchronization module, a second synchronization module, a counter, a latch module and a judgment module; the first synchronization module and the second synchronization module synchronize the reference clock signal and the output clock signal to the same clock domain and respectively output a first synchronization signal and a second synchronization signal; the counter calculates the phase difference of the first synchronous signal and the second synchronous signal; the latch module stores the phase difference of the first synchronous signal and the second synchronous signal in the last period; the judging module compares the phase difference of the first synchronous signal and the second synchronous signal in the period with the phase difference of the first synchronous signal and the second synchronous signal in the previous period; and judging whether the frequency is locked or not according to whether the difference exceeds a set error threshold value. The invention has the advantages of lower cost, lower power consumption and higher detection resolution.
Description
Technical Field
The invention relates to the technical field of circuits, in particular to a frequency locking detection circuit and a detection method.
Background
The phase-locked loop circuit is a circuit for realizing phase synchronization of an output signal and an input signal through feedback, and is widely applied to the technical fields of automatic control, broadcast communication, clock synchronization and the like. When the output signal of the phase-locked loop circuit is equal to the frequency of the input signal, the phase-locked loop circuit is considered to enter a frequency locked state. Whether the phase-locked loop circuit enters a frequency locking state can influence the accuracy and reliability of an output signal, thereby influencing the working stability of a next-stage system controlled by a clock signal output by the phase-locked loop circuit. If the phase-locked loop circuit does not achieve frequency locking, the frequency of its output signal may drift, resulting in degradation of the communication quality or unstable device performance of the next stage system. It is therefore of great importance to detect whether the phase-locked loop circuit is frequency locked.
In the prior art, the common principle of the frequency locking detection circuit is as follows: in a set time window, two counters are adopted to count the input signal and the output signal of the phase-locked loop circuit respectively; comparing the difference between the count values of the two counters; if the difference value of the two count values exceeds the set threshold value, the frequency difference between the input signal and the output signal is considered to be too large, and the phase-locked loop circuit is not locked (out-of-lock); if the difference between the two count values is less than the set threshold, the frequency difference between the input signal and the output signal is considered to be sufficiently small, and the phase-locked loop circuit is already frequency locked.
The frequency lock detection circuit in the prior art has the following defects: 1. two counters are required and the cost is high. 2. Under the condition of higher required detection precision, more hardware resources are required to be consumed, the detection time is long, the counter bit width is large, and the circuit power consumption is large.
Disclosure of Invention
Based on this, it is an object of the present invention to provide a frequency lock detection circuit and a detection method, which have the advantage of achieving a higher detection resolution with lower cost, lower power consumption, shorter detection time.
The invention provides a frequency lock detection circuit, comprising: the device comprises a first synchronization module, a second synchronization module, a counter, a latch module and a judgment module; the first synchronization module and the second synchronization module are used for synchronizing the reference clock signal and the output clock signal to the same clock domain and respectively outputting a first synchronization signal and a second synchronization signal; the counter is used for calculating a phase difference diff (n) of the first synchronous signal and the second synchronous signal in one period according to the first synchronous signal and the second synchronous signal; the latch module is used for storing a phase difference diff (n-1) of the first synchronous signal and the second synchronous signal calculated by the counter in the last period; the judging module is used for comparing the phase difference diff (n) of the first synchronous signal and the second synchronous signal, which are calculated by the counter in the period, with the phase difference diff (n-1) of the first synchronous signal and the second synchronous signal in the last period stored by the latching module; and judging whether the frequency is locked or not according to whether the difference value |diff (n) -diff (n-1) | exceeds a set error threshold value.
The invention can directly obtain the phase difference between the reference signal and the signal to be detected through one counter without respectively calculating the periods of the reference signal and the signal to be detected by two counters and obtaining the phase difference by making the difference. The invention can obtain more accurate detection results by detecting at least two adjacent periods without setting a very long time window. The counter and the latch of the invention only need to record one data, and the occupied data bit width is small. Therefore, the invention realizes higher detection resolution and higher cost performance with lower cost, lower power consumption and shorter detection time.
Further, the device also comprises a first frequency division module and a second frequency division module; the first frequency dividing module is used for dividing the frequency of the output clock signal to obtain a first frequency dividing signal; the second frequency division module is used for dividing the frequency of the reference clock signal to obtain a second frequency division signal; the first frequency dividing module and the second frequency dividing module are used for dividing frequency, and the frequency dividing ratios of the frequency dividing are equal; the first synchronization module and the second synchronization module are used for synchronizing the first frequency division signal and the second frequency division signal to the same clock domain and respectively outputting a first synchronization signal and a second synchronization signal.
Further, when the falling edge of the first synchronous signal is arrived and the falling edge of the second synchronous signal is not arrived, the frequency locking detection circuit is in a LATCH state; in the LATCH state, the counter counts; when the falling edge of the second synchronous signal is arrived and the falling edge of the next first synchronous signal is not arrived, the frequency locking detection circuit is in a HOLD state; in the HOLD state, the latch module HOLDs a phase difference diff (1) of the first and second synchronization signals in the 1 st cycle; when the falling edge of the next first synchronous signal is arrived and the falling edge of the next second synchronous signal is not arrived, the frequency locking detection circuit is in a COMPARE state; in the COMPARE state, the counter recommends counting from 0; at the end of the COMPARE state, the decision module COMPAREs the phase difference diff (2) between the first synchronization signal and the second synchronization signal calculated by the counter in this period with the phase difference diff (2) -diff (1) between the phase differences diff (1) between the first synchronization signal and the second synchronization signal in the last period stored by the latch module; and judges whether the difference |diff (2) -diff (1) | exceeds a set error threshold.
Further, when the COMPARE state is finished, if the decision module decides that the difference |diff (2) -diff (1) | exceeds a set error threshold, outputting an out-of-lock signal; and outputting a locking signal if the difference value |diff (2) -diff (1) | is smaller than a set error threshold value.
Further, when the COMPARE state is finished, if the decision module decides that the difference |diff (2) -diff (1) | exceeds a set error threshold, resetting the lock reference value, and waiting for the next lock detection; and if the difference value |diff (2) -diff (1) | is smaller than the set error threshold value, adding 1 to the locking reference value, and re-entering the HOLD state.
Further, when the COMPARE state is finished, if the decision module decides that the difference |diff (n) -diff (n-1) | is smaller than a set error threshold, adding 1 to the lock reference value; judging whether the locking reference value exceeds a set convergence threshold value or not; and if the locking reference value is smaller than the set convergence threshold value, re-entering the HOLD state.
Further, when the COMPARE state is finished, if the decision module decides that the difference |diff (n) -diff (n-1) | is smaller than a set error threshold, adding 1 to the lock reference value; judging whether the locking reference value exceeds a set convergence threshold value or not; and outputting a locking signal if the locking reference value exceeds a set convergence threshold value.
Based on the same inventive concept, the invention also provides a frequency lock detection method, comprising the following steps: synchronizing the reference clock signal and the output clock signal to the same clock domain, and respectively outputting a first synchronizing signal and a second synchronizing signal; calculating a phase difference diff (n) of the first and second synchronization signals in one period according to the first and second synchronization signals; saving a phase difference diff (n-1) of the first and second synchronization signals in a previous period; comparing a difference value of a phase difference diff (n) of the first and second synchronization signals in the one period with a phase difference diff (n-1) of the first and second synchronization signals in the previous period; and judging whether the frequency is locked or not according to whether the difference value |diff (n) -diff (n-1) | exceeds a set error threshold value.
Further, the method further comprises the steps of: dividing the frequency of the output clock signal to obtain a first frequency-divided signal; dividing the frequency of the reference clock signal to obtain a second frequency-divided signal; the frequency dividing ratio of the frequency division is equal to that of the output clock signal and the reference clock signal; the step of generating the first synchronization signal and the second synchronization signal becomes: generating a first synchronization signal according to the first frequency division signal; and generating a second synchronous signal according to the second frequency division signal.
Further, when the falling edge of the first synchronous signal is arrived and the falling edge of the second synchronous signal is not arrived, the LATCH state is entered; calculating a phase difference diff (1) of the first and second synchronization signals in one period according to the first and second synchronization signals in a LATCH state; entering a HOLD state when a falling edge of a second synchronization signal has arrived and a falling edge of a next first synchronization signal has not arrived; in the HOLD state, saving a phase difference diff (1) of the first and second synchronization signals in the 1 st period; when the falling edge of the next first synchronous signal arrives and the falling edge of the next second synchronous signal does not arrive, the method enters a COMPARE state; calculating a phase difference diff (2) of the first and second synchronization signals in one period based on the first and second synchronization signals again in the COMPARE state; at the end of the COMPARE state, comparing the phase difference diff (2) of the first and second synchronization signals in this period with the difference |diff (2) -diff (1) | of the phase difference diff (1) of the first and second synchronization signals in the previous period; and judges whether the difference |diff (2) -diff (1) | exceeds a set error threshold.
For a better understanding and implementation, the present invention is described in detail below with reference to the drawings.
Drawings
FIG. 1 is a block diagram of a frequency lock detection circuit according to the present invention;
FIG. 2 is a schematic diagram of a state machine jump flow of the frequency lock detection circuit according to the embodiment 1 of the present invention;
FIG. 3 is a timing diagram of the frequency lock detection circuit according to the embodiment 1 of the present invention for performing a single lock detection;
FIG. 4 is a state machine jump flow diagram of the frequency lock detection circuit of the embodiment 2 of the present invention;
Fig. 5 is a timing diagram of the frequency lock detection circuit in embodiment 2 of the present invention during N-cycle lock detection.
Detailed Description
The inventive concept of the frequency lock detection circuit of the present invention is: only one counter is used for counting the phase difference between the reference signal and the signal to be detected, and a latch is used for storing the count value of the previous period; the difference diff of the count value of this one cycle and the count value of the last cycle held by the latch is compared. In case the phase locked loop circuit is already frequency locked, the phase difference between the reference signal and the signal to be detected should be fixed, i.e. the count value of this one period should be equal to the count value of the last period held by the latch, i.e. the difference diff should approach 0. It is thus possible to detect whether the phase-locked loop circuit is frequency locked by determining whether the difference diff is smaller than the set convergence threshold Err.
Referring to fig. 1, fig. 1 is a block diagram of a frequency lock detection circuit according to the present invention. The frequency locking detection circuit is used for detecting whether a phase-locked loop circuit is locked in frequency and comprises a first frequency division module 1, a second frequency division module 2, a first synchronization module 3, a second synchronization module 4, a counter 5, a latch module 6 and a judgment module 7.
The input signal of the phase-locked loop circuit is a reference clock signal refclk, and the output signal is an output clock signal vcoclk. Detecting whether the phase-locked loop circuit is frequency locked refers to detecting whether the difference between the frequencies of the reference clock signal refclk and the output clock signal vcoclk is within a set error range.
The first frequency division module 1 is configured to divide the output clock signal vcoclk to obtain a first frequency division signal dvco. The second frequency division module 2 is configured to divide the frequency of the reference clock signal refclk to obtain a second frequency division signal dref. The first frequency dividing module 1 and the second frequency dividing module 2 are equal in frequency dividing ratio.
The purpose of the first frequency dividing module 1 and the second frequency dividing module 2 dividing the reference clock signal refclk and the output clock signal vcoclk is to reduce the frequency of the signals, thereby reducing the circuit power consumption. In other embodiments where the signal frequency is not high, the first frequency dividing module and the second frequency dividing module may not be used, so that the reference clock signal refclk and the output clock signal vcoclk are directly input to the first synchronization module and the second synchronization module, respectively. The person skilled in the art can adjust the frequency dividing ratio of the first frequency dividing module and the second frequency dividing module according to the actual frequency of the signal and the precision of the counter.
The first synchronization module 3 and the second synchronization module 4 are configured to synchronize the first frequency division signal dvco and the second frequency division signal dref to the same clock domain, and output a first synchronization signal fvco and a second synchronization signal fref respectively. The first synchronization signal fvco and the second synchronization signal fref are both synchronized with the working clock of the counter.
The reference clock signal refclk and the output clock signal vcoclk, and the first divided signal dvco and the second divided signal fvco after frequency division are asynchronous signals, and such asynchronous signals are output to the counter without being subjected to synchronous processing, which may cause a functional error of the counter. It is therefore necessary to synchronize the asynchronous first and second divided signals dvco and fvco (or the reference clock signal refclk and the output clock signal vcoclk) under the clock domain of the working clock of the counter by means of the first and second synchronization modules 3 and 4, thereby circumventing the problems caused by asynchronous signals.
The counter 5 is configured to calculate a phase difference diff (n) between the first synchronization signal fvco and the second synchronization signal fref in one period according to the first synchronization signal fvco and the second synchronization signal fref.
The latch module 6 is configured to store a phase difference diff (n-1) between the first synchronization signal fvco and the second synchronization signal fref calculated by the counter in a previous period.
The decision module 7 is configured to compare a difference value between a phase difference diff (n) of the first synchronization signal fvco and the second synchronization signal fref calculated by the counter in the period and a phase difference diff (n-1) of the first synchronization signal fvco and the second synchronization signal fref in the previous period stored by the latch module; and judging whether the frequency is locked or not according to whether the difference value |diff (n) -diff (n-1) | exceeds a set error threshold Err.
Example 1
In embodiment 1, the frequency lock detection circuit of the present invention performs single lock detection. Referring to fig. 2 and 3, fig. 2 is a state machine jump flow diagram of the frequency lock detection circuit of embodiment 1 of the present invention, and fig. 3 is a timing diagram of the frequency lock detection circuit of embodiment 1 of the present invention in performing a single lock detection.
When single lock detection is carried out, the state machine jump flow of the frequency lock detection circuit is as follows:
① IDLE state: initially in the IDLE state. In the IDLE state, frequency lock detection is waited.
② LATCH state: the LATCH state is in a state where the falling edge of the first synchronization signal fvco has arrived and the falling edge of the second synchronization signal fref has not arrived. In the LATCH state, the counter counts. At the end of the LATCH state, the count value of the counter is the phase difference diff (1) between the first synchronization signal fvco and the second synchronization signal fref in the 1 st period.
③ HOLD state: when the falling edge of the second synchronization signal fref has arrived and the falling edge of the next first synchronization signal fvco has not arrived, the HOLD state is set. In the HOLD state, the latch module HOLDs the phase difference diff (1) of the first and second synchronization signals fvco and fref in the previous cycle (i.e., the 1 st cycle).
④ COMPARE state: the COMPARE state is in when the falling edge of the next first synchronization signal fvco has arrived and the falling edge of the next second synchronization signal fref has not arrived. In the COMPARE state, the counter counts back from 0. At the end of the COMPARE state, the count value of the counter is the phase difference diff (2) between the first synchronization signal fvco and the second synchronization signal fref in the 2 nd period.
When the COMPARE state is finished, the decision module COMPAREs the phase difference diff (2) of the first synchronization signal fvco and the second synchronization signal fref calculated by the counter in the one period (i.e. the 2 nd period) with the difference |diff (2) -diff (1) | of the phase difference diff (1) of the first synchronization signal fvco and the second synchronization signal fref in the last period (i.e. the 1 st period) stored by the latch module; and judging whether the difference value |diff (2) -diff (1) | exceeds a set error threshold value Err; and if the difference value |diff (2) -diff (1) | exceeds a set error threshold Err, outputting an unlocking signal, and re-entering an IDLE state.
⑤ LOCKED state: and if the judging module judges that the difference value |diff (2) -diff (1) | is smaller than the set error threshold Err, entering a LOCKED state. And in the LOCKED state, the judging module outputs a locking signal to finish frequency locking detection.
Example 2
In embodiment 2, the frequency lock detection circuit of the present invention performs N-cycle lock detection. Referring to fig. 4 and fig. 5, fig. 4 is a state machine jump flow diagram of the frequency lock detection circuit of embodiment 2 of the present invention, and fig. 5 is a timing diagram of the frequency lock detection circuit of embodiment 2 of the present invention in performing N cycle lock detection.
When the loop lock detection is carried out for N times, the state machine jump flow of the frequency lock detection circuit is as follows:
① IDLE state: initially in the IDLE state. In the IDLE state, frequency lock detection is waited.
② LATCH state: when the falling edge of the 1 st first synchronization signal fvco arrives and the falling edge of the 1 st second synchronization signal fref does not arrive, the LATCH state is set. In the LATCH state, the counter counts. At the end of the LATCH state, the count value of the counter is the phase difference diff (1) between the first synchronization signal fvco and the second synchronization signal fref in the 1 st period.
③ HOLD state: when the falling edge of the 1 st second synchronization signal fref has arrived and the falling edge of the 2 nd first synchronization signal fvco has not arrived, the HOLD state is set. In the HOLD state, the latch module HOLDs the phase difference diff (1) of the first and second synchronization signals fvco and fref in the previous cycle (i.e., the 1 st cycle).
④ COMPARE state: the COMPARE state is set when the falling edge of the 2 nd first synchronization signal fvco has arrived and the falling edge of the 2 nd second synchronization signal fref has not arrived. In the COMPARE state, the counter counts back from 0. At the end of the COMPARE state, the count value of the counter is the phase difference diff (2) between the first synchronization signal fvco and the second synchronization signal fref in the 2 nd period.
When the COMPARE state is finished, the decision module COMPAREs the phase difference diff (2) of the first synchronization signal fvco and the second synchronization signal fref calculated by the counter in the one period (i.e. the 2 nd period) with the difference |diff (2) -diff (1) | of the phase difference diff (1) of the first synchronization signal fvco and the second synchronization signal fref in the last period (i.e. the 1 st period) stored by the latch module; and judges whether the difference |diff (2) -diff (1) | exceeds a set error threshold Err.
If the difference value |diff (2) -diff (1) | exceeds a set error threshold Err, outputting a lock losing signal, resetting a locking reference value i, and re-entering an IDLE state;
if the difference value |diff (2) -diff (1) | is smaller than the set error threshold value Err, outputting a locking signal, adding 1 to the locking reference value i, and re-entering the HOLD state.
⑤ HOLD state: when the falling edge of the 2 nd second synchronization signal fref has arrived and the falling edge of the 3 rd first synchronization signal fvco has not arrived, the HOLD state is set. In the HOLD state, the latch module HOLDs the phase difference diff (2) of the first and second synchronization signals fvco and fref in the previous cycle (i.e., the 2 nd cycle).
⑥ COMPARE state: the COMPARE state is in the 3 rd first synchronization signal fvco falling edge and the 3 rd second synchronization signal fref falling edge. In the COMPARE state, the counter restarts counting from 0. At the end of the COMPARE state, the count value of the counter is the phase difference diff (3) between the first synchronization signal fvco and the second synchronization signal fref in the 3 rd period.
When the COMPARE state is finished, the decision module COMPAREs the phase difference diff (3) of the first synchronization signal fvco and the second synchronization signal fref calculated by the counter in the 3 rd period with the difference |diff (3) -diff (2) | of the phase difference diff (2) of the first synchronization signal fvco and the second synchronization signal fref in the last period (i.e. the 2 nd period) stored by the latch module; and judging whether the difference value |diff (3) -diff (2) | exceeds a set error threshold value Err;
If the difference value |diff (3) -diff (2) | exceeds a set error threshold Err, resetting the locking reference value i, and re-entering an IDLE state;
If the difference value |diff (3) -diff (2) | is smaller than the set error threshold Err, adding 1 to the locking reference value i; judging whether the locking reference value i exceeds a set convergence threshold N; if the lock reference value i is smaller than the set convergence threshold N, the HOLD state shown by symbol ⑦ in fig. 5 is re-entered.
And if the locking reference value i exceeds the set convergence threshold value N, entering a LOCKED state. When the LOCKED state is entered, the frequency lock detection is ended.
The frequency lock detection circuit of embodiment 2 of the present invention is configured to cycle into HOLD and COMPARE states when performing N cycle lock detection. And after the completion of each COMPARE state, assigning a value to the locking reference value i according to the locking detection result. If the differences |diff (N) -diff (N-1) | of the phase differences of two adjacent periods in N consecutive times are smaller than the set error threshold Err, it is indicated that the synchronicity of the output clock signals of the phase-locked loop circuit has been met, i.e. the phase-locked loop circuit has been frequency locked. At this time, the lock reference value i is accumulated to N, and enters a LOCKED state, thereby ending the frequency lock detection. If the difference |diff (n) -diff (n-1) | of the phase difference between two adjacent periods exceeds the set error threshold Err in any one lock detection, it is indicated that the synchronicity of the output clock signals of the phase-locked loop circuit is not satisfied yet, that is, the phase-locked loop circuit is not locked in frequency yet. At this time, the lock reference value i is cleared, and the IDLE state is re-entered, and the next lock detection is waited.
The relationship between the resolution, the detection duration, and the frequency division ratio of the frequency lock detection circuit of embodiment 2 of the present invention will be exemplified as follows:
Assuming that the frequency of the reference clock signal refclk is 24MHz, the frequency of the output clock signal vcoclk to be detected is about 24MHz. The frequency divider has a division ratio Ndiv of 64, a convergence threshold N of 64, and an error threshold Err of 124 MHz clock cycle. Then, the shortest total time period (i.e., detection time period) required to complete the N number of cyclic lock detections is 4096 (ndiv=64×64=4096) 24MHz clock cycles. The first divided signal dvco and the first synchronization signal fvco have a frequency of 375kHz (24 MHz/64=375 kHz). Since the deviation |diff (n) -diff (n-1) | of the count value diff (n) of the counter from the latch value diff (n-1) of the latch module is smaller than 124 MHz clock period in 375kHz clock period of each detection round, the frequency lock is judged. The frequency resolution is thus 0.09kHz (375×err/(ndiv×n) =375×1/64/64×0.09 kHz).
If resolution needs to be increased, the division ratio of the divider can be increased. For example, assuming that the frequency division ratio Ndiv becomes 128, the detection period becomes 8192 (ndiv×n=64×128=8192) 24MHz clock periods; the resolution becomes 0.045kHz (375×err/(ndiv×n) =375×1/128/64×0.045 kHz). It can be seen that the division ratio Ndiv is doubled, the detection duration is doubled, and the resolution is doubled.
If the detection duration needs to be shortened, the frequency dividing ratio of the frequency divider can be reduced. For example, assuming that the frequency division ratio Ndiv becomes 32, the detection period becomes 2048 (ndiv×n=64×32=2048) 24MHz clock cycles; the resolution becomes 0.18kHz (375×err/(ndiv×n) =375×1/32/64×0.18 kHz). It can be seen that the frequency division ratio Ndiv is reduced by half, the detection duration is reduced by half, and the resolution is also reduced by half.
The invention has the following technical effects: the invention can directly obtain the phase difference between the reference signal and the signal to be detected through one counter without respectively calculating the periods of the reference signal and the signal to be detected by two counters and obtaining the phase difference by making the difference. The invention can obtain more accurate detection results by detecting at least two adjacent periods without setting a very long time window. The counter and the latch of the invention only need to record one data, and the occupied data bit width is small. In summary, the frequency locking detection circuit and the detection method of the invention realize higher detection resolution and higher cost performance with lower cost, lower power consumption and shorter detection time.
The above examples illustrate only a few embodiments of the invention, which are described in detail and are not to be construed as limiting the scope of the invention. It should be noted that modifications and improvements can be made by those skilled in the art without departing from the spirit of the invention, and the invention is intended to encompass such modifications and improvements.
Claims (10)
1. A frequency lock detection circuit, comprising:
The device comprises a first synchronization module, a second synchronization module, a counter, a latch module and a judgment module;
The first synchronization module and the second synchronization module are used for synchronizing the reference clock signal and the output clock signal to the same clock domain and respectively outputting a first synchronization signal and a second synchronization signal;
the counter is used for calculating a phase difference diff (n) of the first synchronous signal and the second synchronous signal in one period according to the first synchronous signal and the second synchronous signal;
The latch module is used for storing a phase difference diff (n-1) of the first synchronous signal and the second synchronous signal calculated by the counter in the last period;
The judging module is used for comparing the phase difference diff (n) of the first synchronous signal and the second synchronous signal, which are calculated by the counter in the period, with the phase difference diff (n-1) of the first synchronous signal and the second synchronous signal in the last period stored by the latching module; and judging whether the frequency is locked or not according to whether the difference value |diff (n) -diff (n-1) | exceeds a set error threshold value.
2. The frequency lock detection circuit of claim 1, wherein:
The device also comprises a first frequency division module and a second frequency division module; the first frequency dividing module is used for dividing the frequency of the output clock signal to obtain a first frequency dividing signal; the second frequency division module is used for dividing the frequency of the reference clock signal to obtain a second frequency division signal; the first frequency dividing module and the second frequency dividing module are used for dividing frequency, and the frequency dividing ratios of the frequency dividing are equal;
the first synchronization module and the second synchronization module are used for synchronizing the first frequency division signal and the second frequency division signal to the same clock domain and respectively outputting a first synchronization signal and a second synchronization signal.
3. The frequency lock detection circuit according to claim 2, wherein:
When the falling edge of the first synchronous signal arrives and the falling edge of the second synchronous signal does not arrive, the frequency locking detection circuit is in a LATCH state; in the LATCH state, the counter counts;
When the falling edge of the second synchronous signal is arrived and the falling edge of the next first synchronous signal is not arrived, the frequency locking detection circuit is in a HOLD state; in the HOLD state, the latch module HOLDs a phase difference diff (1) of the first and second synchronization signals in the 1 st cycle;
When the falling edge of the next first synchronous signal is arrived and the falling edge of the next second synchronous signal is not arrived, the frequency locking detection circuit is in a COMPARE state; in the COMPARE state, the counter recommends counting from 0;
At the end of the COMPARE state, the decision module COMPAREs the phase difference diff (2) between the first synchronization signal and the second synchronization signal calculated by the counter in this period with the phase difference diff (2) -diff (1) between the phase differences diff (1) between the first synchronization signal and the second synchronization signal in the last period stored by the latch module; and judges whether the difference |diff (2) -diff (1) | exceeds a set error threshold.
4. A frequency lock detection circuit according to claim 3, wherein:
When the COMPARE state is finished, if the judging module judges that the difference value |diff (2) -diff (1) | exceeds a set error threshold value, outputting an unlocking signal; and outputting a locking signal if the difference value |diff (2) -diff (1) | is smaller than a set error threshold value.
5. A frequency lock detection circuit according to claim 3, wherein:
when the COMPARE state is finished, if the judging module judges that the difference value |diff (2) -diff (1) | exceeds a set error threshold value, resetting the locking reference value, and waiting for the next locking detection; and if the difference value |diff (2) -diff (1) | is smaller than the set error threshold value, adding 1 to the locking reference value, and re-entering the HOLD state.
6. The frequency lock detection circuit of claim 5, wherein:
When the COMPARE state is finished, if the judging module judges that the difference value |diff (n) -diff (n-1) | is smaller than a set error threshold value, adding 1 to the locking reference value; judging whether the locking reference value exceeds a set convergence threshold value or not; and if the locking reference value is smaller than the set convergence threshold value, re-entering the HOLD state.
7. The frequency lock detection circuit of claim 6, wherein:
When the COMPARE state is finished, if the judging module judges that the difference value |diff (n) -diff (n-1) | is smaller than a set error threshold value, adding 1 to the locking reference value; judging whether the locking reference value exceeds a set convergence threshold value or not; and outputting a locking signal if the locking reference value exceeds a set convergence threshold value.
8. A frequency lock detection method, comprising the steps of:
Synchronizing the reference clock signal and the output clock signal to the same clock domain, and respectively outputting a first synchronizing signal and a second synchronizing signal;
calculating a phase difference diff (n) of the first and second synchronization signals in one period according to the first and second synchronization signals;
Saving a phase difference diff (n-1) of the first and second synchronization signals in a previous period;
Comparing a difference value of a phase difference diff (n) of the first and second synchronization signals in the one period with a phase difference diff (n-1) of the first and second synchronization signals in the previous period; and judging whether the frequency is locked or not according to whether the difference value |diff (n) -diff (n-1) | exceeds a set error threshold value.
9. The frequency lock detection method according to claim 8, wherein:
the method also comprises the steps of: dividing the frequency of the output clock signal to obtain a first frequency-divided signal; dividing the frequency of the reference clock signal to obtain a second frequency-divided signal; the frequency dividing ratio of the frequency division is equal to that of the output clock signal and the reference clock signal;
The step of generating the first synchronization signal and the second synchronization signal becomes: generating a first synchronization signal according to the first frequency division signal; and generating a second synchronous signal according to the second frequency division signal.
10. The frequency lock detection method according to claim 9, wherein:
when the falling edge of the first synchronous signal arrives and the falling edge of the second synchronous signal does not arrive, entering a LATCH state; calculating a phase difference diff (1) of the first and second synchronization signals in one period according to the first and second synchronization signals in a LATCH state;
entering a HOLD state when a falling edge of a second synchronization signal has arrived and a falling edge of a next first synchronization signal has not arrived; in the HOLD state, saving a phase difference diff (1) of the first and second synchronization signals in the 1 st period;
When the falling edge of the next first synchronous signal arrives and the falling edge of the next second synchronous signal does not arrive, the method enters a COMPARE state; calculating a phase difference diff (2) of the first and second synchronization signals in one period based on the first and second synchronization signals again in the COMPARE state;
At the end of the COMPARE state, comparing the phase difference diff (2) of the first and second synchronization signals in this period with the difference |diff (2) -diff (1) | of the phase difference diff (1) of the first and second synchronization signals in the previous period; and judges whether the difference |diff (2) -diff (1) | exceeds a set error threshold.
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