CN118231465A - Semiconductor power device - Google Patents
Semiconductor power device Download PDFInfo
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- CN118231465A CN118231465A CN202211652272.0A CN202211652272A CN118231465A CN 118231465 A CN118231465 A CN 118231465A CN 202211652272 A CN202211652272 A CN 202211652272A CN 118231465 A CN118231465 A CN 118231465A
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- power device
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 53
- 210000000746 body region Anatomy 0.000 claims abstract description 46
- 239000002184 metal Substances 0.000 claims abstract description 28
- 230000004888 barrier function Effects 0.000 claims description 3
- 239000010410 layer Substances 0.000 description 34
- 238000000034 method Methods 0.000 description 8
- 238000011084 recovery Methods 0.000 description 5
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- 239000003990 capacitor Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
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- Junction Field-Effect Transistors (AREA)
Abstract
The embodiment of the invention provides a semiconductor power device, which comprises: an n-type semiconductor layer; a plurality of p-type pillars within the n-type semiconductor layer; the p-type body region is positioned in the n-type semiconductor layer and positioned at the top of the p-type column, and an n-type source region is arranged in the p-type body region; a gate structure recessed in the n-type semiconductor layer for controlling the opening and closing of a current channel, wherein the gate structure comprises a gate dielectric layer and a gate; the clamping gate is recessed in the p-type body region and is isolated from the p-type body region through a first gate dielectric layer; and the source metal layer is electrically connected with the n-type source region and the clamping gate, and a p-n junction diode structure is formed between the source metal layer and the p-type body region.
Description
Technical Field
The invention belongs to the technical field of semiconductor power devices, and particularly relates to a semiconductor power device.
Background
When the semiconductor power device in the prior art is turned off, when the drain-source voltage Vds is smaller than 0V, the parasitic body diode in the semiconductor power device is in a forward bias state, reverse current flows from the source to the drain through the body diode, at this time, the current of the body diode has the phenomenon of injecting minority carrier, and the minority carrier is reverse recovered when the semiconductor power device is turned on again, so that larger reverse recovery current is caused, and the reverse recovery time is long. At present, the method for improving the reverse recovery speed of the semiconductor power device comprises the following steps: the semiconductor power device is connected in parallel with the SiC schottky diode, and at this time, in order to inhibit the reverse recovery current from flowing from the semiconductor power device, the forward conduction voltage drop Vfsd of the diode needs to be improved, which increases the miller platform voltage of the semiconductor power device in the starting process, and requires a high gate driving voltage when in use.
Disclosure of Invention
In view of the above, the present invention is directed to a semiconductor power device, which increases the reverse recovery speed without increasing the miller stage voltage during switching, thereby eliminating the need for additional gate driving voltage.
The embodiment of the invention provides a semiconductor power device, which comprises:
An n-type semiconductor layer;
a plurality of p-type pillars within the n-type semiconductor layer;
The p-type body region is positioned in the n-type semiconductor layer and positioned at the top of the p-type column, and an n-type source region is arranged in the p-type body region;
A gate structure recessed in the n-type semiconductor layer for controlling the opening and closing of a current channel, wherein the gate structure comprises a gate dielectric layer and a gate;
the clamping gate is recessed in the p-type body region and is isolated from the p-type body region through a first gate dielectric layer;
And the source metal layer is electrically connected with the n-type source region and the clamping gate, and a p-n junction diode structure is formed between the source metal layer and the p-type body region.
Optionally, the source metal layer contacts the p-type body region to form a schottky barrier diode structure; or an n-type doped region is arranged in the p-type body region, the p-type body region and the n-type doped region form a p-n junction diode structure, and the source electrode metal layer is electrically connected with the n-type doped region.
Optionally, in the length direction of the current channel, a contact region between the source metal layer and the p-type body region is located between the n-type source region and the clamp gate, and the n-type doped region is located between the n-type source region and the clamp gate.
Optionally, in the width direction of the current channel, a contact region between the source metal layer and the p-type body region is located at one side or two sides of the clamping gate, and the n-type doped region is located at one side or two sides of the clamping gate.
Optionally, the bottom of the clamping gate is located in the p-type body region or extends down into the p-type column.
According to the semiconductor power device, the clamping grid structure is formed in the p-type body region, the clamping grid is connected with the source voltage outside the source metal layer in an outward mode, charges of the semiconductor power device in the starting process can be coupled, the p-type body region is clamped at zero potential, further charging of a Miller capacitor in the starting process is not affected, the voltage of a Miller platform is reduced, and therefore the grid driving voltage is not required to be additionally increased in the application process.
Drawings
In order to more clearly illustrate the technical solution of the exemplary embodiments of the present invention, a brief description is given below of the drawings required for describing the embodiments.
Fig. 1 is a schematic cross-sectional structure along a length direction of a current channel of a first embodiment of a semiconductor power device of the present invention;
Fig. 2 and 3 are schematic cross-sectional structures of a second embodiment of the semiconductor power device of the present invention;
Fig. 4 is a schematic cross-sectional structure of a third embodiment of the semiconductor power device of the present invention.
Detailed Description
In order to make the objects, technical solutions and advantages of the present invention more apparent, the technical solutions of the present invention will be fully described below by way of specific modes with reference to the accompanying drawings in the embodiments of the present invention.
Fig. 1 is a schematic cross-sectional structure along the length direction of a current channel of a first embodiment of a semiconductor power device according to the present invention, and the current channel is not described in detail in the embodiment of the present invention as a common sense structure. As shown in fig. 1, the semiconductor power device of the present invention includes an n-type semiconductor layer 21, the material of the n-type semiconductor layer 21 is typically silicon and is formed on an n-type silicon substrate 20, and the n-type silicon substrate 20 may serve as an n-type drain region of the semiconductor power device.
A plurality of p-type pillars 22 are located within the n-type semiconductor layer 21, two p-type pillars 22 being shown by way of example only in the embodiment shown in fig. 1, the number of p-type pillars 22 being set in accordance with the specific specifications of the semiconductor power device. A p-type body region 23 located within the n-type semiconductor layer 21 and atop the p-type pillar 22, and an n-type source region 24 located within the p-type body region 23.
A gate structure recessed in the n-type semiconductor layer 21 for controlling the turning on and off of a current channel, the gate structure including a gate dielectric layer 27 and a gate 28;
Clamp gate 26 recessed within p-type body region 23, the bottom of clamp gate 26 may be located within p-type body region 23, or may extend down into p-type column 22, as exemplified by the bottom of clamp gate 26 extending down into p-type column 22 in fig. 1. The clamp gate 26 is isolated from the p-type body region 23 by a first gate dielectric layer 25.
A source metal layer 30 electrically connected to the n-type source region 24 and the clamp gate 26, and an interlayer insulating layer 29 for isolating the source metal layer 30 from a gate metal layer (not shown in fig. 1 based on a positional relationship of the cross section). A p-n junction diode structure is formed between the source metal layer 30 and the p-type body region 23, and preferably, the source metal layer 30 is in direct contact with the p-type body region 23 to form a schottky barrier diode structure, so as to simplify the structure and manufacturing process of the semiconductor power device. In fig. 1, the contact area of the source metal layer 30 and the p-type body region 23 is located between the n-type source region 24 and the clamp gate 26 in the length direction of the current channel.
Fig. 2 and 3 are schematic cross-sectional structures of a second embodiment of the semiconductor power device provided in the present invention, fig. 2 is a schematic cross-sectional structure along a length direction of a current channel, fig. 3 is a schematic cross-sectional structure along a width direction of the current channel, the semiconductor power device shown in fig. 2 and 3 is different from the semiconductor super power device shown in fig. 1 in that, in the length direction of the current channel, a contact region between a clamp gate 26 and an n-type source region 24 is not provided, a contact region between the source metal layer 30 and the p-type body region 23 is provided, the contact region between the source metal layer 30 and the p-type body region 23 is provided in the width direction of the current channel, and the contact region between the source metal layer 30 and the p-type body region 23 is located at one side or both sides of the clamp gate 26, and fig. 3 illustrates an exemplary structure in which the contact region between the source metal layer 30 and the p-type body region 23 is located at one side of the clamp gate 26. The contact area between the source metal layer 30 and the p-type body region 23 is arranged on one side or both sides of the clamp gate 26 in the width direction of the current channel, so that the chip area of the semiconductor power device can be effectively reduced.
Fig. 4 is a schematic cross-sectional structure of a third embodiment of the semiconductor power device according to the present invention, and fig. 4 is a schematic cross-sectional structure along a width direction of a current channel. As shown in fig. 4, an n-type doped region 40 is disposed in the p-type body region 23, the p-type body region 23 and the n-type doped region 40 form a p-n junction diode structure, and the source metal layer 30 is in direct contact connection with the n-type doped region 40. The structure in which the n-type doped region 40 is located on one side or both sides of the clamp gate 26 in the width direction of the current channel is exemplarily shown in fig. 4 in which the n-type doped region 40 is located on one side of the clamp gate 26. Alternatively, an n-type doped region may be located between the n-type source region and the clamp gate in the length direction of the current channel, and this structure is not specifically shown in the embodiments of the present invention.
According to the semiconductor power device, the clamping grid structure is formed in the p-type body region, the clamping grid is connected with the source voltage outside the source metal layer in an outward mode, charges of the semiconductor power device in the starting process can be coupled, the p-type body region is clamped at zero potential, further charging of a Miller capacitor in the starting process is not affected, the voltage of a Miller platform is reduced, and therefore the grid driving voltage is not required to be additionally increased in the application process.
Although embodiments of the present invention have been disclosed above, it is not limited to the details and embodiments shown and described, it is well suited to various fields of use for which the invention would be readily apparent to those skilled in the art, and accordingly, the invention is not limited to the specific details and illustrations shown and described herein, without departing from the general concepts defined in the claims and their equivalents.
Claims (5)
1. A semiconductor power device, comprising:
An n-type semiconductor layer;
a plurality of p-type pillars within the n-type semiconductor layer;
The p-type body region is positioned in the n-type semiconductor layer and positioned at the top of the p-type column, and an n-type source region is arranged in the p-type body region;
A gate structure recessed in the n-type semiconductor layer for controlling the opening and closing of a current channel, wherein the gate structure comprises a gate dielectric layer and a gate;
the clamping gate is recessed in the p-type body region and is isolated from the p-type body region through a first gate dielectric layer;
And the source metal layer is electrically connected with the n-type source region and the clamping gate, and a p-n junction diode structure is formed between the source metal layer and the p-type body region.
2. The semiconductor power device of claim 1, wherein the source metal layer is in contact with the p-type body region to form a schottky barrier diode structure; or an n-type doped region is arranged in the p-type body region, the p-type body region and the n-type doped region form a p-n junction diode structure, and the source electrode metal layer is electrically connected with the n-type doped region.
3. The semiconductor power device of claim 2, wherein a contact area of the source metal layer and the p-type body region is located between the n-type source region and the clamp gate and the n-type doped region is located between the n-type source region and the clamp gate in a length direction of the current channel.
4. The semiconductor power device of claim 2, wherein a contact region of the source metal layer with the p-type body region is located at one side or both sides of the clamp gate and the n-type doped region is located at one side or both sides of the clamp gate in a width direction of the current channel.
5. The semiconductor power device of claim 1, wherein a bottom of the clamp gate is located within the p-type body region or extends down into the p-type pillar.
Priority Applications (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211652272.0A CN118231465A (en) | 2022-12-21 | 2022-12-21 | Semiconductor power device |
| PCT/CN2023/121631 WO2024131191A1 (en) | 2022-12-21 | 2023-09-26 | Semiconductor power device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202211652272.0A CN118231465A (en) | 2022-12-21 | 2022-12-21 | Semiconductor power device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN118231465A true CN118231465A (en) | 2024-06-21 |
Family
ID=91509955
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202211652272.0A Pending CN118231465A (en) | 2022-12-21 | 2022-12-21 | Semiconductor power device |
Country Status (2)
| Country | Link |
|---|---|
| CN (1) | CN118231465A (en) |
| WO (1) | WO2024131191A1 (en) |
Family Cites Families (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US7750412B2 (en) * | 2008-08-06 | 2010-07-06 | Fairchild Semiconductor Corporation | Rectifier with PN clamp regions under trenches |
| US7989885B2 (en) * | 2009-02-26 | 2011-08-02 | Infineon Technologies Austria Ag | Semiconductor device having means for diverting short circuit current arranged in trench and method for producing same |
| KR101093678B1 (en) * | 2010-01-26 | 2011-12-15 | (주) 트리노테크놀로지 | Power semiconductor device and manufacturing method thereof |
| JP2017055102A (en) * | 2015-09-10 | 2017-03-16 | 株式会社豊田自動織機 | Trench gate semiconductor device and manufacturing method of the same |
| US10714574B2 (en) * | 2018-05-08 | 2020-07-14 | Ipower Semiconductor | Shielded trench devices |
| CN111276540A (en) * | 2020-01-13 | 2020-06-12 | 上海瞻芯电子科技有限公司 | Trench gate power MOSFET and manufacturing method thereof |
| CN113629128B (en) * | 2020-05-06 | 2022-08-19 | 苏州东微半导体股份有限公司 | Semiconductor device with a plurality of transistors |
-
2022
- 2022-12-21 CN CN202211652272.0A patent/CN118231465A/en active Pending
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2023
- 2023-09-26 WO PCT/CN2023/121631 patent/WO2024131191A1/en unknown
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| Publication number | Publication date |
|---|---|
| WO2024131191A1 (en) | 2024-06-27 |
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