CN118226363A - Digital oscilloscope internal calibration source design method based on FPGA - Google Patents
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Abstract
The invention relates to a digital oscilloscope internal calibration source design method based on FPGA, which belongs to the technical field of test and measurement and comprises the following steps: step one, presetting a calibration source device comprising an FPGA, a direct current source module, a sinusoidal calibration source module and a fast edge source module in an oscilloscope, wherein the sinusoidal calibration source module comprises a numerical control attenuator inside and is used for controlling signal gain; initializing a direct current module, a sinusoidal calibration source module and a fast edge source module by using the FPGA, initializing channel control of each module, and outputting a default calibration signal; and thirdly, receiving a control signal sent by an upper computer of the oscilloscope, calculating a corresponding control value according to the control signal, and reconfiguring through the FPGA to enable the direct current source module or the sine calibration source module or the fast edge source module to output the type, the frequency and the gain of the required calibration signal. The output calibration source of the invention has various types and small volume, and is conveniently integrated into the whole oscilloscope as the whole calibration source.
Description
Technical Field
The invention relates to the technical field of test and measurement, in particular to a digital oscilloscope internal calibration source design method based on FPGA.
Background
With the development of modern electronic test measuring instruments, the measuring bandwidth and the measuring precision of the oscilloscopes are gradually improved; the correct and effective startup self-correction aiming at the high-speed oscilloscope is a precondition for ensuring the normal function and performance of the instrument. Although the conventional oscilloscope standard instrument has excellent program control, universality, accuracy and the like, the conventional oscilloscope standard instrument also has the problems of huge volume, single output of a calibration source signal and difficulty in integration into the instrument to realize automatic calibration during startup.
Disclosure of Invention
The invention aims to overcome the defects of the prior art, provides a digital oscilloscope internal calibration source design method based on FPGA, and solves the defects of the existing oscilloscope standard instrument.
The aim of the invention is achieved by the following technical scheme: a digital oscilloscope internal calibration source design method based on FPGA, the design method includes:
Step one, presetting a calibration source device comprising an FPGA, a direct current source module, a sinusoidal calibration source module and a fast edge source module in an oscilloscope, wherein the sinusoidal calibration source module comprises a numerical control attenuator inside and is used for controlling signal gain;
Initializing a direct current module, a sinusoidal calibration source module and a fast edge source module by using the FPGA, initializing channel control of each module, and outputting a default calibration signal;
And thirdly, receiving a control signal sent by an upper computer of the oscilloscope, calculating a corresponding control value according to the control signal, and reconfiguring through the FPGA to enable the direct current source module or the sine calibration source module or the fast edge source module to output the type, the frequency and the gain of the required calibration signal.
The type, frequency and gain of the calibration signal required by the output of the DC source module in the third step comprise:
a1, according to the required direct current bias, Calculating a desired 16-bit resolution DAC value, wherein m and c are different constants,/>, andFor the connected reference voltage,/>Is the output voltage value;
A2, reconfiguring a register of the DAC chip according to the calculated value in the step A1, and controlling to switch corresponding output channels according to the type of the required signal.
The type, frequency and gain of the calibration signal required by the sinusoidal calibration source module output in the step three comprise:
B1, outputting sine calibration signal frequency according to the requirement Design PLL chip output path selection strategy and must meet the requirements/>And/>Wherein/>To output sinusoidal calibration signal frequency,/>To turn on VCO frequency multiplication,/> ，/>The maximum and minimum VCO frequency values of the PLL chip are respectively divider, the output channel frequency division ratio,/>, andRepresenting 4 sets of divide values;
B2, according to the selected output channel Calculating a VCO frequency value required for a PLL chipAnd VCO feedback loop parameters and based on output sinusoidal calibration signal frequency/>And/>And/>The relation of the output paths is selected, and the integer multiple frequency division N value and the fractional multiple frequency division NUM value of the VCO loop are calculated, wherein/>, theIs the phase detector frequency;
And B3, reconfiguring a register of the PLL chip according to the calculated value in the step B2, and controlling the numerical control attenuator to switch a corresponding output channel according to the type of the required signal and the signal gain.
The type, frequency and gain of the calibration signal required by the fast edge source module output in the third step comprise:
c1, controlling a radio frequency switch to switch and input a fast-edge source excitation signal according to a required fast-edge calibration signal;
and C2, controlling to switch corresponding output channels according to the type of the required signal.
Said calibrating signal frequency based on output sinusoidsAnd/>And/>The relation selection output path of (1) includes:
When outputting sinusoidal calibration signal frequency Greater than or equal to/>Then the output signal path selects the frequency multiplication VCO output, and according to/>Selecting a final VCO frequency in a range of values;
When outputting sinusoidal calibration signal frequency Greater than or equal to/>And is less than/>When the output signal path selects the VCO to directly output, and according to/>Selecting a final VCO frequency in a range;
When outputting sinusoidal calibration signal frequency Less than/>And when the VCO channel frequency division is performed, the output signal path is selected and output.
The invention has the following advantages: the design method of the internal calibration source of the digital oscilloscope based on the FPGA is various in output calibration source types, small in size and convenient to integrate into the whole oscilloscope to serve as a whole calibration source.
Drawings
Fig. 1 is a schematic diagram of the design principle of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are only some embodiments of the present application, not all embodiments. The components of the embodiments of the present application generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations. Accordingly, the following detailed description of the embodiments of the application, as presented in conjunction with the accompanying drawings, is not intended to limit the scope of the application as claimed, but is merely representative of selected embodiments of the application. All other embodiments, which can be made by a person skilled in the art without making any inventive effort, are intended to be within the scope of the present application. The application is further described below with reference to the accompanying drawings.
As shown in fig. 1, the invention specifically relates to a digital oscilloscope internal calibration source design method based on an FPGA, which controls a direct current source module, a sinusoidal calibration source module and a fast edge source module to output different calibration signals through the FPGA, and comprises the following contents:
Step 1, presetting a calibration source device in an oscilloscope, wherein the device comprises an FPGA, a direct current source module, a sinusoidal calibration source module and a fast edge source module; the sine calibration source module comprises a numerical control attenuator which is used for controlling signal gain;
step 2, the FPGA controls the internal direct current source module, the sinusoidal calibration source module and the fast edge source module to perform initialization operation, namely initializing and configuring a register of a DAC in the direct current source module and a register of a PLL chip in the sinusoidal calibration source module, initializing channel control of each module and outputting a default calibration signal;
And 3, in the continuous operation process of the calibration source device, a control signal sent by an upper computer of the oscilloscope can be received, a corresponding control value is calculated according to the required control signal, and reconfiguration is performed through the FPGA, so that the calibration source outputs the required calibration signal type, frequency and gain.
The DC source module adopts a circuit scheme of DAC (digital-to-analog converter) plus an operational amplifier, and the multi-bit DAC can ensure the output precision and can flexibly adjust the output range through the operational amplifier.
The sinusoidal calibration source module uses a PLL chip to generate a calibration source signal of 10MHz-18GHz, and in order to ensure the requirement of the whole machine on spurious indexes of special frequency band signals (200 MHz-300 MHz,4.5 GHz-6.5 GHz,10 GHz-12 GHz and 15 GHz-18 GHz), the output signals are subjected to sectional filtering, and after the sectional filtering, the amplitude of the output sinusoidal signals is greatly dynamically regulated through cascade connection of multistage amplifiers, namely numerical control attenuators.
The fast-edge source module generates a dressing wave signal through the dressing wave generator, and outputs the fast-edge signal after the signals are combined through the amplifying switch.
Further, step 3 includes the following:
1. for a sinusoidal calibration source module:
(1) Calibrating signal frequency according to desired output sine Designing a PLL chip output path selection strategy requires that the following formulas be satisfied:
（1）
（2）
Wherein the method comprises the steps of To output sinusoidal calibration signal frequency,/>To turn on the VCO (voltage controlled oscillator) frequency multiplication, the value is 1 or 2,/>And/>The maximum and minimum VCO frequency values of the PLL chip are respectively divider the output channel frequency division ratio, in equation (2)/>For 4 sets of division values, the selection is made according to the output frequency.
(2) Calculating the required PLL chip according to the selected output pathVCO feedback loop parameters (including/>、/>、And/>) The following formula needs to be satisfied:
（3）
Wherein the method comprises the steps of The phase discrimination frequency is set to 200MHz according to the device manual selection, and the internal calibration source steps by 10MHz,/>The fractional frequency division part of the VCO feedback loop is shown, and the signal frequency is designed to be smaller than 10MHz,200 (MHz) ×1/20) =10 (MHz), so that the step smaller than 10MHz can be ensured only by the denominator larger than 20, and therefore, DEN only needs to be larger than or equal to 20, and DEN is set to 400.
According to formula (1),Greater than or equal to/>The output signal path selects the frequency multiplication VCO output according toSelecting a final VCO frequency in a range of values; /(I)Greater than or equal to/>And is less than/>When the output signal path selects the VCO to directly output, and according to/>Selecting a final VCO frequency in the VCO range; /(I)Less than/>And when the VCO channel frequency division is performed, the output signal path is selected and output.
Further, taking a PLL chip with model LMX2595 as an example, the VCO minimum frequency value of the source module is sine-calibratedCan be configured to 7.5GHz according to the formula (1)/>Thus selecting a channel divide output, referring to the PLL data manual, selecting a divide ratio of 2, i.e./>, in equation (2)Is 1,/>Is 2,/>Is 1,/>Is 1,/>1, The VCO frequency value is calculated to be 12GHz according to the formula (1), and a 6G sine wave signal is output after frequency division by 2, so that/>, in the formula (3)Is 60,/>Is 0,/>400,/>200MHz.
Taking a PLL chip with model LMX2595 as an example, when outputting a 6GHz sinusoidal signal, modifying register data of the PLL chip includes:
1. The reselection signal path is the channel frequency division output, and the value of the configuration register 0x2D [12:11] is 0x0;
2. the channel divide chdiv, divide by 2 need to be reconfigured and the register 0x4b [10:6] value set to 0x0;
3. configuring a hash_order of the PLL with a register 0x2C2:0 value of 0x3;
4. According to the calculated value, NUM value is configured, and the value of the register 0x2B [15:0] is 0x0000;
5. Configuring NUM value, register 0x2A [31:16] value is 0x0000;
6. According to the frequency division value and the VCO frequency in the configuration table, configuring the value of the register 0x25[13:8] to be 0x4;
7. Configuring the value of the integral multiple frequency division N [15:0] of the VCO loop, wherein the value of the register 0x24[15:0] is 0x003C;
8. Configuring the value of the integral multiple frequency division N [18:16] of the VCO loop, and the value of the register 0x22[2:0] is 0x0;
9. Setting the closed seg1_en according to the channel output frequency division value of 2, and setting the register 0x1F < 14 > value of 0x0;
10. setting the value of 0x1B < 0 > to 0x0 by setting the closing vco2x_en according to the output frequency smaller than 7.5G;
11. According to the configuration table and the VCO frequency of 12GHz, the value of VCO_sel,0x14[13:11] is configured to be 0x5;
The specific register values in the above example are: register 0x4B value is set to 0x0800; the 0x2D value is 0xC0DF; a value of 0x2C is 0x1FA3; a value of 0x2B is 0x0000; a value of 0x2A is 0x0000; a value of 0x25 is 0x0404; a value of 0x24 is 0x003C; a value of 0x22 is 0x0000; a 0x1F value of 0x03EC; a value of 0x1B of 0x0002; a 0x14 value of 0xE848; the 0x00 value is 0x251C.
(3) The register in the PLL chip is reconfigured according to the calculated value; wherein the frequency of the sinusoidal calibration signal is greater than or equal to the minimum frequency of the PLLWhen the frequency multiplication or direct output is adopted, different VCO frequencies are selected according to different output signal frequencies; the required signal frequency is less than/>When the VCO divide output is used, different VCO frequencies and channel divide ratios divider are selected according to the different signal frequencies.
(4) And controlling the numerical control attenuator according to the type of the required signal and the signal gain, switching the output channel into a sinusoidal calibration source module, and outputting a calibration source to the whole oscilloscope for self calibration.
2. For a dc source module:
(1) According to the required DC bias, calculating the required 16-bit resolution DAC value, wherein the calculation formula is as follows:
（4）
wherein, for the DAC of the ad5761 model, In the voltage range, m is 4, c is 2,/>In order to obtain the connected reference voltage,Is the output voltage value;
(2) And (3) reconfiguring a register of the DAC chip according to the calculated value in the step (1), switching an output channel to be a direct current source module according to the type of the required signal, and outputting a direct current source signal to the whole oscilloscope for self calibration.
3. For a fast edge source module:
(1) Controlling the radio frequency switch to switch and input a fast edge source excitation signal (300 MHz, 100MHz or 10 HMz) according to the required fast edge calibration signal;
(2) And switching the output channel into a fast-edge source module according to the type of the required signal, and outputting a fast-edge source signal to the whole oscilloscope for self-calibration.
The foregoing is merely a preferred embodiment of the invention, and it is to be understood that the invention is not limited to the form disclosed herein but is not to be construed as excluding other embodiments, but is capable of numerous other combinations, modifications and adaptations, and of being modified within the scope of the inventive concept described herein, by the foregoing teachings or by the skilled person or knowledge of the relevant art. And that modifications and variations which do not depart from the spirit and scope of the invention are intended to be within the scope of the appended claims.
Claims (5)
1. A digital oscilloscope internal calibration source design method based on FPGA is characterized in that: the design method comprises the following steps:
Step one, presetting a calibration source device comprising an FPGA, a direct current source module, a sinusoidal calibration source module and a fast edge source module in an oscilloscope, wherein the sinusoidal calibration source module comprises a numerical control attenuator inside and is used for controlling signal gain;
Initializing a direct current module, a sinusoidal calibration source module and a fast edge source module by using the FPGA, initializing channel control of each module, and outputting a default calibration signal;
And thirdly, receiving a control signal sent by an upper computer of the oscilloscope, calculating a corresponding control value according to the control signal, and reconfiguring through the FPGA to enable the direct current source module or the sine calibration source module or the fast edge source module to output the type, the frequency and the gain of the required calibration signal.
2. The digital oscilloscope internal calibration source design method based on FPGA according to claim 1, wherein the method is characterized in that: the type, frequency and gain of the calibration signal required by the output of the DC source module in the third step comprise:
A1, according to the required DC bias, through Calculating a desired 16-bit resolution DAC value, wherein m and c are different constants,/>, andFor the connected reference voltage,/>Is the output voltage value;
A2, reconfiguring a register of the DAC chip according to the calculated value in the step A1, and controlling to switch corresponding output channels according to the type of the required signal.
3. The digital oscilloscope internal calibration source design method based on FPGA according to claim 1, wherein the method is characterized in that: the type, frequency and gain of the calibration signal required by the sinusoidal calibration source module output in the step three comprise:
B1, outputting sine calibration signal frequency according to the requirement Design PLL chip output path selection strategy and must meet the requirements/>And/>Wherein, the method comprises the steps of, wherein,To output sinusoidal calibration signal frequency,/>To turn on VCO frequency multiplication,/>， />The maximum and minimum VCO frequency values of the PLL chip are respectively divider, the output channel frequency division ratio,/>, andRepresenting 4 sets of divide values;
B2, according to the selected output channel Calculate VCO frequency value required by PLL chip/>And VCO feedback loop parameters and based on output sinusoidal calibration signal frequency/>And/>And/>The relation of the output paths is selected, and the integer multiple frequency division N value and the fractional multiple frequency division NUM value of the VCO loop are calculated, wherein/>, theIs the phase detector frequency;
And B3, reconfiguring a register of the PLL chip according to the calculated value in the step B2, and controlling the numerical control attenuator to switch a corresponding output channel according to the type of the required signal and the signal gain.
4. The digital oscilloscope internal calibration source design method based on FPGA according to claim 1, wherein the method is characterized in that: the type, frequency and gain of the calibration signal required by the fast edge source module output in the third step comprise:
c1, controlling a radio frequency switch to switch and input a fast-edge source excitation signal according to a required fast-edge calibration signal;
and C2, controlling to switch corresponding output channels according to the type of the required signal.
5. The digital oscilloscope internal calibration source design method based on FPGA according to claim 3, wherein the method is characterized in that: said calibrating signal frequency based on output sinusoidsAnd/>And/>The relation selection output path of (1) includes:
When outputting sinusoidal calibration signal frequency Greater than or equal to/>Then the output signal path selects the frequency multiplication VCO output, and according to/>Selecting a final VCO frequency in a range of values;
When outputting sinusoidal calibration signal frequency Greater than or equal to/>And is less than/>When the output signal path selects the VCO to directly output, and according to/>Selecting a final VCO frequency in a range;
When outputting sinusoidal calibration signal frequency Less than/>And when the VCO channel frequency division is performed, the output signal path is selected and output.
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