CN118214634A

CN118214634A - FSK decoder, FSK unpacking method and wireless charging receiving device

Info

Publication number: CN118214634A
Application number: CN202410334551.5A
Authority: CN
Inventors: 张其文; 丁杨
Original assignee: Zhuhai Nanxin Semiconductor Technology Co ltd
Current assignee: Zhuhai Nanxin Semiconductor Technology Co ltd
Priority date: 2024-03-22
Filing date: 2024-03-22
Publication date: 2024-06-18

Abstract

The application provides an FSK decoder, an FSK unpacking method, a wireless charging receiving device, a chip and electronic equipment. The FSK decoder receives a bit stream signal in the current communication process, wherein the bit stream signal is obtained by demodulating the FSK signal sent by the wireless charging sending device, the bit stream signal comprises N pulses, N bits correspond to the N bits, and N is a positive integer. When the width of the pulse in the bit stream signal accords with the preset width, sequentially decoding the pulse of the bit stream signal, counting the bit obtained by decoding, and storing the bit obtained by decoding into a data register. And determining the data type corresponding to the bit stream signal according to the real-time count value of the bit obtained by decoding, and storing the data in the data register into a memory corresponding to the data type. Accordingly, the FSK decoder can adaptively recognize the type of the bit stream signal, thereby improving the stability of the wireless charging system.

Description

FSK decoder, FSK unpacking method and wireless charging receiving device

Technical Field

The present application relates to the field of wireless charging technologies, and in particular, to a Frequency Shift Keying (FSK) decoder, an FSK unpacking method, and a wireless charging receiving device.

Background

With the development of wireless charging technology, more and more electronic devices support wireless charging. Among the mainstream wireless charging standards, the Qi standard occupies most of the market due to its convenience and versatility. Qi is a wireless charging technology, and is also a wireless charging standard established by the wireless charging consortium (wireless power consortium, WPC). Based on the electromagnetic induction principle, the Qi technology can realize wireless transmission of electric energy. The Qi technology provides a charging function for the electronic device without the need for plugging in a cable. In Qi wireless charging systems, one device acts as a transmitter and the other device acts as a receiver. The transmitter converts the baseband signal to an FSK signal using FSK modulation techniques, and the transmitter transmits the FSK signal to the receiver. The receiver receives the FSK signal from the transmitter, decodes the FSK signal into a bit stream signal, and unpacks the bit stream signal to obtain a data packet. Through such a process, a wireless charging function is realized. The data packet obtained by unpacking can be divided into a response packet and a data packet. The reply packet can inform the receiver that the last communication has been successfully received, and the data packet is a data packet containing wireless charging information and sent to the receiver by the transmitter, for example, the data packet can include a control instruction, configuration information and a charging state query sent by the transmitter.

In the related art, before the bitstream signal is unpacked into the data packet, the receiver needs to preset the type of the data packet, and the receiver unpacks the received bitstream signal according to the preset type.

However, when the preset packet type does not match the actually received packet type, a solution Bao Chucuo may be caused. When the Bao Chucuo is resolved, the receiver cannot respond to the actually received data packet, thereby affecting the communication between the transmitter and the receiver. This may lead to an interruption or abnormality of the wireless charging, and the stability of the wireless charging system is affected.

Disclosure of Invention

The application provides an FSK decoder, an FSK unpacking method, a wireless charging receiving device, a chip and electronic equipment, which are used for solving the problem of possible interruption or abnormality in the wireless charging process.

In a first aspect, the present application provides an FSK decoder for use in a wireless charging receiver.

The FSK decoder is for: and receiving a bit stream signal in the current communication process, wherein the bit stream signal is obtained by demodulating an FSK signal transmitted by the wireless charging transmitting device, the bit stream signal comprises N pulses corresponding to N bits, and N is a positive integer.

When the width of the pulse in the bit stream signal accords with the preset width, sequentially decoding the pulse of the bit stream signal, counting the bit obtained by decoding, and storing the bit obtained by decoding into a data register.

And determining the data type corresponding to the bit stream signal according to the real-time count value of the bit obtained by decoding, and storing the data in the data register into a memory corresponding to the data type.

The FSK decoder provided by the application counts the number of bits in the bit stream signal by receiving the bit stream signal in the current communication process. The data of the bit obtained by decoding the bit stream signal may be an acknowledgement packet or a data packet, and the number of bits of the acknowledgement packet and the data packet is different. Typically, the response packet is 8 bits of data, and the data packet is 15 bits of data or greater than 15 bits of data. Thus, the FSK decoder can determine whether the bit stream signal is an acknowledgement packet or a data packet according to the bit number of the received bit stream signal. The FSK decoder does not have to assume in advance whether the received bitstream signal represents an acknowledgement packet or a data packet, and the FSK decoder can decode the bitstream signal into an acknowledgement packet or a data packet of a corresponding type according to the number of bits of the bitstream signal and respond to the acknowledgement packet or the data packet by the processor. Therefore, the FSK decoder can improve the detection accuracy of the detection response packet and the data packet, so that the stability of the wireless charging system is improved, and the wireless charging efficiency is improved.

In one possible design, determining a data type corresponding to the bit stream signal according to the real-time count value of the bit obtained by decoding, and storing the data in the data register into a memory corresponding to the data type, including:

And under the condition that the real-time count value is equal to a first value and new bits are not obtained through further decoding, determining the received bit stream signal as a response packet, and storing the bits obtained through decoding stored in the data register into a memory corresponding to the response packet, wherein the first value is equal to the bit number of the response packet.

Or under the condition that the real-time count value is equal to the second value and the new bit is not obtained by further decoding, determining the received bit stream signal as a data packet, and storing the bit obtained by decoding stored in the data register into a memory corresponding to the data packet. Wherein the second value is equal to the number of bits of the data packet.

Or when the real-time count value is equal to a third value, determining the received bit stream signal as a data packet, and storing the first data of all bits from the start bit in the data register, wherein the third value is larger than the bit number of the data packet.

In one possible design, after determining the data type corresponding to the bit stream signal according to the real-time count value of the bit obtained by decoding and storing the data in the data register into the memory corresponding to the data type, the method further includes:

And under the condition that the real-time count value is equal to the first value and new bits are not obtained through further decoding, sending a first interrupt signal to the processor, wherein the first interrupt signal is used for the processor to execute the operation of corresponding instructions according to the data of all bits and receive the bit stream signal in the next communication process.

And under the condition that the real-time count value is equal to the second value and new bits are not obtained through further decoding, when the check bit and/or the stop bit in the data of all bits are checked successfully, a second interrupt signal is sent to the processor, and the second interrupt signal is used for executing the operation of corresponding instructions according to the data of all bits by the processor and receiving the bit stream signal in the next communication process.

And when the real-time count value is equal to the third value, a third interrupt signal is sent to the processor when the check bit and/or the stop bit in the first data are checked successfully, and the third interrupt signal is used for the processor to execute the operation of the corresponding instruction according to the first data and receive the bit stream signal in the next communication process.

Based on this, when the real-time count value is equal to the first value, the FSK decoder transmits the data of the first value bit to the response packet detector, which can detect whether the data of the first value bit is a response packet. When the count number is equal to the second value or the third value, the FSK decoder sends the data of the second value or the third value to the data packet detector, and the data packet detector can detect whether the data of the second value or the third value is a data packet or not.

In one possible design, the FSK decoder includes: edge detector, data decoder, and store and counter.

The input end of the edge detector is used for inputting a bit stream signal, the output end of the edge detector is connected with the input end of the data decoder, and the output end of the data decoder is connected with the input end of the storage and counter.

And the edge detector is used for determining whether the width of the pulse in the bit stream signal accords with the preset width or not and sending the bit stream signal which accords with the preset width to the data decoder.

And the data decoder is used for decoding the bit stream signal conforming to the preset width and transmitting the bit obtained by decoding to the storage and counter.

And the storage and counter is used for counting the bits obtained by decoding to obtain a real-time count value and storing the bits obtained by decoding and the real-time count value.

And the storage and counter is also used for determining the data type corresponding to the bit stream signal according to the real-time count value of the bit obtained by decoding and sending the bit obtained by decoding to a memory corresponding to the data type.

The first output of the store and counter is connected to the input of the acknowledgement packet detector, the second output of the store and counter is connected to the input of the data packet detector, the output of the acknowledgement packet detector is used for outputting acknowledgement packets and first interrupt signals, the output of the data packet detector is used for outputting data packets, and the second interrupt signal or the third interrupt signal, in one possible design, the FSK decoder further comprises: a response packet detector and a data packet detector.

And the response packet detector is used for receiving the bit obtained by decoding, storing data of all bits in a memory corresponding to the response packet when the real-time count value is equal to the first value and the new bit is not obtained by further decoding, and sending a first interrupt signal to the processor.

And the data packet detector is used for receiving the bit obtained by decoding.

And the data packet detector is also used for storing data of all bits in a memory corresponding to the data packet when the real-time count value is equal to the second value and the new bits are not further decoded, and sending a second interrupt signal to the processor when check bits and/or stop bits in the data of all bits are checked successfully. Or when the real-time count value is equal to the third value, storing the first data in a memory corresponding to the data packet, and sending a third interrupt signal to the processor when the check bit and/or the stop bit in the first data are checked successfully.

In one possible design, the edge detector includes: a first pulse number detector and a second pulse number detector. Wherein the number of pulses detected by the first pulse number detector is different from the number of pulses detected by the second pulse number detector.

Based on this, the first pulse number detector and the second pulse number detector can detect two kinds of bit stream signals with pulse widths, and the unpacking efficiency of the FSK decoder is improved.

In one possible design, a data decoder includes: a data identification judgment device and a pulse number counter.

In one possible design, the store and counter includes: a data shifter and a data bit number counter.

And the data shifter is used for storing the decoded bit.

And the data bit number counter is used for counting the decoded bits to obtain a real-time count value, transmitting the decoded bits to the response packet detector when the real-time count value is equal to the first value, and transmitting the decoded bits to the data packet detector when the real-time count value is equal to the second value or the third value.

Based on this, the store and counter is able to provide the data of the number of bits required by the response packet detector and the data packet detector by means of the data shifter and the data bit number counter.

In one possible design, the reply packet detector includes: the reply detection comparator and the reply timeout timer.

And the response detection comparator is used for receiving the decoded bit, detecting whether the decoded bit is further decoded to obtain a new bit when the real-time count value is equal to the first value, and sending a first stop signal to the response timeout timer when the decoded bit is received.

The response timeout timer is used for setting response timeout time and timing, and stopping timing when the first stop signal is received in the response timeout time; and when the first stop signal is not received within the response timeout time, storing data of all bits in a memory corresponding to the response packet, and sending a first interrupt signal to the processor.

In one possible design, the packet detector includes: packet detection comparators and sync bit detection and counters.

And the information packet detection comparator is used for receiving the bit obtained by decoding, detecting whether the new bit is obtained by further decoding when the real-time count value is equal to the second value, checking check bits and/or stop bits in the bit data obtained by decoding when the new bit is not obtained by further decoding, and sending a second stop signal to the synchronous bit detection and counter when the check is successful.

The packet detection comparator is further configured to receive the decoded bit data, detect whether to further decode to obtain a new bit when the real-time count value is equal to the third value, and check a check bit and/or a stop bit in the decoded bit when the new bit is not further decoded, and send a third stop signal to the synchronous bit detection and counter when the check is successful.

The synchronous bit detection and counter is used for setting a first data timeout time and timing, and stopping timing when a second stop signal is received in the first data timeout time; and when the second stop signal is not received within the first data timeout time, storing the data of all bits in a memory corresponding to the data packet, and sending a second interrupt signal to the processor.

The synchronous bit detection and counter is also used for setting second data timeout time and timing, and stopping timing when a third stop signal is received within the second data timeout time; and when the third stop signal is not received within the data receiving timeout time, storing the first data of all bits of data from the start bit in a memory corresponding to the data packet, and sending a third interrupt signal to the processor.

In one possible design, the synchronization bit detection and counter is further configured to store the second data of all bits before the start bit in the synchronization bit number register when the real-time count value is equal to the third value.

In a second aspect, the present application proposes an FSK unpacking method, including:

Receiving a bit stream signal in the current communication process, wherein the bit stream signal is obtained by demodulating an FSK signal sent by a wireless charging and sending device, the bit stream signal comprises N pulses corresponding to N bits, and N is a positive integer;

When the width of the pulse in the bit stream signal accords with the preset width, sequentially decoding the pulse of the bit stream signal, counting the bit obtained by decoding, and storing the bit obtained by decoding into a data register;

The FSK unpacking method further comprises the following steps:

When the width of the bit stream signal of the bit obtained by decoding does not accord with the preset width, discarding the bit stream signal and sending prompt information to the processor, wherein the prompt information is used for prompting the bit stream signal receiving error and receiving the bit stream signal in the next communication process.

The FSK unpacking method further comprises the following steps: and when the real-time count value is equal to the third value, storing second data of all bits of data before the start bit in the synchronous bit number register.

In a third aspect, the present application provides a wireless charging reception apparatus, including: processor, FSK demodulator, data register and FSK decoder.

In a fourth aspect, the present application provides a chip, comprising: an FSK decoder, or a wireless charging receiving device.

In a fifth aspect, the present application proposes an electronic device comprising: wireless charging receiving device.

The advantages provided in the second to fifth aspects and the possible designs of the second to fifth aspects may be referred to the advantages brought by the possible embodiments of the first aspect and the first aspect, and are not described herein.

Drawings

Fig. 1 is a schematic structural diagram of a wireless charging system according to an embodiment of the present application;

fig. 2 is a schematic structural diagram of a wireless charging receiving device according to an embodiment of the present application;

FIG. 3 is a schematic diagram of an FSK decoder according to an embodiment of the present application;

fig. 4 is a schematic diagram of a bit stream signal of a reply packet according to an embodiment of the present application;

fig. 5 is a schematic diagram of a bit stream signal of a data packet according to an embodiment of the present application;

FIG. 6 is a schematic diagram of another bitstream signal of a data packet according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of an FSK decoder according to an embodiment of the present application;

FIG. 8 is a schematic diagram of another FSK decoder according to an embodiment of the present application;

fig. 9 is a flowchart of an FSK unpacking method according to an embodiment of the present application.

Detailed Description

In the present application, "at least one" means one or more, and "a plurality" means two or more. "and/or", describes an association relationship of an association object, and indicates that there may be three relationships, for example, a and/or B, and may indicate: a alone, a and B together, and B alone, wherein a, B may be singular or plural. The character "/" generally indicates that the context-dependent object is an "or" relationship. "at least one of" or the like means any combination of these items, including any combination of single item(s) or plural items(s). For example, at least one (one) of a, b, or c alone may represent: a alone, b alone, c alone, a combination of a and b, a combination of a and c, b and c, or a combination of a, b and c, wherein a, b, c may be single or plural. Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance.

The terms "center," "longitudinal," "transverse," "upper," "lower," "left," "right," "front," "rear," and the like refer to an orientation or positional relationship based on that shown in the drawings, merely for convenience of description and to simplify the description, and do not indicate or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and therefore should not be construed as limiting the application.

The terms "connected," "connected," and "connected" are to be construed broadly, and may refer to, for example, electrical or signal connections in addition to physical connections, e.g., direct connections, i.e., physical connections, or indirect connections via at least one element therebetween, such as long as electrical circuit communication is achieved, and communications within two elements; signal connection may refer to signal connection through a medium such as radio waves, in addition to signal connection through a circuit. The specific meaning of the above terms in the present application will be understood in specific cases by those of ordinary skill in the art.

Illustratively, the present application provides a wireless charging system. Referring to fig. 1, fig. 1 is a schematic structural diagram of a wireless charging system according to an embodiment of the application.

As shown in fig. 1, the wireless charging system of the present application may include: wireless charging transmitting device and wireless charging receiving device.

The wireless charging system can realize the function of wireless charging through a plurality of wireless charging standards, and the wireless charging standards at least comprise the Qi standard and the A4WP (alliance for wireless power) standard. The A4WP standard realizes a wireless charging function with a long distance through an electromagnetic resonance principle. The Qi standard is used for wireless charging through the electromagnetic induction principle, and the charging efficiency of wireless charging by adopting the Qi standard is high. Therefore, the Qi standard is widely used in wireless charging of electronic devices.

The electronic device may be a mobile phone (such as a folding screen mobile phone, a large screen mobile phone, etc.), a tablet computer, a notebook computer, a wearable device, a vehicle-mounted device, an augmented reality (augmented reality, AR)/Virtual Reality (VR) device, an ultra-mobile personal computer (UMPC), a netbook, a Personal Digital Assistant (PDA), an intelligent television, a smart screen, a high definition television, a 4K television, an intelligent sound box, an intelligent projector, etc., which does not limit the specific type of the electronic device according to the present application.

The wireless charging transmitting device can transmit electric energy to the wireless charging receiving device in an electromagnetic wave mode, so that the wireless charging receiving device can conduct wireless charging. The wireless charging transmitting apparatus may be provided in a charging device that supplies power to the electronic device. The wireless charging transmitting device is also communicated with the wireless charging receiving device when transmitting electric energy. The wireless charging transmitting device can modulate the baseband signal into an FSK signal, and the wireless charging transmitting device sends the FSK signal to the wireless charging receiving device. The baseband signal can carry wireless charging information sent by the wireless charging transmitting device. The wireless charging transmitting device communicates with the wireless charging receiving device by transmitting an FSK signal to the wireless charging receiving device, wherein the FSK signal can carry wireless charging information. For example, the wireless charging information may include response information, a charging power adjustment command, a charge state command, and a charge time control command.

The wireless charging receiving device may also be referred to as a power receiver or a charging container, and may be provided in an electronic device that receives electric energy, the wireless charging receiving device being capable of receiving electric energy transmitted in the form of electromagnetic waves. The wireless charging receiving device also communicates with the wireless charging transmitting device when receiving the electric energy. The wireless charging reception device communicates with the wireless charging transmission device by transmitting a request signal to the wireless charging transmission device, for example, the request signal may carry a signal requesting adjustment of power, a signal requesting initialization, and the like.

After the wireless charging receiving device receives the FSK signal sent by the wireless charging transmitting device, the wireless charging receiving device demodulates the FSK signal into a bit stream signal, and the wireless charging receiving device also judges the data type of the bit stream signal, so that bit stream signals of different types are identified to obtain wireless charging information.

The wireless charging receiving device provided by the application is described in detail below with reference to fig. 2. Referring to fig. 2, fig. 2 is a schematic structural diagram of a wireless charging receiving device according to an embodiment of the application.

As shown in fig. 2, the wireless charging reception apparatus of the present application may include: processor, FSK decoder, data register and FSK demodulator.

The FSK demodulator is capable of receiving the FSK signal transmitted by the wireless charging transmitter, demodulating the FSK signal into a bit stream signal, and transmitting the bit stream signal to the FSK decoder. The FSK demodulator is capable of transmitting status information to the processor and receiving configuration information transmitted by the processor.

The FSK decoder receives the bit stream signal sent by the FSK demodulator, and the FSK decoder judges the data type of the bit stream signal. The FSK decoder stores bit stream signals of different types into the data register, and the processor identifies the data of different types in the data register to obtain wireless charging information.

The processor is capable of communicating with the FSK demodulator to obtain status information of the FSK demodulator. The processor sends configuration information to the FSK demodulator, e.g., the processor sends configuration information to the FSK demodulator to configure parameters of the FSK demodulator. The processor receives the different types of data sent by the data register, so that the data are analyzed into corresponding wireless charging information.

The data register can store different types of data sent by the FSK decoder for the processor to parse the different types of data into corresponding wireless charging information.

Therefore, the wireless charging receiving device can analyze the FSK signal sent by the wireless charging transmitting device into wireless charging information through the processor, the FSK decoder, the data register and the FSK demodulator. Therefore, wireless charging information is transmitted, and the wireless charging system is ensured to work.

Based on the above description of the wireless charging receiving device, the FSK decoder according to the present application will be described in detail with reference to fig. 3. Fig. 3 is a schematic diagram of an FSK decoder according to an embodiment of the present application. The FSK decoder can implement the steps of:

(1) Receiving a bit stream signal in the current communication process, wherein the bit stream signal is obtained by demodulating an FSK signal sent by a wireless charging and sending device, the bit stream signal comprises N pulses corresponding to N bits, and N is a positive integer;

(2) When the width of the pulse in the bit stream signal accords with the preset width, sequentially decoding the pulse of the bit stream signal, counting the bit obtained by decoding, and storing the bit obtained by decoding into a data register;

(3) And determining the data type corresponding to the bit stream signal according to the real-time count value of the bit obtained by decoding, and storing the data in the data register into a memory corresponding to the data type.

In the application, the data register is named differently in the response packet detector and the data packet detector. The data register may be referred to as a memory corresponding to the response packet in the response packet detector, and the data register may be referred to as a memory corresponding to the data packet in the data packet detector.

In addition, the bit obtained by decoding may be expressed as data of the ith bit, and the real-time count value may be expressed as j.

The FSK decoder may be applied to a wireless charging reception apparatus, and in particular, the FSK decoder is capable of implementing the steps of:

Step 1) the FSK decoder can receive a bit stream signal in the current communication process, wherein the bit stream signal is obtained by demodulating the FSK signal sent by the wireless charging sending device, and the bit number of the bit stream signal is N, and N is a positive integer.

The FSK decoder may receive the bit stream signal transmitted by the FSK demodulator during one communication of the wireless charging transmitting device and the wireless charging receiving device. The bit stream signal may be data representing an acknowledgement packet or a data packet transmitted from the wireless charging transmitting apparatus to the wireless charging receiving apparatus, thereby performing the current communication. After the previous communication is completed, the FSK decoder may receive the bit stream signal in the next communication. Wherein the FSK decoder may repeat the same process as the decoding of the current communication for the bitstream signal of the next communication.

The bit stream signal in each communication may comprise N bits, the bit stream data for each bit representing a baseband signal with or without a change in one or more parameters of frequency, amplitude or phase.

Step 2) when the width of the bit stream signal of the ith bit accords with the preset width, decoding the bit stream signal of the ith bit by the FSK decoder to obtain data of the ith bit, storing the data of the ith bit by the FSK decoder, updating j=j+1, updating i=i+1, taking positive integers which are larger than or equal to 1 and smaller than or equal to N, and taking integers which are larger than or equal to 0 and smaller than or equal to i.

The bit stream signal of each bit may be represented by binary data "0" or "1". The width of each bit represents the pulse duration of binary data "0" or binary data "1".

The preset width is a pulse duration of the bit stream signal of 1 bit that the FSK decoder expects to receive. For example, the preset width may be 128 microseconds (μs) or 512 microseconds (μs).

The width of the bit stream signal of different bits can represent different communication states. The communication state is a different state when the wireless charging transmitting device and the wireless charging receiving device communicate. The communication state may include power control, data transmission, security authentication, and device identification.

When the preset width is set to 512, the FSK decoder wants to receive a communication signal of a maximum power point (maximum power point, MPP) handshake. The MPP handshake can ensure maximum power transfer between the wireless charging transmitter and the wireless charging receiver. When the FSK decoder detects a bit stream signal with the width of 512 bits, the FSK decoder can confirm that the wireless charging transmitter and the wireless charging receiver are in MPP handshake, so that the energy transmission efficiency in the wireless charging process can be improved.

When the preset width is set to 128, the FSK decoder wants to transmit wireless charging data. When the wireless charging transmitter and the wireless charging receiver want to perform data transmission, the start or end of data transmission is indicated by a bit stream signal of bits having a transmission width of 128.

J represents the number of bits of data stored in the FSK decoder.

The FSK decoder stores 1-bit data and updates j=j+1 once every 1-bit stream signal is decoded by the FSK decoder.

Starting from the bit stream signal of bit 1, the FSK decoder is able to detect whether the width of the bit stream signal of each bit corresponds to a preset width. The FSK decoder decodes the bit stream signal of the bit having the width of the preset width, and the FSK decoder increments the number of bit stream signals of the bit by 1 at a time, that is, performs an operation of i=i+1 once.

When the width of the bit stream signal of a certain bit does not accord with the preset width, the FSK decoder discards the bit stream signal of the certain bit and does not increment i by 1. Thus, the decoding accuracy of the FSK decoder can be improved and the waste of resources of the FSK decoder can be reduced.

When the width of the bit stream signal of a certain bit accords with the preset width, the FSK decoder decodes the bit stream signal of the bit and increments i by 1. Then, the FSK decoder detects whether the width of the bit stream signal of the next bit accords with the preset width, and so on until the bit stream signal of the Nth bit is decoded or discarded, so that the FSK decoder decodes the data of the current communication.

The data of the bit obtained by decoding the bit stream signal may be an acknowledgement packet or a data packet, and the number of bits of the acknowledgement packet and the data packet is different. And each time the bit stream signal in the current communication process is received, the process of the step 2) is circularly executed until the condition of one step of the steps 3), 4) and 5) is met, and the FSK decoder continues to receive the bit stream signal in the next communication process. Typically, the response packet is 8 bits of data, and the data packet is 15 bits of data or greater than 15 bits of data. Thus, when j is equal to the first value, the FSK decoder may implement step 3 as follows). Wherein the first value is the number of bits of the response packet. When j is equal to the second value, the FSK decoder may implement step 4) as follows. When j is equal to the third value, the FSK decoder may implement step 5 as follows). Wherein the second value or the third value is the number of bits of the data packet.

Step 3) when j is equal to the first value and the FSK decoder does not store the data of the ith bit, the FSK decoder stores the data of all bits in the data register, and the FSK decoder sends a first interrupt signal to the processor, wherein the first interrupt signal is used for the processor to execute the operation of a corresponding instruction according to the data of all bits and receive the bit stream signal in the next communication process. Wherein the first value is equal to the number of bits of the reply packet.

The first value may be the number of bits of the acknowledgement packet. For example, when the response packet is 8 bits, the first value is set to 8.

The data of all bits may represent a reply or acknowledgement signal of the wireless charging transmitter to the request information of the wireless charging receiver. When the first value is set to 8, the data of all stored bits is 8 bits.

The first interrupt signal indicates that the communication is completed, and the next communication can be performed. The first interrupt signal may instruct the processor to issue an instruction to start the next communication. The first interrupt signal may further instruct the processor to perform an operation of acknowledging the acknowledgement according to the data of all bits, thereby informing the wireless charging transmitting device of the information that the wireless charging receiving device has received the acknowledgement information. In this way, the wireless charging transmitting device can perform the next communication.

The bit stream signal may represent different binary data "0" and "1" by the number of changes of the high level and the low level.

The bit stream signal of the acknowledgement packet is the first numerical bit before the data decoded into bits. Next, taking the first value as 8 as an example, an implementation manner of the response packet will be described in detail.

Fig. 4 is a bit schematic diagram of a response packet according to an embodiment of the present application. As shown in fig. 4, bit stream signals a0 to a7 of 8-bit binary data are "00111100". Taking the example of a transmission time of 500 mus per 1 bit, then binary data "0" may be represented by a high level of 500 mus or a low level of 500 mus. Binary data "1" may be represented by a low level of 250 μs plus a high level of 250 μs, or by a high level of 250 μs plus a low level of 250 μs.

When j is equal to the first value, i=j+1. Therefore, when the data of the ith bit is not stored, it indicates that the FSK decoder does not receive the bit stream signal of the new bit, and the number of data of the current bit is j.

When j is equal to 8, since i=j+1, i=9 if a bit stream signal of a new bit is received. Therefore, when the 9 th bit data is not stored, it indicates that the FSK decoder does not receive the 9 th bit data, and the current bit data number is 8.

Thus, when the FSK decoder determines that the bit data is 8 and there is no new bit data, the FSK decoder can determine that the 8 bit data is a response packet. The FSK decoder stores the 8 bits of data in a data register, and the FSK decoder sends a first interrupt signal to the processor.

The FSK decoder stores 8 bits of data in the data register so that the processor can read the 8 bits of data in the data register to cause the wireless charging receiving device to respond to the reply packet.

When j is equal to the first value, and the FSK decoder stores the data of the ith bit, indicating that the FSK decoder received the bit stream signal of the j+1th bit, the FSK decoder received no acknowledgement packet. At this point, the FSK decoder continues to store the new bit data until no more new bit stream signal is received or until j equals the second value, the FSK decoder implements step 4).

Step 4) when j is equal to the second value and the FSK decoder does not store data of i bits, the FSK decoder stores data of all bits in the data register, and when check bits and/or stop bits in the data of all bits are checked successfully, the FSK decoder sends a second interrupt signal to the processor, wherein the second interrupt signal is used for the processor to execute operation of corresponding instructions according to the data of all bits and receive a bit stream signal in the next communication process. Wherein the second value is equal to the number of bits of the data packet.

The second value may be a number of bits of the data packet. For example, when the packet is 11 bits, the second value is set to 11.

The data of all bits may represent a charge power adjustment command, a charge state command, and a charge time control command sent by the wireless charge transmitter to the wireless charge receiver. When the second value is set to 11, the data of all stored bits is 11 bits.

The second interrupt signal indicates that the communication is completed and the next communication can be performed, and the second interrupt signal indicates the processor to send out an instruction for starting the next communication. The second interrupt signal may instruct the processor to perform an operation corresponding to the data packet according to the data of all bits.

The bit stream signal of the data packet may be a second number of bits prior to decoding the data as bits. Next, taking the second value as 11 as an example, an implementation of the data packet will be described in detail.

Fig. 5 is a schematic diagram of a bit stream signal of a data packet according to an embodiment of the present application. As shown in fig. 5, the bit stream signal of 11-bit binary data is "00011110011". The bit stream signal of 11 bits may include: a start bit, a data bit, a check bit, and an end bit. Wherein the start bit is denoted by binary data "0", and the data bits b0 to b7 are denoted by "00111100". If the data bit contains an even number of "1" s, the parity bit is represented by binary data "1", otherwise, the parity bit is represented by binary data "0". The end bit is represented by binary data "1".

When j is equal to the second value, i=j+1. Therefore, when the data of the ith bit is not stored, it indicates that the FSK decoder does not receive the bit stream signal of the new bit, and the number of data of the current bit is j.

When j is equal to 11, since i=j+1, if a bit stream signal of a new bit is received, i=12. Therefore, when the 12 th bit data is not stored, it indicates that the FSK decoder does not receive the 12 th bit data, and the number of data of the current bit is 11.

When the FSK decoder judges that the bit data is 11 and no new bit data is added, the FSK decoder can determine that the 11 bit data is a data packet. The FSK decoder stores the 11 bits of data in a data register.

The FSK decoder also performs a check of the check bits and/or the stop bits on the 11-bit data stored in the data register. That is, the FSK decoder may check the check bit, may check the stop bit, and may check both the check bit and the stop bit.

Cyclic redundancy check (cyclic redundancy check, CRC) is a data transmission error detection technique, which can check the check bits and the end bits. And calculating a check code or an end bit in the wireless charging transmitter, attaching the obtained check code to a data packet, and transmitting the data packet to a wireless charging receiver. The wireless charging receiver verifies the received data packet and the check code, thereby judging whether the received data packet is correct and complete.

The FSK decoder sends a second interrupt signal to the processor when the check bit and/or the stop bit in the data of all bits is checked successfully. The processor reads 11-bit data in the data register, thereby performing an operation corresponding to the data packet according to the 11-bit data.

When j is equal to the second value and the FSK decoder stores the data of the ith bit, it indicates that the FSK decoder receives the bit stream signal of the j+1th bit, and the data of the present communication is not represented by the 11-bit data packet. At this point, the FSK decoder continues to store the new bit data until the new bit stream signal is no longer received or until j equals the third value, the FSK decoder implements step 5).

Step 5) when j is equal to the third value, the FSK decoder stores the first data of all bits from the start bit in the data register, and when the check bit and/or the stop bit in the first data are checked successfully, the FSK decoder sends a third interrupt signal to the processor, and the third interrupt signal is used for the processor to execute the operation of the corresponding instruction according to the first data and receive the bit stream signal in the next communication process. Wherein the third value is greater than the number of bits of the data packet.

The third value may be greater than the number of bits of the data packet. For example, when the packet is 15 bits, the third value is set to 15.

In the following, another implementation of the data packet will be described in detail, taking the third value as 15 as an example.

Fig. 6 is a schematic diagram of a bit stream signal of another data packet according to an embodiment of the present application. As shown in fig. 6, the bit stream signal of 15-bit binary data is "111100011110011". The bit stream signal of 15 bits may include: preamble bit, start bit, data bit, check bit and end bit. Where the preamble bits are c 0-c 3, c 0-c 3 may be represented by binary data "1111", the start bit by binary data "0", and the data bit by "00111100". If the data bit contains an even number of "1" s, the parity bit is represented by binary data "1", otherwise, the parity bit is represented by binary data "0". The end bit is represented by binary data "1".

The first data from the start bit may represent a charge power adjustment command, a charge state command, and a charge time control command sent by the wireless charging transmitter to the wireless charging receiver. Wherein the first data stored when the third value is set to 15 is 11 bits of data starting from the start bit after the preamble bit. The first data includes: a start bit, a data bit, a check bit, and an end bit.

The third interrupt signal indicates that the communication is completed and the next communication can be performed, and the third interrupt signal indicates the processor to send out an instruction for starting the next communication. The third interrupt signal may instruct the processor to perform a corresponding operation according to the first data.

Therefore, when the FSK decoder needs to detect the data packet including the preamble bit, j is set to the third value, so that the FSK decoder can accurately detect the data packet including the preamble bit, and the processor can perform a corresponding operation according to the data in the data packet.

The FSK decoder provided by the application counts the number of bits in the bit stream signal by receiving the bit stream signal in the current communication process. When the count number is equal to the first value, the FSK decoder transmits the data of the first value bit to the response packet detector, which is capable of detecting whether the data of the first value bit is a response packet. When the count number is equal to the second value or the third value, the FSK decoder sends the data of the second value or the third value to the data packet detector, and the data packet detector can detect whether the data of the second value or the third value is a data packet or not. The data of the bit obtained by decoding the bit stream signal may be an acknowledgement packet or a data packet, and the number of bits of the acknowledgement packet and the data packet is different. Typically, the response packet is 8 bits of data, and the data packet is 15 bits of data or greater than 15 bits of data. Thus, the FSK decoder can determine whether the bit stream signal is an acknowledgement packet or a data packet according to the bit number of the received bit stream signal. The FSK decoder does not have to assume in advance whether the received bitstream signal represents an acknowledgement packet or a data packet, and the FSK decoder can decode the bitstream signal into an acknowledgement packet or a data packet of a corresponding type according to the number of bits of the bitstream signal and respond to the acknowledgement packet or the data packet by the processor. Therefore, the FSK decoder can improve the detection accuracy of the detection response packet and the data packet, so that the stability of the wireless charging system is improved, and the wireless charging efficiency is improved.

The FSK decoder proposed by the present application is described in detail below. Referring to fig. 7, fig. 7 is a schematic structural diagram of an FSK decoder according to an embodiment of the present application.

As shown in fig. 7, the FSK decoder of the present application may include: an edge detector, a data decoder, a store and counter, a response packet detector, and a data packet detector.

In fig. 7, the bit stream signal is denoted BS.

The input end of the edge detector is used for inputting a bit stream signal, the output end of the edge detector is connected with the input end of the data decoder, the output end of the data decoder is connected with the input end of the storage and counter, the first output end of the storage and counter is connected with the input end of the response packet detector, the second output end of the storage and counter is connected with the input end of the data packet detector, the output end of the response packet detector is used for outputting a first interrupt signal, and the output end of the data packet detector is used for outputting a second interrupt signal or a third interrupt signal.

The edge detector can receive the bit stream signal sent by the FSK demodulator, the edge detector sequentially detects the pulse width of each bit in the bit stream signal, and when the pulse width of the bit stream signal of a certain bit accords with the preset width, the edge detector transmits one bit which accords with the preset width to the data decoder.

The data decoder is capable of receiving the bits sent by the edge detector, decoding the received bits to obtain bit data, and sending the bit data to the storage and counter. Wherein one bit of data can represent one bit of wireless charging information transmitted by the wireless charging transmitting device.

The storage and counter is capable of receiving the bit data transmitted from the data decoder, and stores and counts the bit data received each time. The store and counter sends the bit data to the reply packet detector and the data packet detector, respectively.

The response packet detector is capable of receiving the bit data stored and transmitted by the counter, and judges whether the bit data is a response packet by judging the number of bits of the bit data. In addition, the output end of the response packet detector is also used for outputting the response packet. The response packet detector may send the response packet to the data register. The number of bits of the response packet may be 8 bits, and the response packet may represent response information sent by the wireless charging transmitter.

The packet detector is capable of receiving the bit data stored and transmitted by the counter, and judges whether the bit data is a packet by judging the number of bits of the bit data. In addition, the output end of the data packet detector is also used for outputting the data packet. The packet detector may send the packet to the data register. The number of bits of the data packet may be 11 bits or 15 bits, and the data packet may represent a charging power adjustment command, a charging state command, and a charging time control command sent by the wireless charging transmitter.

Specifically, the edge detector is capable of detecting whether the width of the bit stream signal of the i-th bit corresponds to a preset width, and transmitting the bit stream signal of the i-th bit corresponding to the preset width to the data decoder.

The edge detector may detect rising and falling edges of the bit stream signal, i.e., the edge detector detects a process of the bit stream signal from a low level to a high level or from a high level to a low level. The edge detector can detect the pulse duration of every 1 bit in the bit stream signal by detecting the rising edge and the falling edge of the pulse, and time the time difference between the two pulse edges, which is the pulse width of 1 bit.

For example, when the FSK decoder sets a pulse width of 512, the edge detector detects rising and falling edges of the bit stream signal pulse of 1 bit, and calculates a time difference between both edges of the 1 bit pulse. If the time difference is equal to 512, the edge detector can determine that the pulse width of one bit is 512. The one-bit data is a bit stream signal of valid bits, and the FSK decoder performs the next processing on the valid bit stream signal, thereby detecting a data packet or a response packet.

The data decoder may decode the bit stream signal of the ith bit to obtain data of the ith bit, and transmit the decoded data of the ith bit to the storage and counter.

The store and counter is capable of storing the data of the i-th bit and updating j=j+1, i=i+1, and transmitting the data of the i-th bit to the response packet detector when j is equal to the first value, and transmitting the data of the i-th bit to the packet detector when j is equal to the second value or the third value.

The response packet detector may receive the i bits of data and store all bits of data in the data register when j is equal to the first value and the store sum counter does not store the i bits of data, the response packet detector transmitting a first interrupt signal to the processor. The response packet detector stores all bits of data by sending a response packet to the data register.

The response packet detector comprises two output ends, and the two output ends are respectively used for outputting a response packet and a first interrupt signal.

The packet detector is capable of receiving i bits of data.

When j is equal to the second value and the store and counter does not store i bits of data, the packet detector may store all bits of data in the data register, and the packet detector may send a second interrupt signal to the processor when check bits and/or stop bits in all bits of data check successfully. The packet detector stores all bits of data by sending packets to the data register.

The data packet detector comprises two output terminals for outputting the data packet and the second interrupt signal, respectively.

Or when j is equal to the third value, the data packet detector may store the first data of all bits of data from the start bit in the data register, and send a third interrupt signal to the processor when the check bit and/or the stop bit in the first data check succeeds. The data packet detector stores the first data by sending a data packet to the data register.

At this time, the two output terminals of the packet detector are respectively used for outputting the first data and the third interrupt signal.

In summary, the FSK decoder can quickly decode the bitstream signal into corresponding types of acknowledgement packets or data packets through the above devices.

The following describes in detail the implementation of the FSK decoder according to the present application with reference to fig. 8.

Referring to fig. 8, fig. 8 is a schematic structural diagram of an FSK decoder according to an embodiment of the present application.

As shown in fig. 8, in the FSK decoder, the edge detector may include: a first pulse number detector and a second pulse number detector. Wherein the number of pulses detected by the first pulse number detector is different from the number of pulses detected by the second pulse number detector.

The first pulse number detector and the second pulse detector can detect the pulse width of the bit stream signal. The first pulse number detector and the second pulse detector detect different pulse widths. For example, the first pulse number detector detects a pulse width of 128 and the second pulse detector detects a pulse width of 512.

Before the communication starts, the FSK decoder determines the pulse width of the bit stream signal to be received, sets the pulse width to be received as a preset width, and the first pulse number detector or the second pulse number detector can detect the bit stream signal with the preset width, so that the first pulse number detector or the second pulse number detector detects the width of the bit stream signal.

With continued reference to fig. 8, the data decoder may include: a data identification judgment device and a pulse number counter.

Wherein the data identification decider is capable of decoding the bitstream signal one bit at a time. The pulse number counter can count the number of times of decoding of the data discrimination judgment unit.

The data identification determiner may decode the bit stream signal of the i-th bit to obtain the data of the i-th bit. In the decoding process of the data identification judging device, the pulse number counter counts the number of the data pulses of each bit to obtain a count value. That is, the count value of the pulse number counter is incremented by 1 every 1-bit data decoded by the data identification determiner.

Continuing with fig. 8, the store and counter may include: a data shifter and a data bit number counter. Wherein the data shifter may store the data of the i-th bit and update i=i+1.

The data bit number counter may count the number of data bits of the bit and update j=j+1. When j is equal to the first value, the data bit number counter may send i bits of data to the reply packet detector. When j is equal to the second value or the third value, the data bit number counter may send i bits of data to the packet detector.

The data shifter may store the received decoded bit data. The decoded bit data are stored in the data shifter in sequence, and the data shifter stores the data of each bit in a bit mode according to a certain sequence, so that temporary storage and shifting operation of the bit data are realized.

The data bit number counter may count the number of data bits stored by the data shifter. The data shifter increments the count result by 1 each time it receives the decoded data "0" or "1".

Continuing with fig. 8, the reply packet detector may include: the reply detection comparator and the reply timeout timer.

Wherein the reply detect comparator may receive i bits of data. And, when j is equal to the first value and no data of the i-th bit is stored, the response detection comparator may detect whether the data of the i+1th bit is received. The response detection comparator may send a first stop signal to the response timeout timer when the (i+1) -th bit data is received.

The response timeout timer may set a response timeout time and count. When the first stop signal is received within the response timeout time, the response timeout timer stops counting. When the first stop signal is not received within the response timeout period, the response timeout timer may store all bits of data in the data register and send a first interrupt signal to the processor.

With continued reference to fig. 8, the packet detector may include: packet detection comparators and sync bit detection and counters.

The packet detection comparator may receive the data of the i bits, and when j is equal to the second value and the data of the i bits is not stored, detect whether the data of the i+1th bit is received, and when the data of the i+1th bit is not received, check a check bit and/or a stop bit in the data of the i bits, and send a second stop signal to the synchronous bit detection and counter when the check is successful.

The synchronous bit detection and counter can set a first data timeout time and count time, and stop counting when a second stop signal is received within the first data timeout time. And when the second stop signal is not received within the first data timeout time, storing the data of all bits in the data register and sending a second interrupt signal to the processor.

The synchronization bit detection and counter may set a second data timeout time and count time, and stop counting when a third stop signal is received within the second data timeout time. When the third stop signal is not received within the data receiving timeout period, storing the first data of all bits of data from the start bit in the data register, and transmitting a third interrupt signal to the processor.

The packet detection comparator may receive the data of the i bits, and when j is equal to the third value and the data of the i bits is not stored, detect whether the data of the i+1th bit is received, and when the data of the i+1th bit is not received, check a check bit and/or a stop bit in the data of the i bits, and send a third stop signal to the synchronous bit detection and counter when the check is successful.

The sync bit detection and counter may set a first data timeout time and a second data timeout time and count. The sync bit detection and counter may stop timing when a stop signal is received at the first data timeout time or the second data timeout time. The sync bit detection and counter may store the data packet in a data register and send a second interrupt signal or a third interrupt signal to the processor when the stop signal is not received within the reply timeout period.

In addition, the packet detection comparator can also detect the check bit and the stop bit of the received data packet to confirm the integrity and the correctness of the data packet.

The sync bit detection and counter may store the second data of all bits before the start bit in the sync bit number register when j is equal to the third value.

In summary, based on the above description of the FSK decoder, the FSK decoder may unpack the bitstream signal by the FSK unpacking method.

The specific procedure of the FSK unpacking method will be described in detail based on the structure of the FSK decoder shown in fig. 8, with reference to fig. 9.

Referring to fig. 9, fig. 9 is a flowchart of an FSK unpacking method according to an embodiment of the present application.

As shown in fig. 9, the FSK unpacking method may include:

Step 101, the edge detector receives the bit stream signal in the current communication process. The bit stream signal is obtained by demodulating the FSK signal sent by the wireless charging sending device, the bit number of the bit stream signal is N, and N is a positive integer.

Step 102, when the width of the bit stream signal of the ith bit accords with the preset width, decoding the bit stream signal of the ith bit to obtain data of the ith bit, storing the data of the ith bit, updating j=j+1, updating i=i+1, taking positive integers larger than or equal to 1 and smaller than or equal to N, taking integers larger than or equal to 0 and smaller than or equal to i, until the following is satisfied, and continuously receiving the bit stream signal in the next communication process:

When j is equal to the first value and the storage and counter does not store the data of the ith bit, the data of all bits are stored in the data register, and the response packet detector sends a first interrupt signal to the processor, wherein the first interrupt signal is used for the processor to execute the operation of a corresponding instruction according to the data of all bits and receive a bit stream signal in the next communication process. Wherein the first value is equal to the number of bits of the reply packet.

Or when j is equal to the second value and the storage and counter does not store the data with i bits, storing the data with all bits in the data register, and sending a second interrupt signal to the processor when the check bit and/or the stop bit in the data with all bits are checked successfully by the data packet detector, wherein the second interrupt signal is used for the processor to execute the operation of the corresponding instruction according to the data with all bits and receive the bit stream signal in the next communication process. Wherein the second value is equal to the number of bits of the data packet.

Or when j is equal to a third value, storing first data of all bit data from a start bit in a data register, and sending a third interrupt signal to the processor when check bits and/or stop bits in the first data are checked successfully, wherein the third interrupt signal is used for the processor to execute corresponding instruction operation according to the first data and receive a bit stream signal in the next communication process. Wherein the third value is greater than the number of bits of the data packet.

Therefore, by the FSK unpacking method, the FSK decoder can detect the data packet and the response packet, so that the wireless charging efficiency is improved.

In the above-described embodiments, all or part of the functions may be implemented by software, hardware, or a combination of software and hardware. When implemented in software, may be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the processes or functions in accordance with the present application are produced in whole or in part. The computer may be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions may be stored in a computer readable storage medium. The computer readable storage medium may be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. that contains an integration of one or more available media. The usable medium may be a magnetic medium (e.g., floppy disk, hard disk, tape), an optical medium (e.g., DVD), or a semiconductor medium (e.g., solid State Disk (SSD)), etc.

Those of ordinary skill in the art will appreciate that implementing all or part of the above-described method embodiments may be accomplished by a computer program to instruct related hardware, the program may be stored in a computer readable storage medium, and the program may include the above-described method embodiments when executed. And the aforementioned memory includes: a read-only memory (ROM) or a random access memory (random access memory, RAM), a magnetic disk or an optical disk, or the like.

Claims

1. An FSK decoder is characterized by being applied to a wireless charging receiving device;

the FSK decoder is used for:

receiving a bit stream signal in the current communication process, wherein the bit stream signal is obtained by demodulating an FSK signal sent by a wireless charging and sending device, the bit stream signal comprises N pulses, N bits correspond to the N bits, and N is a positive integer;

2. The FSK decoder according to claim 1, wherein said determining a data type corresponding to said bitstream signal from said decoded real-time count value of bits and storing data in said data register in a memory corresponding to said data type comprises:

Under the condition that the real-time count value is equal to a first value and new bits are not obtained through further decoding, determining that the received bit stream signal is a response packet, and storing the bits obtained through decoding stored in the data register into a memory corresponding to the response packet, wherein the first value is equal to the bit number of the response packet;

or under the condition that the real-time count value is equal to a second value and a new bit is not obtained by further decoding, determining that the received bit stream signal is a data packet, and storing the bit obtained by decoding stored in the data register into a memory corresponding to the data packet; wherein the second value is equal to the number of bits of the data packet;

Or when the real-time count value is equal to a third value, determining that the received bit stream signal is a data packet, and storing first data of all bits from a start bit in a data register, wherein the third value is larger than the bit number of the data packet.

3. The FSK decoder according to claim 2, wherein after determining the data type corresponding to the bitstream signal from the real-time count value of the decoded bits and storing the data in the data register in the memory corresponding to the data type, further comprising:

Transmitting a first interrupt signal to a processor when the real-time count value is equal to the first value and a new bit is not decoded further, wherein the first interrupt signal is used for the processor to execute the operation of a corresponding instruction according to the data of all bits and receive a bit stream signal in the next communication process;

When the real-time count value is equal to the second value and the new bit is not obtained through further decoding, a second interrupt signal is sent to a processor when check bits and/or stop bits in the data of all bits are checked successfully, and the second interrupt signal is used for the processor to execute the operation of a corresponding instruction according to the data of all bits and receive a bit stream signal in the next communication process;

4. The FSK decoder according to claim 1, wherein the FSK decoder comprises: an edge detector, a data decoder, and a store and counter;

The input end of the edge detector is used for inputting the bit stream signal, the output end of the edge detector is connected with the input end of the data decoder, and the output end of the data decoder is connected with the input end of the storage and counter;

the edge detector is configured to determine whether a pulse width in the bitstream signal meets the preset width, and send the bitstream signal meeting the preset width to the data decoder;

The data decoder is used for decoding a bit stream signal conforming to a preset width and transmitting the bit obtained by decoding to the storage and counter;

The storage and counter is used for counting the bits obtained by decoding to obtain the real-time count value and storing the bits obtained by decoding and the real-time count value;

the storage and counter is further configured to determine a data type corresponding to the bitstream signal according to the real-time count value of the decoded bit, and send the decoded bit to a memory corresponding to the data type.

5. The FSK decoder of claim 4, further comprising: a response packet detector and a data packet detector;

The first output end of the storage and counter is connected with the input end of the response packet detector, the second output end of the storage and counter is connected with the input end of the data packet detector, the output end of the response packet detector is used for outputting a response packet and a first interrupt signal, and the output end of the data packet detector is used for outputting a data packet, and a second interrupt signal or a third interrupt signal;

The response packet detector is configured to receive the decoded bits, store data of all bits in a memory corresponding to the response packet when the real-time count value is equal to a first value and the real-time count value is not further decoded to obtain new bits, and send a first interrupt signal to the processor;

The data packet detector is used for receiving the bit obtained by decoding;

The data packet detector is further configured to store data of all bits in a memory corresponding to the data packet when the real-time count value is equal to a second value and no new bits are obtained by further decoding, and send a second interrupt signal to the processor when check bits and/or stop bits in the data of all bits are successfully checked; or when the real-time count value is equal to a third value, storing the first data in a memory corresponding to the data packet, and sending a third interrupt signal to the processor when the check bit and/or the stop bit in the first data are successfully checked.

6. The FSK decoder according to claim 5 wherein said edge detector comprises: a first pulse number detector and a second pulse number detector; wherein the number of pulses detected by the first pulse number detector and the second pulse number detector are different.

7. The FSK decoder according to claim 5 or 6, wherein the data decoder comprises: a data identification judgment device and a pulse number counter.

8. The FSK decoder according to any of claims 4 to 7 wherein said store and counter comprises: a data shifter and a data bit number counter;

the data shifter is used for storing the bit obtained by decoding;

The data bit number counter is configured to count the decoded bits to obtain the real-time count value, send the decoded bits to the response packet detector when the real-time count value is equal to the first value, and send the decoded bits to the data packet detector when the real-time count value is equal to the second value or the third value.

9. The FSK decoder according to any of claims 4 to 8 wherein said acknowledgement packet detector comprises: a response detection comparator and a response timeout timer;

The response detection comparator is configured to receive the decoded bit, detect whether to further decode to obtain a new bit when the real-time count value is equal to a first value, and send a first stop signal to the response timeout timer when the further decoded bit is received;

The response timeout timer is used for setting response timeout time and timing, and stopping timing when the first stop signal is received in the response timeout time; and when the first stop signal is not received within the response timeout time, storing data of all bits in a memory corresponding to the response packet, and sending a first interrupt signal to a processor.

10. The FSK decoder according to any of claims 4 to 9 wherein said packet detector comprises: a packet detection comparator and a sync bit detection and counter;

The information packet detection comparator is used for receiving the bit obtained by decoding, detecting whether to further decode to obtain a new bit when the real-time count value is equal to a second value, checking check bits and/or stop bits in the bit data obtained by decoding when the new bit is not further decoded, and sending a second stop signal to the synchronous bit detection and counter when the check is successful;

The packet detection comparator is further configured to receive the bit data obtained by decoding, detect whether to further decode to obtain a new bit when the real-time count value is equal to a third value, and check a check bit and/or a stop bit in the bit obtained by decoding when the new bit is not further decoded, and send a third stop signal to the synchronous bit detection and counter when the check is successful;

The synchronous bit detection and counter is used for setting a first data timeout time and timing, and stopping timing when the second stop signal is received in the first data timeout time; when the second stop signal is not received within the first data timeout time, storing data of all bits in a memory corresponding to the data packet, and sending a second interrupt signal to a processor;

The synchronous bit detection and counter is also used for setting a second data timeout time and timing, and stopping timing when the third stop signal is received in the second data timeout time; and when the third stop signal is not received within the data receiving timeout time, storing the first data of all bits from the start bit in a memory corresponding to the data packet, and sending a third interrupt signal to a processor.

11. The FSK decoder of claim 10 wherein said sync bit detection and counter is further configured to store in said sync bit number register a second data of all bits preceding the start bit when said real time count value is equal to a third value.

12. An FSK unpacking method, characterized by being applied to an FSK decoder according to any of claims 1-11; the method comprises the following steps:

13. The FSK unpacking method according to claim 12, further comprising:

And discarding the bit stream signal and sending prompt information to a processor when the width of the bit stream signal of the bit obtained by decoding does not accord with the preset width, wherein the prompt information is used for prompting the bit stream signal receiving error and receiving the bit stream signal in the next communication process.

14. The FSK unpacking method according to claim 12 or 13, characterized in that said method further comprises:

And when the real-time count value is equal to the third value, storing second data of all bits of data before the start bit in the synchronous bit number register.

15. A wireless charging reception apparatus, characterized in that the wireless charging reception apparatus comprises: processor, FSK demodulator, data register and FSK decoder according to any of claims 1 to 11.

16. A chip, comprising: an FSK decoder according to any of claims 1 to 11, or a wireless charging receiving device according to claim 15.

17. An electronic device, comprising: the wireless charging receiving device of claim 15.