CN118214433A - Parallel de-interleaver and de-interleaving method suitable for 5G LDPC code - Google Patents

Abstract

The invention provides a parallel de-interleaver and a method suitable for a 5G LDPC code, wherein the parallel de-interleaver comprises a parameter calculation module, a bit de-interleaving module and a bit splicing module which are cascaded, and the output end of the parameter calculation module is also connected with the input end of the bit splicing module; the de-interleaving method comprises initializing parallel codeword data and decoding parameters of a 5G LDPC code; the parameter calculation module calculates the length of the residual bits at the end of each de-interleaving block; the parameter calculation module calculates the parameter of each de-interleaving block; the bit de-interleaving module performs bit de-interleaving processing on the parallel codeword data; and the bit splicing module acquires a de-interleaving result of the 5G LDPC code. The invention obtains the effective bit of each element in the de-interleaving block matrix through splicing, and widens the application range of the de-interleaving device; by adjusting the arrangement mode of the parallel codeword data, the generation of the de-interleaving address is avoided, the participation of hardware is less, and the resource consumption is reduced.

Description

Parallel de-interleaver and de-interleaving method suitable for 5G LDPC code

Technical Field

The invention belongs to the technical field of basic electronic circuits, relates to a parallel de-interleaver and a de-interleaving method, and in particular relates to a parallel de-interleaver and a de-interleaving method suitable for a 5G LDPC code.

Background

The low-density parity check code LDPC code has excellent performance, can realize high-throughput transmission, and is one of digital channel coding schemes in a 5G system of a fifth generation communication technology. The 5G LDPC code is of a quasi-cyclic structure, is not good at correcting burst errors, and because of channel interference, the 3GPP conference points out that an interleaving/de-interleaving scheme needs to be added in a system, so that the burst errors are converted into random errors, and the interleaving mode is block interleaving, thereby improving the reliability of information.

According to the 3GPP conference 38# protocol, the uplink and downlink resource allocation situation is defined that in a physical layer link channel, the range of a modulation coding mode MCS (modulation and coding scheme) is 0-27, a protocol table determines the modulation order Q (modulation order) and the code rate R (target code rate) according to parameters such as MCS, the like, the residual parameters such as code length and the like are influenced by the MCS, the channel condition and the system resource, the parameter variation range is wide, the span is large, and the complexity of system design is greatly increased. The decoding system comprises a data processing part, an iterative calculation part and an output verification part, and after receiving codeword data and parameters transmitted by a channel, the decoding system firstly needs to process the codeword data according to the parameters. The deinterleaver is used as an important link of a data processing part of the decoding system, and has the characteristics of low resource consumption, strong universality, high throughput, realization of data temporary storage and the like.

The parallel de-interleaving of the 5G LDPC code refers to simultaneous input or output of a plurality of bits, for example, a parallel interleaver, a de-interleaver and a method applicable to the 5G-NR are disclosed in the patent application with the application publication number CN 111555761A, and the parallel de-interleaver and the method applicable to the 5G LDPC code are provided, and the parallel de-interleaver of the invention comprises at least two bit de-interleaving modules, a ping-pong controller, an input channel switching module and an output channel switching module; the interleaving method is that each interleaving module is connected with an input switching module, interleaving processing is carried out on different input parallel data, a matrix construction unit stores binary 5G LDPC codes cached in a read-write buffer according to interleaving addresses, and after data storage is finished, codeword splicing is carried out according to output parallelism and interleaving results are output. The invention improves the data throughput by improving the parallelism of data processing in the deinterleaver, reduces the processing delay, is suitable for the deinterleaving or interleaving data processing flow using the LDPC channel coding mode in the physical channel in 5G-NR, but has poorer flexibility because the bit width of input data is in bytes, and has limited application range of the deinterleaver because of the existence of a ping-pong input controller and a plurality of bit deinterleaving modules and the generation of a deinterleaving address, additionally increases the resource consumption, and has 1 bit granularity when the 5G LDPC code is segmented, and has length difference among different blocks, and the data needs to be spliced again.

Disclosure of Invention

The invention aims to provide a parallel de-interleaver suitable for 5G LDPC aiming at the defects in the prior art, which is used for solving the technical problems of narrow application range, large resource consumption and low flexibility in the prior art.

In order to achieve the above purpose, the technical scheme adopted by the invention is as follows:

The parallel de-interleaver suitable for the 5G LDPC code comprises a cascaded parameter calculation module, a bit de-interleaving module and a bit splicing module, wherein the output end of the parameter calculation module is also connected with the input end of the bit splicing module; the bit de-interleaving module comprises a cascade branch jumping unit, a register matrix construction unit, Q parallel first-in first-out read-write buffers and an output control unit, wherein the branch jumping unit comprises a plurality of parallel jumping branches; the register matrix constructing unit comprises Q parallel bus registers; the bit splicing module comprises a shift register and a code word splicing unit which are cascaded, wherein Q is more than or equal to 1.

A method of deinterleaving of the parallel deinterleaver of claim 1 comprising the steps of:

(1) Initializing parallel codeword data and decoding parameters of a 5G LDPC code:

The decoding parameters of the binary 5G LDPC code after interleaving by the initialization encoder comprise a modulation order Q and the number of de-interleaving blocks C, and the length of each de-interleaving block is E _c; the parallel multiple codeword data of the 5G LDPC code have the parallelism of P and the bit width of W, wherein P is more than or equal to 1, and W is any positive integer;

(2) The parameter calculation module calculates the end remaining bit length of each de-interleaved block:

The parameter calculation module calculates the column number M _c of the matrix of each de-interleaving block according to the modulation order Q and the length E _c of each de-interleaving block, and calculates the tail residual bit length L _c of each de-interleaving block according to M _c and the parallelism P of the code word data;

(3) The parameter calculation module calculates the parameters of each de-interleaving block:

The parameter calculation module calculates the parameters of each de-interleaving block when L _c is more than 0, wherein the parameters comprise a data length R _c, a temporary storage data length Er _c, a data shift register shift coefficient N _c, a parallel bit splicing coefficient T _c and a shift factor S _c;

(4) The bit de-interleaving module performs bit de-interleaving processing on the parallel codeword data:

The bit de-interleaving module adjusts the arrangement mode of a plurality of parallel codeword data of the 5G LDPC code, constructs a matrix F _QM with the dimension of Q multiplied by M through the adjusted data, then caches the matrix F _QM, and then transversely partitions the cached matrix by taking M _c as a unit to obtain a de-interleaving block matrix with the dimension of Q multiplied by M _c, wherein the C de-interleaving block matrix is M＝{M₁,M₂,…,M_c,…,M_C}；

(5) The bit splicing module acquires a de-interleaving result of the 5G LDPC code:

The bit splicing module judges whether L _c > 0 is true, if yes, the invalid bit in F _qm is removed according to the parameter of each de-interleaving block calculated in the step (3) and each element F _qm in F _QM, and the valid bit is spliced, then P multiplied by W valid bits in F _qm obtained by splicing are used as the de-interleaving result of the 5G LDPC code, otherwise, the invalid bit is removed Is a result of deinterleaving of the 5G LDPC code.

Compared with the prior art, the invention has the following advantages:

1. In the process of obtaining the de-interleaving result of the 5G LDPC code, the bit splicing module eliminates the invalid bit of each element in the de-interleaving block matrix and splices the valid bit, thereby avoiding the defect that the length difference exists between different blocks in the prior art and effectively widening the application range of the de-interleaver.

2. The invention adjusts the arrangement mode of a plurality of parallel codeword data of the 5G LDPC code through the bit de-interleaving module, avoids generating de-interleaving addresses, and the parallel de-interleaving device only comprises three modules, does not need to participate in a ping-pong input controller and a plurality of bit de-interleaving modules, and reduces resource consumption compared with the prior art.

3. The bit de-interleaving module and the parameter calculation module in the invention can realize parallel de-interleaving operation supporting input codeword data with arbitrary bit width and parallelism, so that the flexibility is improved.

Drawings

Fig. 1 is a schematic diagram of a parallel deinterleaver according to the present invention.

Fig. 2 is a schematic diagram of a bit de-interleaving module according to the present invention.

FIG. 3 is a schematic diagram of the bus register of the present invention for adjusting the arrangement of parallel data.

Fig. 4 is a flowchart of an implementation of the de-interleaving method of the present invention.

Fig. 5 is a schematic diagram of shift register shifting and truncation in the bit-concatenation module of the present invention.

Fig. 6 is a schematic diagram of a codeword splicing unit interception and splicing in a bit splicing module of the present invention.

Detailed Description

The invention is described in further detail below with reference to the attached drawings and specific examples:

Referring to fig. 1, the parallel deinterleaver of the present invention includes a parameter calculation module, a bit deinterleaving module and a bit splicing module which are cascaded, and the output end of the parameter calculation module is also connected with the input end of the bit splicing module; the bit de-interleaving module has a structure shown in fig. 2 and comprises a cascade branch jumping unit, a register matrix construction unit, Q parallel first-in first-out read-write buffers and an output control unit, wherein the branch jumping unit comprises a plurality of parallel jumping branches; the register matrix constructing unit comprises Q parallel bus registers; the bit splicing module comprises a shift register and a code word splicing unit which are cascaded, wherein Q is more than or equal to 1. In this embodiment, p= 8,Q =4 and w=6.

Bit interleaving is part of the rate matching in coding and de-interleaving is the inverse of interleaving in coding. The modulation order is Q, the length of the c de-interleaving block of E _c, and the data before de-interleaving is assumed to beThe deinterleaved data isThe operation procedure is as follows:

The branch jumping unit comprises 6 branches, jumps to the corresponding branch under the condition of Q=4, and carries out de-interleaving operation according to the interleaving mode and the input data; the register matrix constructing unit includes 4 bus registers REG0 to REG3 with 48 bits, each bus register performs a de-interleaving process on the input 8 parallel data, referring to fig. 3, considering that 48 parallel 5G LDPC code data are input, the data are put into the bus registers REG0 to REG3 according to the illustrated sequence, when the bus register REG0 is full of 48 bits, one element F _1m in the matrix F _QM is obtained, REG0 to REG3 constructs 4 elements in the matrix F _QM at the same time, namely F _1m～f_4m, the first-in first-out read-write buffer starts to buffer the data, and the values in the 4 bus registers at this time are stored in the 4 first-in first-out read-write buffers as the elements F _1m of the matrix.

According to the bit de-interleaving module constructed by the method, for the interleaving mode of block interleaving, a de-interleaving mode of 'writing according to columns and reading according to rows' is adopted, a register matrix constructing unit in the bit de-interleaving module is used, and a matrix is constructed through parallel 4 bus registers with fixed widths, so that the generation of extra de-interleaving addresses is avoided. The first-in first-out read-write buffer is used for buffering one row in the matrix, various Q values can be adapted by adjusting the number of the first-in first-out buffer, the subsequent 5G LDPC codeword data can be continuously input due to the fact that the first-in first-out buffer does not need address control, the output of the bit deinterleaving module is not needed after the whole deinterleaving block matrix is completely constructed, the overlong occupation of the data in the buffer resource and the data loss of the subsequently input codeword due to the overflow of the buffer resource are avoided, and the participation of a ping-pong input controller and a plurality of bit deinterleaving modules is not needed; in this embodiment, q=4, the method may complete the read-write operation on Q caches at the same time (in one clock), and adopt fifo buffers, and adopt the same enabling control to support multiple paths of data read-write, and according to different modes, branches select different combination modes, so that each fifo buffer is fully utilized, and redundancy of resources is reduced.

The bus register and the first-in first-out buffer in the bit de-interleaving module constructed according to the method can flexibly adjust the bit width according to the input data bit width and the parallelism on the basis of not changing the overall structure and the number, and the correct bit de-interleaving result is obtained. The bit width of the input data has important influence on the resource consumption in the hardware realization process, the bit width of the input data is closely related to the precision of a decoding system, the parallelism of the input data influences the parallelism of a de-interleaver, and the realization of the flexibility of the input data has important significance. According to the parameters calculated by the parameter calculation module, the correctness of the parallel data in the parallel de-interleaving process is ensured, so that the flexibility is improved.

Referring to fig. 4, the deinterleaving method of the present invention includes the steps of:

step 1) initializing parallel codeword data and decoding parameters of a 5G LDPC code:

The decoding parameters of the binary 5G LDPC code after interleaving by the initialization encoder comprise a modulation order Q and the number of de-interleaving blocks C, and the length of each de-interleaving block is E _c; the parallel multiple code word data of the 5G LDPC code, the parallelism of the code word data is P, the bit width of the code word data is W, wherein P is more than or equal to 1, and W is any positive integer. Consider an implementation under p= 8,Q =4, w=6, c=7.

Initializing parallel codeword data of the 5G LDPC code to be binary 5G LDPC code data which is received by a physical layer and sent by an MAC layer to be encoded and interleaved by an encoder, inputting 8 codeword data of 6 bits in parallel by a parallel de-interleaver in one clock, and considering that the actual transmission bit number of the codeword data is G= 61440, namely 7680 clock cycles are required, and inputting all transmission bits of the codeword data can be completed.

According to the 3GPP protocol, the initial decoding parameters are sent by the physical layer to the MAC layer, and are used for representing the number C of blocks which can be formed by the codeword data G and the characteristic coefficient modulation order Q of a deinterleaver specified by MCS, and the length E _c of each deinterleaved block is implemented according to the 3GPP protocol, and the following operation procedures are carried out:

Considering that the actual transmission bit number of the 5G LDPC code is g= 61440, the values of the blocks E _c appear differently and are distributed as e= {8776,8776,8776,8776,8776,8780,8780}.

Step 2) the parameter calculation module calculates the end remaining bit length of each de-interleaving block:

The parameter calculation module calculates the column number M _c of the matrix of each de-interleaving block according to the modulation order Q and the length E _c of each de-interleaving block, and calculates the tail residual bit length L _c of each de-interleaving block according to the parallelism P of M _c and code word data, wherein the calculation formula is as follows:

L_c＝mod(M_c,P)

where mod (. Cndot.) represents the remainder operation, The representation is rounded down.

According to the above calculation formula, the distribution of M _c,M_c of each matrix column number of the de-interleaving block is calculated as m= {2194,2194,2194,2194,2194,2195,2195}, and the length L _c of the remaining bits at the end of each de-interleaving block is calculated as l= {2,2,2,2,2,3,3}.

Step 3) the parameter calculation module calculates the parameters of each de-interleaving block:

The parameter calculation module calculates parameters of each de-interleaving block when L _c is more than 0, wherein the parameters comprise a data length R _c, a temporary storage data length Er _c, a data shift register shift coefficient N _c, a parallel bit splicing coefficient T _c and a shift factor S _c, and the parameters comprise:

T_c＝{t₁,t₂,…,t_q,…,t_Q}

R_c＝mod(R_c-1+L_c,P)

Er_c＝P-R_c

N_c＝Er_c×W

t_q＝mod(t_q-1-L_c,P)

where T _q represents the q-th element in the c-th parallel bit-splice coefficient T _c, mod (·) represents the remainder operation.

L= {2,2,2,2,2,3,3}, each block L _c value is greater than 0, and the parameter calculation module calculates the parameter of each deinterleaved block. The parameter calculation module calculates parameters required by the bit splicing module, wherein the data length R _c, the temporary data length Er _c and the shift coefficient N _c,R_c of the data shift register are distributed as R= {2,4,6,0,2,5,0}, the Er _c is distributed as Er= {0,6,4,2,0,6,3}, and the N _c is distributed as N= {0,36,24,12,0,36,18}.

Step 4) the bit de-interleaving module performs bit de-interleaving processing on the parallel codeword data:

The bit de-interleaving module adjusts the arrangement mode of a plurality of parallel codeword data of the 5G LDPC code, constructs a matrix F _QM with the dimension of Q multiplied by M through the adjusted data, then caches the matrix F _QM, and then transversely partitions the cached matrix by taking M _c as a unit to obtain a de-interleaving block matrix with the dimension of Q multiplied by M _c, wherein the C de-interleaving block matrix is M= { M ₁,M₂,…,M_c,…,M_C }, the implementation steps are:

consider a specific implementation under m= {2194,2194,2194,2194,2194,2195,2195}, p= 8,Q =4, w=6, c=7.

Step 4 a), selecting an interleaving mode corresponding to the modulation order by a branch jumping unit through jumping branches with the same modulation order; q bus registers in the register matrix constructing unit adjust the arrangement mode of the parallel codeword data according to the selected interleaving mode, and construct a matrix F _QM with dimension of Q multiplied by M through the adjusted data:

Wherein f _qm is that the q-th bus register contains p×w bits of data; in this embodiment, the sum of the columns of all the matrix of the deinterleaved blocks in M is 7680, which indicates that the constructed matrix contains 4 rows 7680 columns, and one element f _qm is 48 bits of data.

Step 4 b), the q-th first-in first-out read-write buffer buffers the q-th data in the matrix F _QM; for convenience of description, the 4 FIFO read/write buffers in the subsequent steps are denoted as FIFO1 to FIFO4, and FIFO1 stores the first row element of matrix F _4,7680, including all elements { F _1,1,f_1,2,…,f_1,7680 }.

Step 4 c) when M > M _c/Q, the output control unit adds a row pointer to the matrix F _QM, when the row pointer points to the last element of the qth row of the c-th deinterleaved block matrix of F _QM At that time, the line pointer update points to the (q+1) th line, and so on, until the line pointer points to/>The last element/>When the matrix/>, of the de-interleaving block of the c de-interleaving block is obtained

When a downstream module signal is received, it indicates that the memories in other peripheral modules of the current decoding system are empty, data loss caused by repeated writing cannot occur, an output control unit in the bit deinterleaving module is in a working state, and since data writing is 4 groups of intermittent writing, data reading is continuous reading, in order to ensure the continuity of data output, meanwhile, the throughput of the parallel deinterleaving device is improved, the requirement that the storage time of the data in a buffer memory is excessively long and the depth of the buffer memory is increased is avoided, taking c=1 and e ₁ =8776 as an example, a parameter calculation module calculates that the column number of the deinterleaving block matrix is M ₁ =2194, and when the matrix elements cached in the FIFO1 are f _1,549, namely, the total number of matrix elements cached in all 4 first-in first-out read-write buffers is 2196, the output control unit performs line pointer update, and the line pointer points to the matrix element f _1,1. When the line pointer points to F _1,2194, it indicates that the 1 st line of the 4×2194-dimensional deinterleaved block matrix divided by c=1 block has completed outputting, and so on, until the line pointer points to the element F _4,2194, it indicates that the block corresponding construction matrix has been completely read out in the fifo buffer, and the deinterleaved block matrix F _4,2194 of the 1 st deinterleaved block is obtained. Repeating the above operation to obtain the rest de-interleaving block matrix.

Step 5) the bit splicing module obtains a de-interleaving result of the 5G LDPC code:

The bit splicing module judges whether L _c > 0 is true, if yes, the invalid bit in F _qm is removed according to the parameter of each de-interleaving block calculated in the step (3) and each element F _qm in F _QM, and the valid bit is spliced, then P multiplied by W valid bits in F _qm obtained by splicing are used as the de-interleaving result of the 5G LDPC code, otherwise, the invalid bit is removed Each element f _qm in the 5G LDPC code is used as a deinterleaving result, and the implementation steps are as follows:

Step 5 a), the bit de-interleaving module outputs data, the data is put into the low order of a shift register, the shift register shifts left by S multiplied by W bits, when the bit de-interleaving module does not output data When in data, the bit de-interleaving module outputs high P multiplied by W bits of the shift register;

Referring to fig. 5, when c=2, L ₂ =2, satisfying the condition greater than 0, consider that the bit deinterleaving module obtains the 2 nd deinterleaved block matrix as example F _4,2194, the number of rows of the deinterleaved block matrix is 4, consider that the bit deinterleaving module obtains the 2 nd element F _1,2 of 1 row in the matrix F _4,2194, that is, the 2 nd element in the storage FIFO1 is the element F _1,2 in the matrix pointed to by the line pointer of the output control unit in the bit deinterleaving module at this time; the element F _1,2 is put into the lower 48 bits of the shift register, at this time, the elements in the shift register are F _1,1 and the element F _1,2 are sequentially arranged, S ₂ =6 in the deinterleaved block matrix parameters calculated by the parameter calculation module, the shift register shifts left by 36 bits, and when the bit deinterleaving module does not output the data of the last element F _q2194 of each row of the 2 nd deinterleaved block matrix as an example F _4,2194, the shift register in the bit splicing module intercepts the upper 48 bits as the deinterleaving result of the 5G LDPC code.

Step 5 b) when the bit de-interleaving module outputsWhen data is processed, the code word splicing unit intercepts the high (P-T _q-S_c) multiplied by W bits of the shift register and the data is obtained by/(I)The bits and N _c XW bits in the shift of the data shift register in the code word splicing unit sequentially form new P XW bits, and the bit de-interleaving module outputs the new P XW bits.

Referring to fig. 6, since there is no bit deinterleaving module output when the bit deinterleaving module outputs the data of the element F _1,2194 of the 1 st row of the 1 st deinterleaving block matrix, but it is not the legacy data of the output result of the 5G LDPC code, in order to improve the example versatility, when considering the bit deinterleaving module outputs the data of the last element F _1,2194 of the 1 st row of the 2 nd deinterleaving block matrix F _4,2194, the FIFO1 output data is read at this time, the deinterleaver output needs to perform additional splicing operation according to the parameters of R ₂、S₂、N₂ in the bit splicing parameters of the 2 nd deinterleaving block and the 1 st element T ₁ in the T ₂, at this time, the data shift register shifts by a factor N ₂ =4, which means that the 48 bit data output by the FIFO1 only needs to output the high 24 bits at this time, the remaining 24 bits need to be temporarily output as the legacy bits, the data shift register needs to be temporarily stored, the FIFO1 st row of the 3 rd deinterleaving block is output when waiting for c=3, and the element of the FIFO1 is output again; at this time, the parallel bit splicing coefficient t ₂＝4,S₂ =2, and the data shift register and the shift register which output and temporarily store the legacy bits at this time are cut and spliced according to the parameters, that is, the high 12 bits of the shift register, the 12 bits in f _1,2194 and the 24 bits in the shift of the data shift register in the code word splicing unit are cut and spliced, so that new 48-bit data are obtained and used as the de-interleaving result of the 5G LDPC code.

The foregoing description is only a specific example of the invention, and it will be apparent to those skilled in the art that various modifications and changes in form and detail may be made without departing from the principles and construction of the invention, but these modifications and changes based on the idea of the invention are still within the scope of the appended claims.

Claims (6)

1. The parallel de-interleaver suitable for the 5G LDPC code is characterized by comprising a cascaded parameter calculation module, a bit de-interleaving module and a bit splicing module, wherein the output end of the parameter calculation module is also connected with the input end of the bit splicing module; the bit de-interleaving module comprises a cascade branch jumping unit, a register matrix construction unit, Q parallel first-in first-out read-write buffers and an output control unit, wherein the branch jumping unit comprises a plurality of parallel jumping branches; the register matrix constructing unit comprises Q parallel bus registers; the bit splicing module comprises a shift register and a code word splicing unit which are cascaded, wherein Q is more than or equal to 1.

2. A method of deinterleaving of a parallel deinterleaver as claimed in claim 1, comprising the steps of:

(1) Initializing parallel codeword data and decoding parameters of a 5G LDPC code:

The decoding parameters of the binary 5G LDPC code after interleaving by the initialization encoder comprise a modulation order Q and the number of de-interleaving blocks C, and the length of each de-interleaving block is E _c; the parallel multiple codeword data of the 5G LDPC code have the parallelism of P and the bit width of W, wherein P is more than or equal to 1, and W is any positive integer;

(2) The parameter calculation module calculates the end remaining bit length of each de-interleaved block:

The parameter calculation module calculates the column number M _c of the matrix of each de-interleaving block according to the modulation order Q and the length E _c of each de-interleaving block, and calculates the tail residual bit length L _c of each de-interleaving block according to M _c and the parallelism P of the code word data;

(3) The parameter calculation module calculates the parameters of each de-interleaving block:

The parameter calculation module calculates the parameters of each de-interleaving block when L _c is more than 0, wherein the parameters comprise a data length R _c, a temporary storage data length Er _c, a data shift register shift coefficient N _c, a parallel bit splicing coefficient T _c and a shift factor S _c;

(4) The bit de-interleaving module performs bit de-interleaving processing on the parallel codeword data:

The bit de-interleaving module adjusts the arrangement mode of a plurality of parallel codeword data of the 5G LDPC code, constructs a matrix F _QM with the dimension of Q multiplied by M through the adjusted data, then caches the matrix F _QM, and then transversely partitions the cached matrix by taking M _c as a unit to obtain a de-interleaving block matrix with the dimension of Q multiplied by M _c, wherein the C de-interleaving block matrix is M＝{M₁,M₂,…,M_c,…,M_C}；

(5) The bit splicing module acquires a de-interleaving result of the 5G LDPC code:

The bit splicing module judges whether L _c > 0 is true, if yes, the invalid bit in F _qm is removed according to the parameter of each de-interleaving block calculated in the step (3) and each element F _qm in F _QM, and the valid bit is spliced, then P multiplied by W valid bits in F _qm obtained by splicing are used as the de-interleaving result of the 5G LDPC code, otherwise, the invalid bit is removed Is a result of deinterleaving of the 5G LDPC code.

3. The deinterleaving method of claim 2, wherein the end remaining bit length L _c of each of the deinterleaving blocks in step (2) is calculated by the following formula:

L_c＝mod(M_c,P)

where mod (. Cndot.) represents the remainder operation, The representation is rounded down.

4. The deinterleaving method of claim 2, wherein the parameters of each of the deinterleaving blocks of step (3) are selected from the group consisting of:

T_c＝{t₁,t₂,…,t_q,…,t_Q}

R_c＝mod(R_c-1+L_c,P)

Er_c＝P-R_c

N_c＝Er_c×W

t_q＝mod(t_q-1-L_c,P)

where T _q represents the q-th element in the c-th parallel bit-splice coefficient T _c, mod (·) represents the remainder operation.

5. The deinterleaving method of claim 2, wherein the bit deinterleaving module in step (4) performs bit deinterleaving processing on the parallel codeword data, the implementation steps being:

(4a) The branch jump unit selects an interleaving mode corresponding to the modulation order through a jump branch with the same modulation order; q bus registers in the register matrix constructing unit adjust the arrangement mode of the parallel codeword data according to the selected interleaving mode, and construct a matrix F _QM with dimension of Q multiplied by M through the adjusted data:

wherein f _qm is that the q-th bus register contains p×w bits of data;

(4b) The q-th first-in first-out read-write buffer buffers the q-th data in the matrix F _QM;

(4c) When M is larger than M _c/Q, the output control unit adds a line pointer to the matrix F _QM, and when the line pointer points to the last element of the Q-th line of the c-th de-interleaving block matrix of F _QM At that time, the line pointer update points to the (q+1) th line, and so on, until the line pointer points to/>The last element/>When the matrix/>, of the de-interleaving block of the c de-interleaving block is obtained

6. The deinterleaving method of claim 2, wherein the P x W effective bits in f _qm in step (5) are obtained by:

(5a) The shift register registers each element F _qm in F _QM to the lower bits of the shift register and shifts left the data registered therein by S W bits when not registered When elements are generated, the bit splicing module takes P multiplied by W bits of the high position of the shift register as P multiplied by W effective bits in f _qm;

(5b) When the shift register registers When in element, the code word splicing unit intercepts the high (P-T _q-S_c) multiplied by W bits of the shift register and the bit of the bit is expressed by the number of the bits of the shift registerThe S _c XW bits and the N _c XW bits in the shift of the data shift register in the code word splicing unit are sequentially spliced, and the P XW bits obtained by splicing are used as the effective bits of f _qm.