CN118210749A - SerDes-based AXI3 bus inter-chip bridging method and system - Google Patents

Abstract

The invention belongs to the technical field of integrated circuit design, and particularly relates to an AXI3 bus inter-chip bridging method and system based on SerDes, which are used for designing a structure of a master side and a slave side, wherein the master side and the slave side comprise 5 independent channel buffer FIFO, an AXI3 asynchronous bus bridge, a data packet module and a data analysis module; the method comprises the steps of designing a host side packet format, dividing a data packet flowing from a host side to a slave side into two independent bit wide domains, wherein the two independent bit wide domains comprise a write data channel bit wide domain and a write address/read address/host side FIFO state bit wide domain; the slave-side packet format is designed to divide the data packet flowing from the slave-side to the master-side into three independent bit-wide fields, including a read data channel bit-wide field, a write response channel bit-wide field, and a slave-side FIFO status bit-wide field. The invention realizes the chip-to-chip address mapping access with the highest performance as possible by using the high-speed serial link based on SerDes and using the lowest cost as possible, thereby meeting the customized inter-chip communication requirement in the burst transmission scene.

Description

SerDes-based AXI3 bus inter-chip bridging method and system

Technical Field

The invention belongs to the technical field of integrated circuit design, and particularly relates to an AXI3 bus inter-chip bridging method and system based on SerDes.

Background

AXI3 (Advanced eXtensible Interface) is an on-chip bus protocol, which is the most important part of AMBA3.0 proposed by ARM corporation, and is an on-chip bus for high performance, high bandwidth, and low latency.

When high-speed serial bus has become the main way to communicate between chips, it is just as a key SoC component as the key bottom layer component SerDes (serial/parallel conversion module) of high-speed serial bus. The most important example is PCIe bus, where the protocol layer is divided into a transaction layer, a link layer, and a physical layer, the protocol is complex, implementation is difficult, and the corresponding driving development and debugging period is long when applied. For customized inter-chip communication in some application scenarios, PCIe high-speed serial buses with complex protocols cannot be well adapted to requirements, and in particular, for some application scenarios with confidentiality requirements, standard bus IPs designed by other manufacturers are often not desired.

Therefore, the invention designs a SerDes-based inter-chip bridging method of an on-chip AXI3 bus with higher performance under burst transmission, which is low in cost and light in weight and is used for meeting the customized inter-chip communication requirements under partial application scenes.

Disclosure of Invention

The invention aims to solve the problems in the prior art and provides an AXI3 bus inter-chip bridging method and system based on SerDes, which realize inter-chip address mapping access with as high performance as possible by using a high-speed serial link based on SerDes with as low cost as possible, thereby meeting the customized inter-chip communication requirement under a burst transmission scene.

In order to achieve the above purpose, the present invention adopts the following technical scheme:

An AXI3 bus inter-chip bridging method based on SerDes, comprising:

Designing a master side and a slave side structure, wherein the master side and the slave side comprise 5 independent channel buffer FIFO, an AXI3 asynchronous bus bridge, a data packet module and a data analysis module which are designed for 5 channels of an AXI3 bus;

The host side packs the write address, the write data and the read address channel data and transmits the packed data to the slave side through the SerDes bus, and the slave side analyzes the packed data; similarly, the slave side packages the read data and the write response channel data, and transmits the package to the host side through the SerDes bus, and the host side analyzes the package;

The method comprises the steps of designing a packet format for a data packet module at a host side by a domain division method, dividing a data packet flowing to a slave side at the host side into two independent bit wide domains, wherein the two independent bit wide domains comprise a write data channel bit wide domain and a write address/read address/host side FIFO state bit wide domain;

The data packet from the slave side to the host side is divided into three independent bit wide fields including a read data channel bit wide field, a write response channel bit wide field and a slave side FIFO state bit wide field.

According to the SerDes-based AXI3 bus inter-chip bridging method, further, the 5-channel buffer FIFO comprises a write data FIFO, a write address FIFO, a read address FIFO, a write response FIFO and a read data FIFO.

According to the AXI3 bus inter-chip bridging method based on the SerDes, the host side further packages write address, write data and read address channel data and transmits the package to the slave side through the SerDes bus, and the slave side analyzes the package; similarly, the slave side packages the read data and the write response channel data, and transmits the package to the host side through the SerDes bus, and the host side analyzes the package, which specifically includes:

The host side successfully handshakes with the FIFO through an AXI3 asynchronous bus bridge, stores the effective information of an AXI3 bus write address, write data and a read address channel into the respective FIFO, and then the data packet module reads and packages for one time or multiple times and transmits the data packet through a SerDes bus;

The channel information analyzed by the slave side is stored into the corresponding FIFO of the slave side, and then the generation of the corresponding channel time sequence of the AXI3 bus is completed through the handshake between the FIF0 and the AXI3 asynchronous bus bridge;

The slave side successfully handshakes with the FIFO through an AXI3 asynchronous bus bridge, effective information of the AXI3 bus read data and write response channels is stored in the respective FIFO, and then the data packet module reads and packages for one or more times and transmits the data packet through a SerDes bus;

The channel information after the analysis at the host side is stored in the corresponding FIFO at the host side, and then the generation of the corresponding channel time sequence of the AXI3 bus is completed through the handshake between the FIFO and the AXI3 asynchronous bus bridge.

According to the AXI3 bus inter-chip bridging method based on SerDes, further, the parallel bit width of the SerDes is 64bits, and the information bit widths of 5 channels of the AXI3 bus are respectively: 90bits for write address, 153bits for write data, 90bits for read address, 139bits for read data, and 10bits for write response.

According to the AXI3 bus inter-chip bridging method based on SerDes of the present invention, further, the host side packet format is: the data packet bits [50:0] represent write data channel information, and the bits [51] serve as identification bits for identifying whether the write data channel information in the data packet transmitted by the beat is valid or not; bits [63:52] are shared by write address, read address and host side FIFO states, bits [63:62] are used to express whether the packet's corresponding bit wide information is valid and information type, bits [61:52] indicate write address channel, read address channel or host side FIFO state information.

According to the AXI3 bus inter-chip bridging method based on SerDes of the present invention, further, the slave-side packet format is: bits [4:0] of the data packet represent slave-side FIFO state information, bits [51:5] represent read data channel information, bits [52] are used as identification bits to identify whether read data channel information is valid within the data packet transmitted by the beat, bits [62:53] represent write response channel information, bits [63] are used as identification bits to identify whether write response channel information is valid within the data packet transmitted by the beat.

According to the AXI3 bus inter-chip bridging method based on SerDes of the present invention, further, the master/slave side FIFO status is used for the own party to identify whether the own receiving FIFO is almost full, if the own FIFO is almost full and valid, the opposite party data packet module will stop reading valid data from its FIFO and stop the continuous transmission of valid data; at this time, if the FIFO of the counterpart is full due to the stop of the transmission, the FIFO of the counterpart will automatically interrupt the handshake with the AXI3 asynchronous bus bridge, thereby interrupting the data transmission of the corresponding channel of the AXI3 bus of the counterpart.

According to the SerDes-based AXI3 bus inter-chip bridging method, further, transmission of host side FIFO state information has highest priority, and polling transmission is carried out on read address channel information and write address channel information; the slave-side FIFO state monopolizes one bit wide domain, without priority issues.

An AXI3 bus inter-chip bridging system based on SerDes, configured to implement an AXI3 bus inter-chip bridging method based on SerDes as described above, comprising:

The structure design module is used for designing the structures of a master side and a slave side, wherein the master side and the slave side comprise 5 independent channel buffer FIFO, an AXI3 asynchronous bus bridge, a data packet module and a data analysis module which are designed for 5 channels of an AXI3 bus;

the data transmission module is used for packaging write address, write data and read address channel data by the host side, transmitting the package to the slave side through the SerDes bus, and analyzing the package by the slave side; similarly, the slave side packages the read data and the write response channel data, and transmits the package to the host side through the SerDes bus, and the host side analyzes the package;

the host side packet format design module is used for designing a packet format for the host side data packet module through a domain division method, dividing a data packet flowing to the slave side from the host side into two independent bit wide domains, including a write data channel bit wide domain and a write address/read address/host side FIFO state bit wide domain;

The slave side packet format design module is used for designing a packet format for the slave side data packet module through a domain division method, and dividing a data packet flowing from the slave side to the host side into three independent bit wide domains, including a read data channel bit wide domain, a write response channel bit wide domain and a slave side FIFO state bit wide domain.

Compared with the prior art, the invention has the following advantages:

1. The AXI3 bus reads and writes are separated, and has an outbound characteristic, that is, when the own party sends the write data, the AXI3 bus may have a requirement of sending the next write address, or AXI3 may have a requirement of sending the read address, if the packet bit wide domain is not divided, when burst transmission (also called continuous transmission, such as burst transmission of 16 data, or continuous writing/reading of 16 data) is performed, for example, when burst writing of data, the write data may need to be interrupted, and the next "read address" or "write address" may be sent. Or, when there is a request to send a read/write address, the transmission can be performed only after the last burst transmission is completed. Either case can cause increased idle time of the write data channel and the read data channel, resulting in reduced transmission performance. The invention maintains the independence of each channel of the AXI3 through dividing the data packet bit wide domain, ensures the continuity of the AXI3 bus during burst transmission, and adapts to the outbound transmission characteristic of the AXI3 bus.

2. The invention fully utilizes the bandwidth of the SerDes bus, for example, the information bit width of a write data channel is 153bits, if the SerDes bus with the width of 64bits is used for transmission, 20 percent of bandwidth is wasted every 3 periods, the bit wide domain is divided, and although the data information is transmitted in one shot in 3 periods, the 20 percent of bandwidth is essentially utilized for transmitting the read/write address information and the FIFO state information, so that the bandwidth is fully utilized, and the mutual independence of the information transmission in each bit wide domain also simplifies the hardware design.

3. The invention adopts the same packet transmission to the FIFO state, saves sideband signals of interfaces between chips, and is easy to apply and deploy.

4. The invention designs a low-cost and light-weight inter-chip bridging method aiming at an on-chip AXI3 bus by using a high-speed SerDes, and simultaneously considers the burst transmission performance. The method of the invention directly encapsulates/analyzes the AXI3 channel information, directly bridges the bottom AXI3 bus, abandons complex protocols, has no other software overhead except for some software configuration requirements on SerDes, and meets the customized lightweight inter-chip address mapping access requirements. Only a high-speed serial link is used, without any other sideband signal requirements.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a host side frame pattern of an embodiment of the present invention;

FIG. 2 is a slave side frame pattern of an embodiment of the present invention;

FIG. 3 is a block diagram of a packet bit wide division of data sent by a host and received by a slave according to an embodiment of the present invention;

FIG. 4 is a block diagram of the bit wide division of packets sent from a host and received by a host according to an embodiment of the present invention;

FIG. 5 is a write address, read address polling state machine of an embodiment of the invention.

Detailed Description

The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

The present embodiment does not limit the number of SerDes channels, does not limit the parallel bit width, specifically uses SerDes with a serial/parallel ratio of 1:64 as an example, and bridges the AXI3 bus with a 128-bit data bit width and a 64-bit address bit width, but the method can be cited by other SerDes serial/parallel ratios and other AXI3 bus bit width designs, or by designs aimed at AXI4, and is also within the scope of the present invention.

The embodiment provides an AXI3 bus inter-chip bridging method based on SerDes, which comprises the following steps:

Step S101, designing a master side and slave side structure.

AXI3 is a burst transfer-based protocol that defines 5 independent transaction channels, read Address (AR), read data (R), write Address (AW), write data (W), and write response (B), respectively. The address channel carries control class information describing the data attributes being transferred. The write data channel transmits data from the master to the slave, which uses the write response channel to inform the master that the write task is complete in a write transaction. The read data channel transmits data from slave to master.

As shown in fig. 1 and 2, the master side and the slave side contain 5 independent channel buffers FIFO (SYNC FIFO) designed for 5 channels of the AXI3 bus, an AXI3 asynchronous bus bridge (axi_async_bridge), a data packet module, and a data parsing module. The data package module is responsible for the package of channel information, and the data analysis module is responsible for the analysis of channel information. The 5 lane buffer FIFOs include a write data FIFO, a write address FIFO, a read address FIFO, a write response FIFO, and a read data FIFO for buffering information for 5 lanes of AXI 3. The AXI3 asynchronous bus bridge is used for isolating a design module clock domain and an integrated system clock domain, and improves the usability of design.

Step S102, master and slave inter-chip communication.

Specifically, the host side packages write address, write data and read address channel data and transmits the package to the slave side through the SerDes bus, and the slave side analyzes the package to generate AXI3 transaction information. Similarly, the slave side encapsulates the read data and the write response channel data and transmits the encapsulated read data and the write response channel data to the host side through the SerDes bus, and the host side parses the encapsulated read data and the write response channel data, including:

(1) The host side successfully handshakes with the FIFO through the AXI3 asynchronous bus bridge, stores the effective information of the AXI3 bus write address, write data and read address channels into the respective FIFO, and then the data packet module reads and packages for one time or multiple times and transmits the packets through the SerDes bus.

The channel information analyzed by the slave side is stored in the corresponding FIFO of the slave side, and then the generation of the corresponding channel time sequence of the AXI3 bus is completed through the handshake between the FIF0 and the AXI3 asynchronous bus bridge.

(2) The slave side successfully handshakes with the FIFO through the AXI3 asynchronous bus bridge, the effective information of the AXI3 bus read data and write response channels is stored in the respective FIFO, and then the data packet module reads and packages one or more times and transmits the data packet through the SerDes bus.

The channel information after the analysis at the host side is stored in the corresponding FIFO at the host side, and then the generation of the corresponding channel time sequence of the AXI3 bus is completed through the handshake between the FIFO and the AXI3 asynchronous bus bridge.

The AXI3 bus is a valid/ready handshake protocol, each channel of the bus comprises a pair of valid/ready signals, and if handshake is successful, a beat of effective information of the corresponding channel is transmitted. Taking the write data channel as an example (other channels are similar), the write data channel signals are shown in table 1, and each beat has 153bits of information (excluding valid/ready signals), and the 153bits of information are transmitted in packets. In this architecture, the sender completes the clock domain isolation of the system from the design module through the AXI3 asynchronous bus bridge. The data packet module reads and packs for many times and transmits the data packet through the SerDes bus.

TABLE 1AXI3 channel signals and bit widths

Corresponding to the sent packet is packet analysis, the AXI3 write data channel information after the receiver analysis is stored into the corresponding FIFO of the receiver, and then the generation of the corresponding AXI3 write data channel time sequence is completed through the handshake between the FIFO and the AXI3 asynchronous bus bridge. So far, the transmission of the AXI3 bus write data channel information from the sender to the receiver is completed.

In this embodiment, the packet length is 64bits wide in parallel (SerDes may employ other parallel bit widths). After the SerDes link is established stably, a packet of data is transmitted every beat of the parallel clock. Each bit wide field in the packet contains an identification bit for identifying whether corresponding data in each bit wide field of the packet is valid. When the AXI3 write data channel has no valid data to transmit, the data packet module still sends invalid data to keep SerDes transmitting continuously, and the information content is do not care, and the corresponding identification bit is invalid and can be discarded by the opposite side.

The information bit widths of the 5 channels of the AXI3 bus are respectively as follows: 90bits for write address, 153bits for write data, 90bits for read address, 139bits for read data, and 10bits for write response. The parallel bit width of SerDes is 64bits, and the 5 channel information bit widths are not integer multiples of 64, which means that if 64bits of bit width is used for directly packaging channel information, the waste of serial link bandwidth is caused. For example: the information bit width of the write data channel is 153bits, at least 3 parallel clock cycles are required to complete the transmission, and the last cycle wastes 64 x 3-153=39 bits. In addition, in this packet mode, the write address and read address channel information flowing in the same direction as the write data may also interfere with the burst write data transmission.

To prevent interruption in burst transfers or blockage of read/write address transmissions. The embodiment designs a domain division method, carries out domain division on 64bits parallel bit width of SerDes, ensures the independence of 5 channels of AXI3 as much as possible, ensures the continuity of burst transmission, and also ensures the outlining transmission characteristic of an AXI3 bus. Step S103 and step S104 design a master side packet format and a slave side packet format, respectively.

Step S103, designing a packet format for the data packet module at the host side by a domain division method.

As shown in fig. 3, the data packet (each 64bits is packed, because the SerDes parallel bit width is 64 bits) flowing from the host side to the slave side is divided into two independent bit-width fields, including a write data channel bit-width field and a write address/read address/host side FIFO status bit-width field, which are independent of each other and do not affect each other. For example, when write address channel valid data is transmitted, the write data channel bit width field within the same data packet may or may not be valid information.

Each of the data channels for writing is 153bits in bit width, and independently occupies a 52bits wide field of data packet bits [51:0], wherein the bits [51] are used as identification bits for identifying whether the data channel information written in the data packet transmitted by the writing is valid, the remaining 51bits wide field of [50:0] is used for transmitting valid data of the data channel for writing, and the data packet module (153/51=3) takes 3 clock cycles to read and transmit the complete data channel information for writing in one writing.

The common bits [63:52] of the write address, the read address and the host side FIFO state total 12bits of bit wide fields, the bits [63:62] are used for expressing whether the corresponding bit wide field information of the packet is valid or not and the information type (the write address, the read address, the FIFO state or the invalid information), and the corresponding codes of the 2bits of identification bits are shown in a table 2; bits [61:52] represent write address channel, read address channel, or host side FIFO status information.

Table 2 header encoding for write address, read address and FIFO status

Load(s)	[63:62]
		IDLE	2‘b00
Write address channel (AW)	2‘b01
		Read address channel (AR)	2‘b10
MasterFIFO state	2‘b11

The host-side FIFO status is used to identify to the partner whether the partner receiving FIFO is almost full, and if the partner receives information that the partner FIFO is almost full, the partner data packet module will stop reading valid data from its FIFO, stopping the continuous transmission of valid data. At this time, if the FIFO of the other party is full due to the stop of the transmission, the FIFO of the other party will automatically interrupt the handshake with the AXI3 asynchronous bus bridge, thereby interrupting the data transmission of the corresponding channel of the AXI3 bus of the other party, and ensuring the integrity of the data. After the own FIFO is almost full of invalid information is transferred to the other party, the other party resumes data transmission.

As shown in Table 1, the read/write address channel information bit width is 90bits. As shown in fig. 3, the packet bits [61:52] are 10bits in total, (90/10=9) the packet module uses 9 parallel clock cycles to read and transmit a complete burst of valid write address or read address channel information, although the number of cycles is more, the read/write address information is sparse relative to the continuous dense burst read/write data, and when the burst data is transmitted, the read/write address channel information has enough time to transmit (write data and read/write address bit are independent of each other in wide range, and do not affect each other), so that the transmission of the read/write data channel information is not affected by the lack of read/write address.

The FIFO status type of data packet needs to identify whether the host side write response FIFO, read data FIFO is almost full (as shown in fig. 1, B represents write response FIFO, R represents read data FIFO). The packet bits [61:52] are sufficient to express FIFO status information.

Because the read/write address information and FIFO status information share one bit wide area, the transmission of information is exclusive. At this time, the transmission of FIFO status data has the highest priority, and if the host side receives FIFO almost full, the host side will interrupt the possible subsequent transmission of read/write address after completing the transmission of the current read/write address channel information, and the FIFO status information of the host side will be preferentially transmitted, and the transmission of read/write address information will be resumed after completing the transmission.

Similarly, the read address and the write address share a bit wide area, so that in order to prevent the read address and the write address from blocking each other, polling transmission needs to be performed on the read address and the write address, and a polling state machine is shown in fig. 5. Regardless of whether read address information or write address information needs to be transmitted, the state machine does not stay in a certain state continuously.

Step S104, the packet format is designed for the slave side data packet module by a domain division method.

The slave side works in the same way as master.

As shown in fig. 4, the data packet flowing from the slave side to the host side is divided into three independent bit-width domains, including a read data channel bit-width domain, a write response channel bit-width domain and a slave side FIFO status bit-width domain, which are still independent of each other and do not affect each other.

Specifically, packet bits [4:0] represent slave-side FIFO state information, bits [51:5] represent read data lane information, bits [52] are identification bits identifying whether read data lane information is valid within the data packet transmitted by the beat, bits [62:53] represent write response lane information, and bits [63] are identification bits identifying whether write response lane information is valid within the data packet transmitted by the beat.

The effect of the slave-side FIFO state is the same as that of the master-side FIFO state of step S103, and reference is made to the above description. In addition, the slave-side FIFO state monopolizes one bit wide area, and there is no priority problem.

Taking the read data channel transmission as an example, as shown in table 1, the read data channel information bit width is 139bits. The read data channel information occupies 48bits of the data packet bits [52:5], wherein the bits [52] are used to express whether the packet read data channel information is valid. Bits [51:5] are 47bits wide, the data packet module takes 3 parallel clock cycles to read the read data channel information after one time of transmission, and only 47 x 3-139 = 2bits wide is wasted.

The write response occupies 11 bits total of [63:53], wherein the bit [63] is a valid information identification bit. The data package module can completely transmit 10bits of write response information by using one parallel clock period. The remaining bit widths are divided into a slave-side FIFO state that is used to express whether the slave-side receive FIFO is nearly full.

Correspondingly, the present embodiment also provides an AXI3 bus inter-chip bridging system based on SerDes, which includes:

The structure design module is used for designing the structure of a master side and a slave side, wherein the master side and the slave side comprise 5 independent channel buffer FIFO, an AXI3 asynchronous bus bridge, a data packet module and a data analysis module which are designed for 5 channels of an AXI3 bus.

The data transmission module is used for packaging write address, write data and read address channel data by the host side, transmitting the package to the slave side through the SerDes bus, and analyzing the package by the slave side; similarly, the slave side wraps the read data and the write response channel data, and transmits the data to the host side through the SerDes bus, and the host side parses the wrapping.

The host side packet format design module is used for designing a packet format for the host side data packet module through a domain division method, and dividing the data packet flowing to the slave side from the host side into two independent bit wide domains, including a write data channel bit wide domain and a write address/read address/host side FIFO state bit wide domain.

The slave side packet format design module is used for designing a packet format for the slave side data packet module through a domain division method, and dividing a data packet flowing from the slave side to the host side into three independent bit wide domains, including a read data channel bit wide domain, a write response channel bit wide domain and a slave side FIFO state bit wide domain.

The relative steps, numerical expressions and numerical values of the components and steps set forth in these embodiments do not limit the scope of the present invention unless it is specifically stated otherwise.

In the present specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the system disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.

The elements and method steps of the examples described in connection with the embodiments disclosed herein may be embodied in electronic hardware, computer software, or a combination thereof, and the elements and steps of the examples have been generally described in terms of functionality in the foregoing description to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Those of ordinary skill in the art may implement the described functionality using different methods for each particular application, but such implementation is not considered to be beyond the scope of the present invention.

Those of ordinary skill in the art will appreciate that all or a portion of the steps in the above methods may be performed by a program that instructs associated hardware, and that the program may be stored on a computer readable storage medium, such as: read-only memory, magnetic or optical disk, etc. Alternatively, all or part of the steps of the above embodiments may be implemented using one or more integrated circuits, and accordingly, each module/unit in the above embodiments may be implemented in hardware or may be implemented in a software functional module. The present invention is not limited to any specific form of combination of hardware and software.

Finally, it should be noted that: the above examples are only specific embodiments of the present invention, and are not intended to limit the scope of the present invention, but it should be understood by those skilled in the art that the present invention is not limited thereto, and that the present invention is described in detail with reference to the foregoing examples: any person skilled in the art may modify or easily conceive of the technical solution described in the foregoing embodiments, or perform equivalent substitution of some of the technical features, while remaining within the technical scope of the present disclosure; such modifications, changes or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present invention, and are intended to be included in the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims (10)

1. An AXI3 bus inter-chip bridging method based on SerDes, comprising:

Designing a master side and a slave side structure, wherein the master side and the slave side comprise 5 independent channel buffer FIFO, an AXI3 asynchronous bus bridge, a data packet module and a data analysis module which are designed for 5 channels of an AXI3 bus;

The host side packs the write address, the write data and the read address channel data and transmits the packed data to the slave side through the SerDes bus, and the slave side analyzes the packed data; similarly, the slave side packages the read data and the write response channel data, and transmits the package to the host side through the SerDes bus, and the host side analyzes the package;

The method comprises the steps of designing a packet format for a data packet module at a host side by a domain division method, dividing a data packet flowing to a slave side at the host side into two independent bit wide domains, wherein the two independent bit wide domains comprise a write data channel bit wide domain and a write address/read address/host side FIFO state bit wide domain;

The data packet from the slave side to the host side is divided into three independent bit wide fields including a read data channel bit wide field, a write response channel bit wide field and a slave side FIFO state bit wide field.

2. The SerDes-based AXI3 bus inter-slice bridging method of claim 1, wherein said 5 lane buffer FIFOs include a write data FIFO, a write address FIFO, a read address FIFO, a write response FIFO, and a read data FIFO.

3. The method of claim 2, wherein the host side encapsulates write address, write data, read address channel data and transmits the encapsulated packets to the slave side via the SerDes bus, and the slave side parses the encapsulated packets; similarly, the slave side packages the read data and the write response channel data, and transmits the package to the host side through the SerDes bus, and the host side analyzes the package, which specifically includes:

The host side successfully handshakes with the FIFO through an AXI3 asynchronous bus bridge, stores the effective information of an AXI3 bus write address, write data and a read address channel into the respective FIFO, and then the data packet module reads and packages for one time or multiple times and transmits the data packet through a SerDes bus;

The channel information analyzed by the slave side is stored into the corresponding FIFO of the slave side, and then the generation of the corresponding channel time sequence of the AXI3 bus is completed through the handshake between the FIF0 and the AXI3 asynchronous bus bridge;

The slave side successfully handshakes with the FIFO through an AXI3 asynchronous bus bridge, effective information of the AXI3 bus read data and write response channels is stored in the respective FIFO, and then the data packet module reads and packages for one or more times and transmits the data packet through a SerDes bus;

The channel information after the analysis at the host side is stored in the corresponding FIFO at the host side, and then the generation of the corresponding channel time sequence of the AXI3 bus is completed through the handshake between the FIFO and the AXI3 asynchronous bus bridge.

4. The AXI3 bus inter-chip bridging method based on SerDes according to claim 1, wherein the SerDes parallel bit width is 64bits, and the information bit widths of 5 channels of the AXI3 bus are respectively: 90bits for write address, 153bits for write data, 90bits for read address, 139bits for read data, and 10bits for write response.

5. The SerDes-based AXI3 bus inter-slice bridging method of claim 4, wherein said host-side packet format is: the data packet bits [50:0] represent write data channel information, and the bits [51] serve as identification bits for identifying whether the write data channel information in the data packet transmitted by the beat is valid or not; bits [63:52] are shared by write address, read address and host side FIFO states, bits [63:62] are used to express whether the packet's corresponding bit wide information is valid and information type, bits [61:52] indicate write address channel, read address channel or host side FIFO state information.

6. The SerDes-based AXI3 bus inter-chip bridging method of claim 5, wherein said slave-side packet format is: bits [4:0] of the data packet represent slave-side FIFO state information, bits [51:5] represent read data channel information, bits [52] are used as identification bits to identify whether read data channel information is valid within the data packet transmitted by the beat, bits [62:53] represent write response channel information, bits [63] are used as identification bits to identify whether write response channel information is valid within the data packet transmitted by the beat.

7. The method of claim 6, wherein the master/slave side FIFO status is used to identify to the other party whether the receiving FIFO is almost full, and if the other party receives the information that the receiving FIFO is almost full, the data packet module of the other party stops reading the valid data from the FIFO and stops the continuous transmission of the valid data; at this time, if the FIFO of the counterpart is full due to the stop of the transmission, the FIFO of the counterpart will automatically interrupt the handshake with the AXI3 asynchronous bus bridge, thereby interrupting the data transmission of the corresponding channel of the AXI3 bus of the counterpart.

8. The SerDes-based AXI3 bus inter-slice bridging method of claim 6, wherein transmission of host-side FIFO status information has highest priority, polling transmission of read address channel information and write address channel information; the slave-side FIFO state monopolizes one bit wide domain, without priority issues.

9. A SerDes-based AXI3 bus inter-chip bridging system, configured to implement a SerDes-based AXI3 bus inter-chip bridging method according to any one of claims 1 to 8, comprising:

The structure design module is used for designing the structures of a master side and a slave side, wherein the master side and the slave side comprise 5 independent channel buffer FIFO, an AXI3 asynchronous bus bridge, a data packet module and a data analysis module which are designed for 5 channels of an AXI3 bus;

the data transmission module is used for packaging write address, write data and read address channel data by the host side, transmitting the package to the slave side through the SerDes bus, and analyzing the package by the slave side; similarly, the slave side packages the read data and the write response channel data, and transmits the package to the host side through the SerDes bus, and the host side analyzes the package;

the host side packet format design module is used for designing a packet format for the host side data packet module through a domain division method, dividing a data packet flowing to the slave side from the host side into two independent bit wide domains, including a write data channel bit wide domain and a write address/read address/host side FIFO state bit wide domain;

The slave side packet format design module is used for designing a packet format for the slave side data packet module through a domain division method, and dividing a data packet flowing from the slave side to the host side into three independent bit wide domains, including a read data channel bit wide domain, a write response channel bit wide domain and a slave side FIFO state bit wide domain.

10. An electronic device, comprising:

At least one processor, and a memory coupled to the at least one processor;

Wherein the memory stores a computer program executable by the at least one processor to implement the method of any one of claims 1-8.