CN118199390A - Three-level inverter protection circuit - Google Patents
Three-level inverter protection circuit Download PDFInfo
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- CN118199390A CN118199390A CN202410246716.3A CN202410246716A CN118199390A CN 118199390 A CN118199390 A CN 118199390A CN 202410246716 A CN202410246716 A CN 202410246716A CN 118199390 A CN118199390 A CN 118199390A
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Abstract
The application relates to a three-level inverter protection circuit, which belongs to the technical field of electronic equipment and comprises a first current limiting module, a second current limiting module, a third current limiting resistor, a first capacitor, a second capacitor, an inner tube control module and an outer tube control module; the third current limiting resistor, the first current limiting module and the first capacitor are connected in series, the free end of the first capacitor is connected with the ground, the connection common end of the first capacitor and the first current limiting module is connected with the inner tube control module, and the output end of the inner tube control module is connected with the inner tube; the common connection end of the third current limiting resistor and the first current limiting module is connected with the second current limiting module, the free end of the second current limiting module is connected with the second capacitor, the free end of the second capacitor is grounded, the common connection end of the second capacitor and the second current limiting module is connected with the outer tube control module, and the output end of the outer tube control module is connected with the outer tube. The application reduces the risk of the problem of the turn-on and turn-off sequence of the switching tube in the three-level inverter.
Description
Technical Field
The application relates to the technical field of electronic equipment, in particular to a three-level inverter protection circuit.
Background
The three-level topological structure has the advantages of large output capacity, high output voltage, small current harmonic content and the like, so that the three-level structure is widely applied to the field of variable frequency speed regulation of high-voltage high-power alternating current motors. In order to prevent the direct connection of the bridge arms of the inverter, dead zones are added in trigger signals complementary to the same bridge arm to ensure that the switching tube on the same bridge arm can be switched on only after the switching tube complementary to the switching tube on the same bridge arm is reliably switched off. If the sequence of the on or off of the switching tube is wrong, the overvoltage damage of the semiconductor power switching device can be caused.
At present, the controller and the programmable logic device are adopted to complete the time sequence control of the switching tube so as to achieve the aim of protecting the three-level inverter, for example, a field programmable gate array (field programmable GATE ARRAY, FPGA) with an ARM processor, the ARM processor completes the realization of an algorithm, and the FPGA completes the construction of a time sequence. The time sequence control core is used in the mode, and the risk of occurrence of problems of the time sequence control core is high, for example, the problems of abnormal peripheral circuits, abnormal crystal oscillator, abnormal power supply and the like of the time sequence control core can cause unavailability of the time sequence control core, so that the on and off sequence of the switching tube is influenced, and the risk of occurrence of problems of the on and off sequence of the switching tube is increased in the mode.
Disclosure of Invention
In order to reduce the risk of problems in the turn-on and turn-off sequence of switching tubes in a three-level inverter, the application provides a three-level inverter protection circuit.
In a first aspect of the present application, a three-level inverter protection circuit is provided. The protection circuit comprises a first current limiting module, a second current limiting module, a third current limiting resistor, a first capacitor, a second capacitor, an inner tube control module and an outer tube control module;
The third current limiting resistor, the first current limiting module and the first capacitor are connected in series, the free end of the first capacitor is grounded and connected, the connection common end of the first capacitor and the first current limiting module is connected with the first input end of the inner tube control module, the second input end of the inner tube control module inputs an inner tube modulation signal of the three-level inverter, and the output end of the inner tube control module is connected with an inner tube of the three-level inverter;
The third current limiting resistor and the connection public end of the first current limiting module are connected with the second current limiting module, the free end of the second current limiting module is connected with the second capacitor, the free end of the second capacitor is grounded, the connection public end of the second capacitor and the second current limiting module is connected with the first input end of the outer tube control module, the second input end of the outer tube control module inputs an outer tube modulation signal of the three-level inverter, and the output end of the outer tube control module is connected with the outer tube of the three-level inverter.
According to the technical scheme, the first current limiting module and the second current limiting module are respectively connected with the third current limiting resistor to form two links for respectively controlling the outer tube and the inner tube of the three-level inverter, and due to the difference of charge and discharge speeds of the first current limiting module and the second current limiting module, the time of high-level signals or low-level signals transmitted to the inner tube control module and the outer tube control module is different, a certain time delay is generated, the time sequence control of the on-off of the inner tube and the outer tube is realized, and the risk that the on-off sequence of the switching tube in the three-level inverter is problematic is reduced by using the combination of simple electronic components.
In one possible implementation manner, the first current limiting module includes a diode and a first current limiting resistor, the diode and the first current limiting resistor are connected in parallel, the third current limiting resistor is connected with a negative common terminal, the first capacitor is connected with a positive common terminal, the negative common terminal represents a connection common terminal of a negative electrode of the diode and the first current limiting resistor, and the positive common terminal represents a connection common terminal of a positive electrode of the diode and the first current limiting resistor.
In one possible implementation manner, the second current limiting module includes a diode and a second current limiting resistor, where the diode and the second current limiting resistor are connected in parallel, the third current limiting resistor is connected to a positive common terminal, the second capacitor is connected to a negative common terminal, the positive common terminal represents a connection common terminal of the positive electrode of the diode and the second current limiting resistor, and the negative common terminal represents a connection common terminal of the negative electrode of the diode and the second current limiting resistor.
In one possible implementation, the diode is a schottky diode
In one possible implementation, the inner tube control module and the outer tube control module are both and gates.
In one possible implementation, the diode has an on-state voltage drop of 0.2V-0.5V.
In one possible implementation manner, the protection circuit further includes a modulation signal generating module, and the modulation signal generating module is connected to the second input ends of the inner tube control module and the outer tube control module, respectively, and is configured to output the inner tube modulation signal and the outer tube modulation signal.
In one possible implementation manner, the protection circuit further includes a main control module, where the main control module is connected to the free end of the third current limiting resistor, and the main control module is configured to output a high level signal or a low level signal.
According to the technical scheme, the main control module inputs a high-level signal or a low-level signal to the third current limiting resistor, so that the switching tube of the three-level inverter is controlled to be turned on or off.
In one possible implementation, the first current limiting resistor is a variable resistor or a resistor matrix.
In one possible implementation manner, the first capacitor includes a single-pole multi-throw switch and a capacitor matrix, the capacitor matrix includes a plurality of capacitors, the capacitance value of each capacitor in the capacitor matrix is different, the stationary end of the single-pole multi-throw switch is connected with the positive common end, the movable end of the single-pole multi-throw switch is connected with the capacitors in the capacitor matrix, and the free ends of the capacitors in the capacitor matrix are grounded.
In summary, the present application includes at least one of the following beneficial technical effects:
The first current limiting module and the second current limiting module are respectively connected with the third current limiting resistor to form two links for respectively controlling the outer tube and the inner tube of the three-level inverter, and due to the difference of charge and discharge speeds of the first current limiting module and the second current limiting module, the time of high-level signals or low-level signals transmitted to the inner tube control module and the outer tube control module is different, a certain time delay is generated, the time sequence control of the on-off of the inner tube and the outer tube is realized, and the risk that the on-off sequence of the switching tube in the three-level inverter is problematic is reduced by using the combination of simple electronic components.
Drawings
Fig. 1 is a schematic circuit diagram of a three-level inverter protection circuit according to an embodiment of the present application.
Fig. 2 is a schematic diagram of the protection principle provided by the embodiment of the application.
Fig. 3 is a timing diagram of a three-level inverter protection circuit according to an embodiment of the present application.
Fig. 4 is a circuit schematic diagram of a three-level inverter protection circuit according to an embodiment of the present application.
In the figure, 1, a first current limiting module; 2. a second current limiting module; 3. a third current limiting resistor; 4. a first capacitor; 5. a second capacitor; 6. an inner tube control module; 7. an outer tube control module; 8. a modulation signal generation module; 9. and a main control module.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In addition, the term "and/or" herein is merely an association relationship describing an association object, and means that three relationships may exist, for example, a and/or B may mean: a exists alone, A and B exist together, and B exists alone. In this context, unless otherwise specified, the term "/" generally indicates that the associated object is an "or" relationship.
For a general two-level inverter, when an insulated gate bipolar transistor (insulate gate bipolar transistor, IGBT) driving board detects a short circuit or under-voltage fault, pulses are blocked immediately, meanwhile, fault signals are sent to a controller, and after the controller receives the fault signals, other IGBTs are blocked. For three levels, the sequence of switching on and off of the switching tube is required, and if the sequence is wrong, the device is likely to be damaged. The three-level inverter requires that the outer tube is closed before the inner tube is closed at the closing time, and the inner tube is opened at the opening time under the condition of high direct current voltage, or the inner tube is opened before the outer tube is opened, otherwise, the inner tube is extremely easy to be damaged by overvoltage due to bearing the voltage of the whole bus.
The application provides a three-level inverter protection circuit, which completes time sequence control through a simple resistor-capacitor and a logic control device, saves design cost, test cost and operation and maintenance cost of a time sequence control core compared with a mode of using the time sequence control core, reduces the risk of occurrence of problems of the turn-on and turn-off sequence of a switching tube in the three-level inverter, and improves the reliability of the protection circuit.
Embodiments of the application are described in further detail below with reference to the drawings.
Referring to fig. 1, the three-level inverter protection circuit comprises a first current limiting module 1, a second current limiting module 2, a third current limiting resistor 3, a first capacitor 4, a second capacitor 5, an inner tube control module 6 and an outer tube control module 7; the third current limiting resistor 3, the first current limiting module 1 and the first capacitor 4 are connected in series, the free end of the first capacitor 4 is grounded, the connection common end of the first capacitor 4 and the first current limiting module 1 is connected with the first input end of the inner tube control module 6, the second input end of the inner tube control module 6 inputs an inner tube modulation signal of the three-level inverter, and the output end of the inner tube control module 6 is connected with an inner tube of the three-level inverter; the connection common terminal of the third current limiting resistor 3 and the first current limiting module 1 is connected with the second current limiting module 2, the free terminal of the second current limiting module 2 is connected with the second capacitor 5, the free terminal of the second capacitor 5 is grounded, the connection common terminal of the second capacitor 5 and the second current limiting module 2 is connected with the first input terminal of the outer tube control module 7, the second input terminal of the outer tube control module 7 inputs the outer tube modulation signal of the three-level inverter, and the output terminal of the outer tube control module 7 is connected with the outer tube of the three-level inverter.
Further, the first current limiting module 1 includes a diode and a first current limiting resistor, the diode and the first current limiting resistor are connected in parallel, the third current limiting resistor 3 is connected to a negative common terminal, the first capacitor 4 is connected to a positive common terminal, the negative common terminal represents a connection common terminal between a negative electrode of the diode and the first current limiting resistor, and the positive common terminal represents a connection common terminal between a positive electrode of the diode and the first current limiting resistor.
Further, the second current limiting module 2 includes a diode and a second current limiting resistor, the diode and the second current limiting resistor are connected in parallel, the third current limiting resistor 3 is connected to a positive common terminal, the second capacitor 5 is connected to a negative common terminal, the positive common terminal represents a connection common terminal between the positive electrode of the diode and the second current limiting resistor, and the negative common terminal represents a connection common terminal between the negative electrode of the diode and the second current limiting resistor.
In the embodiment provided in the present application, the diode is a schottky diode, and in other embodiments, other diodes that can achieve the effect may be used, which is not limited herein. In the embodiment provided by the present application, the inner pipe control module 6 and the outer pipe control module 7 are both and gates. The on-state voltage drop of the diode is 0.2V-0.5V.
The three-level inverter protection circuit further comprises a modulation signal generation module 8, wherein the modulation signal generation module 8 is respectively connected with the second input ends of the inner tube control module 6 and the outer tube control module 7, and is used for outputting the inner tube modulation signal and the outer tube modulation signal. In the embodiment provided in the present application, the modulation signal generating module 8 is a pulse modulator, and in other embodiments, other devices capable of generating the inner tube modulation signal or the outer tube modulation signal may be used, which is not limited herein.
The three-level inverter protection circuit further comprises a main control module 9, wherein the main control module 9 is connected with the free end of the third current limiting resistor 3, and the main control module 9 is used for outputting a high-level signal or a low-level signal.
Before understanding the protection process of the three-level inverter protection circuit, a basic principle needs to be known first, referring to fig. 2, in which a power supply, a resistor and a capacitor are connected in series, where Vt is a voltage value on the capacitor at any time t, E is a signal high-level voltage, R is a resistance value of a charging resistor, C is a capacitance value of the charging capacitor, and the voltage on the capacitor is expressed as follows by a formula: vt=e [1-exp (-t/RC) ], and thus t= RCLn [ E/(E-Vt) ]. In the process of discharging the capacitor through the resistor, the voltage on the capacitor at any time t is as follows: vt=e exp (-t/RC) then t= RCLn [ E/Vt ], where exp () represents the base-E exponent and Ln () is the base-E logarithm.
Referring to fig. 1, in a specific example, R1 is a first current limiting resistor, R2 is a second current limiting resistor, R3 is a third current limiting resistor 3, C1 is a first capacitor 4, C2 is a second capacitor 5, D1 and D2 are schottky diodes, an on-state voltage drop is between 0.2V and 0.5V, the on-state voltage drop of the diodes is related to the current limiting resistor connected in parallel, and the larger the resistance of the current limiting resistor, the larger the on-state voltage drop, in this example, the on-state voltage drop of the diodes is about 0.2V. The Signal1 flowing out of the first current limiting module 1 flows into the and gate U1 of the inner pipe control module 6, and the Signal2 flowing out of the second current limiting module 2 flows into the and gate U2 of the outer pipe control module 7. In fig. 1, ctrEN is a control signal output by the main control module 9, exterPWM is an outer tube modulation signal sent by the modulation signal generation module 8 for modulating an outer tube in the three-level inverter, interPWM is an inner tube modulation signal sent by the modulation signal generation module 8 for modulating an inner tube in the three-level inverter. ExterDri is an output signal of the outer tube control module 7, and is also an outer tube IGBT driving signal which is received by the outer tube in the three-level inverter and controls the outer tube to be turned on or off. InterDri is an output signal of the inner tube control module 6, and is also an inner tube IGBT driving signal received by an inner tube in the three-level inverter for controlling the on or off of the inner tube.
In the example provided by the present application, the level high transition threshold is 2V, the level low transition threshold is 0.8V, and the control signal is active high.
When CtrEN outputs a high-level signal, the high-level signal passes through the third current-limiting resistor R3 and the diode D1 to rapidly charge the first capacitor C1, and since the threshold voltage of the logic chip and gate is far higher than D1 voltage drop, i.e. 2V is higher than 0.2V, the voltage drop of the diode D1 is negligible, and at this time, t1=r3×c1×ln [ E/(E-Vt) ]. The high level signal also flows through the third current limiting resistor R3 and the second current limiting resistor R2 to charge the second capacitor C2 slowly, and at this time, the time t2= (r2+r3) ×c2×ln [ E/(E-Vt) ], and the difference between T2 and T1, i.e., T2-T1, is the opening delay of the inner tube and the outer tube.
When CtrEN outputs a low level signal, vt is set as the voltage drop of the schottky diode, and at this time, the second capacitor C2 is rapidly discharged through the diode D2 and the third current limiting resistor R3, and the time t3=r3×c2×ln [ E/Vt ]. Meanwhile, the first capacitor C1 is discharged slowly through the first current limiting resistor R1 and the third current limiting resistor R3, and the time t4= (r1+r3) ×c1×ln [ E/Vt ], and then the difference between T3 and T4, i.e. T4-T3, is the turn-off delay of the inner tube and the outer tube.
In the actual use process of the three-level inverter protection circuit, suitable electrical devices can be used according to the actual delay requirement, for example, the delay is set to 2s, then the value of the T2-T1 is 2, wherein E and Vt are all available data, the relational expression of R1, R2, R3, C1 and C2 can be obtained, and as long as the value of R1, R2, R3, C1 and C2 meets the relational expression, the effect of closing the outer tube first and closing the inner tube at the transition time of the control signal CtrEN from the high-level signal to the low-level signal can be achieved, and the effect of opening the inner tube first and then opening the outer tube at the transition time of the control signal CtrEN from the low-level signal to the high-level signal can be achieved.
Referring to fig. 3, fig. 3 includes a timing diagram of signals, in which dead time is not shown, and the dead time is a protection period set for preventing upper and lower tubes of the H-standard or half-H-standard from being simultaneously turned on due to a switching speed problem when a pulse width modulation (pulse width modulation, PWM) signal is outputted.
In a specific example, when the control Signal is a high level Signal, C1 charges quickly, C2 charges slowly, the voltages of C1 and C2 reach the high level threshold sequentially, signal1 becomes a high level Signal first, interDri also outputs a high level Signal when InterPWM is also a high level Signal, so as to control the inner tube to be turned on, since C2 charges slowly, signal2 becomes a high level Signal after Signal1, exterDri also outputs a high level Signal when ExterPWM is also a high level Signal, so as to control the outer tube to be turned on, and since the charging speeds of C1 and C2 are different, the time for reaching the high level threshold is different, so that the inner tube and the outer tube are sequentially turned on.
When the control signal is changed into a low level signal, C1 is slowly discharged and C2 is rapidly discharged, so that C2 reaches a low level threshold value first, a low level signal is output, no matter ExterPWM is high level or low level, at the moment ExterDri outputs the low level signal, and the outer tube is controlled to be closed. When C1 reaches the low level threshold, interDri outputs a low level signal to control the inner tube to close, regardless of whether InterPWM is high or low. Because the discharging speeds of C1 and C2 are different, the time for reaching the low level threshold is different, and the inner tube and the outer tube are turned off successively.
Referring to fig. 4, the first current limiting resistor is a variable resistor or a resistor matrix, and similarly, the second current limiting resistor is a variable resistor or a resistor matrix. From the foregoing, it can be seen that when the control delay of the inner tube and the outer tube in the three-level inverter changes, the magnitude relation of R1, R2, R3, C1 and C2 changes, and in order to adapt to the delay changes in different environments, the first current limiting resistor and the second current limiting resistor are set as variable resistors or resistor matrices, and a user can adjust the resistance values of the first current limiting resistor and the second current limiting resistor according to specific use requirements.
Similarly, when the resistances of the first current limiting resistor and the second current limiting resistor are changed, the capacitance values of the first capacitor 4 and the second capacitor 5 need to be adjusted accordingly. Referring to fig. 4, the first capacitor 4 includes a single-pole multi-throw switch S1 and a capacitor matrix, the capacitor matrix includes a plurality of capacitors, for example, C11, C12, … … C1n, the capacitors in the capacitor matrix have different capacitance values, a stationary end of the single-pole multi-throw switch S1 is connected to the positive common terminal, a movable end of the single-pole multi-throw switch S1 is connected to the capacitors in the capacitor matrix, and a free end of the capacitors in the capacitor matrix is grounded. The second capacitor 5 includes a single-pole multi-throw switch S2 and a capacitor matrix, the capacitor matrix includes a plurality of capacitors, for example, C21, C22, … … C2n, the capacitors in the capacitor matrix have different capacitance values, the stationary end of the single-pole multi-throw switch S2 is connected to the negative common end, the movable end of the single-pole multi-throw switch S2 is connected to the capacitors in the capacitor matrix, and the free ends of the capacitors in the capacitor matrix are grounded. In other embodiments, the adjustment of the first current limiting resistor, the second current limiting resistor, the first capacitor 4 and the second capacitor 5 may be implemented in other manners, which are not limited herein.
The three-level inverter protection circuit provided by the application has the advantages of low cost, reliable protection, strong expansibility, no need of programming and capability of performing more complex wave-by-wave current limiting function by using simple control and electrical devices without an additional controller.
The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the application is not limited to the specific combinations of the features described above, but also covers other embodiments which may be formed by any combination of the features described above or their equivalents without departing from the spirit of the application. Such as the above-mentioned features and the technical features having similar functions (but not limited to) applied for in the present application are replaced with each other.
Claims (10)
1. The three-level inverter protection circuit is characterized by comprising a first current limiting module (1), a second current limiting module (2), a third current limiting resistor (3), a first capacitor (4), a second capacitor (5), an inner tube control module (6) and an outer tube control module (7);
The third current limiting resistor (3), the first current limiting module (1) and the first capacitor (4) are connected in series, the free end of the first capacitor (4) is grounded, the connection common end of the first capacitor (4) and the first current limiting module (1) is connected with the first input end of the inner tube control module (6), the second input end of the inner tube control module (6) inputs an inner tube modulation signal of the three-level inverter, and the output end of the inner tube control module (6) is connected with the inner tube of the three-level inverter;
The third current limiting resistor (3) and the connection public end of the first current limiting module (1) are connected with the second current limiting module (2), the free end of the second current limiting module (2) is connected with the second capacitor (5), the free end of the second capacitor (5) is grounded, the connection public end of the second capacitor (5) and the second current limiting module (2) is connected with the first input end of the outer tube control module (7), the second input end of the outer tube control module (7) inputs an outer tube modulation signal of the three-level inverter, and the output end of the outer tube control module (7) is connected with the outer tube of the three-level inverter.
2. The three-level inverter protection circuit according to claim 1, wherein the first current limiting module (1) comprises a diode and a first current limiting resistor, the diode and the first current limiting resistor are connected in parallel, the third current limiting resistor (3) is connected with a negative common terminal, the first capacitor (4) is connected with a positive common terminal, the negative common terminal represents a connection common terminal of a negative electrode of the diode and the first current limiting resistor, and the positive common terminal represents a connection common terminal of a positive electrode of the diode and the first current limiting resistor.
3. The three-level inverter protection circuit according to claim 1, wherein the second current limiting module (2) comprises a diode and a second current limiting resistor, the diode and the second current limiting resistor are connected in parallel, the third current limiting resistor (3) is connected with a positive common terminal, the second capacitor (5) is connected with a negative common terminal, the positive common terminal represents a connection common terminal of the positive electrode of the diode and the second current limiting resistor, and the negative common terminal represents a connection common terminal of the negative electrode of the diode and the second current limiting resistor.
4. A three-level inverter protection circuit according to claim 2 or 3, wherein the diode is a schottky diode.
5. The three-level inverter protection circuit according to claim 1, characterized in that the inner tube control module (6) and the outer tube control module (7) are both and gates.
6. A three-level inverter protection circuit according to claim 2 or 3, wherein the diode has an on-state voltage drop of 0.2V-0.5V.
7. The three-level inverter protection circuit according to claim 1, further comprising a modulation signal generation module (8), the modulation signal generation module (8) being connected to the second inputs of the inner tube control module (6) and the outer tube control module (7), respectively, for outputting the inner tube modulation signal and the outer tube modulation signal.
8. The three-level inverter protection circuit according to claim 1, further comprising a main control module (9), wherein the main control module (9) is connected to a free end of the third current limiting resistor (3), and the main control module (9) is configured to output a high level signal or a low level signal.
9. The three-level inverter protection circuit of claim 2, wherein the first current limiting resistor is a variable resistor or a resistor matrix.
10. The three-level inverter protection circuit according to claim 2, wherein the first capacitor (4) comprises a single-pole multi-throw switch and a capacitor matrix, the capacitor matrix comprises a plurality of capacitors, the capacitance value of each capacitor in the capacitor matrix is different, the stationary end of the single-pole multi-throw switch is connected with the positive common end, the movable end of the single-pole multi-throw switch is connected with the capacitor in the capacitor matrix, and the free end of the capacitor in the capacitor matrix is grounded.
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410246716.3A CN118199390A (en) | 2024-03-05 | 2024-03-05 | Three-level inverter protection circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202410246716.3A CN118199390A (en) | 2024-03-05 | 2024-03-05 | Three-level inverter protection circuit |
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| CN118199390A true CN118199390A (en) | 2024-06-14 |
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| CN202410246716.3A Pending CN118199390A (en) | 2024-03-05 | 2024-03-05 | Three-level inverter protection circuit |
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