CN118198099A

CN118198099A - Semiconductor structure and forming method thereof

Info

Publication number: CN118198099A
Application number: CN202211591345.XA
Authority: CN
Inventors: 邹振东; 赖云凯; 廖志成; 李家豪
Original assignee: Vanguard International Semiconductor Corp
Current assignee: Vanguard International Semiconductor Corp
Priority date: 2022-12-12
Filing date: 2022-12-12
Publication date: 2024-06-14

Abstract

The application provides a semiconductor structure and a forming method thereof, wherein the semiconductor structure comprises: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate and having a first conductivity type, wherein a protruding structure is formed on an upper portion of the epitaxial layer; a well disposed in the epitaxial layer, the well having a second conductivity type; the insulation structure is arranged on the side wall of the protruding structure; an upper electrode layer surrounding the protruding structure, the upper electrode layer being electrically connected to the epitaxial layer and the well; and a lower electrode layer disposed under the substrate and opposite to the epitaxial layer. The semiconductor structure of the present application has a breakdown voltage comparable to that of a conventional junction barrier schottky or trench junction barrier schottky diode, and has various electrical improvements.

Description

Semiconductor structure and forming method thereof

Technical Field

The present invention relates generally to semiconductor structures and methods of forming the same, and more particularly to semiconductor structures including insulating structures and methods of forming the same.

Background

In recent years, the semiconductor industry has seen significant progress in the development of power devices (power devices). Various power devices such as High Voltage Metal Oxide Semiconductor (HVMOS) transistors, insulated gate bipolar transistors (insulated gate bipolar Transistor, IGBT), junction FIELD EFFECT Transistors (JFET), and schottky barrier diodes (Schottky barrier diode, SBD) have been developed. These components are commonly used in a variety of applications such as power amplification, power control in power systems for appliances such as household appliances, communications equipment, and automotive generators.

Among the above devices, the schottky barrier diode has a high-speed switch (high-switching) and can withstand high voltages of several hundred volts. In order to improve the performance of schottky barrier diodes, such as increasing breakdown voltage, reducing leakage current, etc., a device combining a schottky diode and a PN diode, which is called a junction barrier schottky (Junction Barrier Schottky, JBS) diode, has been developed. However, while junction barrier schottky diodes can reduce surface electric fields and reduce leakage currents due to the PN junctions, they have a larger on-resistance and a slower switching speed than schottky barrier diodes.

Thus, trenches may also be provided on both sides of the schottky junction to form a trench junction barrier schottky (Trench Junction Barrier Schottky, TJBS) diode. The trench junction barrier schottky diode includes mesa (mesa) shaped semiconductor layers between trench structures to reduce the surface electric field at the schottky junction and reduce leakage current. However, as mesa-shaped semiconductor layers are formed, the on-resistance of the entire device increases due to the increased thickness of the semiconductor layers.

In summary, while the prior art schottky barrier diodes generally meet their intended use, they have not met the needs in all respects. For example, how to manufacture a schottky barrier diode with a low on-resistance while reducing the generation of leakage current is still the subject of the current research in the industry. Therefore, the development of the power device requires continuous updating and adjustment to solve various problems faced in the operation of the power device.

Disclosure of Invention

In order to solve the above problems, the present application provides the following.

A semiconductor structure, comprising: a substrate having a first conductivity type; an epitaxial layer disposed on the substrate and having a first conductivity type, wherein a protruding structure is formed on an upper portion of the epitaxial layer; a well disposed in the epitaxial layer, the well having a second conductivity type; the insulation structure is arranged on the side wall of the protruding structure; an upper electrode layer surrounding the protruding structure, the upper electrode layer being electrically connected to the epitaxial layer and the well; and a lower electrode layer disposed under the substrate and opposite to the epitaxial layer.

A method of forming a semiconductor structure, comprising: depositing an epitaxial layer having a first conductivity type on a substrate having the first conductivity type; forming a well having a second conductivity type in the epitaxial layer; performing a patterning process to form a protruding structure on the upper portion of the epitaxial layer; forming an insulating structure on the sidewalls of the protruding structure; forming an upper electrode layer surrounding the protruding structure, and electrically connected to the epitaxial layer and the well; and forming a lower electrode layer opposite to the epitaxial layer on the substrate.

Thus, the semiconductor structure of the present application has a breakdown voltage (breakdown voltage) comparable to that of a conventional junction barrier schottky or trench junction barrier schottky diode, and various electrical improvements.

Drawings

In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art. In the drawings:

Fig. 1 is a cross-sectional view of a semiconductor structure, according to some embodiments of the application.

Fig. 2 is a cross-sectional view of a conventional trench junction barrier schottky diode.

Fig. 3A-3G are cross-sectional views illustrating various stages of a method of forming a semiconductor structure, in accordance with some embodiments of the present application.

Symbol description:

10 semiconductor structure

100 Substrate

102,102': Epitaxial layer

102E field effect accumulation layer

102P protruding structure

102T trench structure

104 Well

106 Insulating structure

107 Spacer

108 Upper electrode layer

110 Lower electrode layer

Detailed Description

The following disclosure provides many different embodiments, or examples, to demonstrate different components of an embodiment of the present application. Specific examples of components and arrangements of components in the present specification are disclosed below to simplify the present disclosure. Of course, these specific examples are not intended to limit the application. For example, if the following disclosure describes forming a first element on or over a second element, this includes embodiments in which the formed first and second elements are in direct contact, and also includes embodiments in which additional elements may be formed between the first and second elements, the first and second elements are not in direct contact. In addition, various examples in the description of the application may use repeated reference characters and/or words. These repeated symbols or words are for simplicity and clarity and are not intended to limit the relationship between the various embodiments and/or configurations described.

Moreover, for convenience in describing the relationship of one element or component to another element(s) or component(s) in the drawings, spatially relative terms such as "under …," "under," "lower," "above," "upper," and the like may be used. Spatially relative terms may be intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. When the device is turned to a different orientation (e.g., rotated 90 degrees or other orientations), the spatially relative descriptors used herein interpreted in accordance with the turned orientation.

The terms "about", "approximately" and "approximately" herein generally mean within 20%, preferably within 10%, and more preferably within 5%, or within 3%, or within 2%, or within 1%, or within 0.5% of a given value or range. It should be noted that the numbers provided in the specification are about numbers, i.e., without a specific recitation of "about", "approximately", the meaning of "about", "approximately" may still be implied.

Embodiments of the invention are described below that may provide additional steps before, during, and/or after the various stages described in these embodiments. Some of the stages may be replaced or eliminated in different embodiments. Additional components may be added to the semiconductor device structure. Some of the described components may be replaced or omitted in different embodiments. Although some of the embodiments discussed are performed in a specific order of steps, these steps may be performed in another logical order.

The term "substantially" as used herein means that a given amount of value may vary based on the particular technology node to which the target semiconductor device is associated. In some embodiments, the term "substantial" may mean that a given amount of value is within, for example, ±5% of a target (or desired) value, based on a particular technology node.

A semiconductor structure and a method of forming the same are provided, which embed a metal-insulator-semiconductor (MIS) structure in a Trench Junction Barrier Schottky (TJBS) diode to form a field effect accumulation layer (FIELD EFFECT accumulation layer) of carriers when conducting. Further, the upper electrode layer of the semiconductor structure is electrically connected with the well between the protruding structures of the semiconductor epitaxial layer (e.g., the bottom of the trench), and an ohmic contact is formed at the interface between the upper electrode layer and the well. Thus, the semiconductor structure of the present application has a breakdown voltage (breakdown voltage) comparable to that of a conventional junction barrier schottky or trench junction barrier schottky diode, and various electrical improvements. For example, the semiconductor structure of the present application can have a smaller leakage current than a conventional junction barrier schottky diode and a lower on-resistance than a conventional trench junction barrier schottky diode. In addition, the semiconductor structure of the application has better reverse recovery property, can reduce power loss and heat productivity of the diode in the process from the on state to the complete off state of the diode, and is beneficial to the application under high frequency.

Fig. 1 is a cross-sectional view of a semiconductor structure, according to some embodiments of the application. Semiconductor structure 10 may include a substrate 100, an epitaxial layer 102, a well 104, an insulating structure 106, an upper electrode layer 108, and a lower electrode layer 110. The substrate 100 may have a first conductivity type (e.g., n-type). The epitaxial layer 102 may be disposed on the substrate 100 and have the first conductivity type described above, and have a protruding structure 102P on an upper portion of the epitaxial layer 102. The well 104 may be disposed in the epitaxial layer 102, and the well 104 has a second conductivity type (e.g., p-type) opposite the first conductivity type. The insulating structure 106 may be disposed on a sidewall of the protruding structure 102P. The upper electrode layer 108 may surround the protruding structure 102P, and the upper electrode layer 108 is electrically connected to the epitaxial layer 102 and the well 104. The lower electrode layer 110 may be disposed under the substrate 100 and opposite to the epitaxial layer 102.

In some embodiments, the base 100 is a bulk semiconductor substrate, such as a semiconductor wafer. In some embodiments, the substrate 100 is formed of silicon, germanium, other suitable semiconductor materials, or a combination of the foregoing. For example, in one particular embodiment, the substrate 100 comprises silicon. In some embodiments, the substrate 100 may include a compound semiconductor, such as silicon carbide, gallium nitride, gallium oxide, gallium arsenide, other suitable semiconductor materials, or combinations of the foregoing. In some embodiments, the substrate 100 may comprise an alloy semiconductor, such as silicon germanium, silicon germanium carbide, other suitable materials, or a combination of the foregoing. In some embodiments, the substrate 100 may be composed of multiple layers of materials, such as multiple layers of materials including silicon/silicon germanium, silicon/silicon carbide.

In some embodiments of the present application, for example, the substrate 100 is a wafer doped with a dopant of a first conductivity type, and the first conductivity type is n-type. In some other embodiments, the first conductivity type may also be p-type. In the case where the first conductivity type is n-type, the dopant having the first conductivity type may be, for example, nitrogen, phosphorus, arsenic, antimony, bismuth, silicon. In some embodiments, the doping concentration of the substrate 100 is between about 1E19atoms/cm3 to about 1E21atoms/cm 3.

Epitaxial layer 102 may comprise the same or similar materials as substrate 100, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium carbide, other suitable materials, or combinations of the foregoing. In some embodiments, the substrate 100 and the epitaxial layer 102 have the same conductivity type (e.g., n-type), and the substrate 100 and the epitaxial layer 102 may include the same dopant. In some embodiments, the dopant concentration of the dopant in the epitaxial layer 102 is less than the dopant concentration in the substrate 100. In some embodiments, the doping concentration of epitaxial layer 102 is between about 1E13atoms/cm3 to about 1E18atoms/cm 3. In some embodiments of the present application, epitaxial layer 102 comprises silicon carbide, for example. The epitaxial layer 102 is formed of silicon carbide, and the epitaxial layer 102 can be doped with a dopant that is suitable for the band range of silicon carbide and has a low activation energy. In addition, the epitaxial layer 102 formed of silicon carbide can provide a higher breakdown voltage, lower leakage current, and lower on-resistance.

With continued reference to fig. 1, the well 104 may comprise the same or similar material as the substrate 100, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium carbide, other suitable materials, or combinations of the foregoing. In some embodiments, the substrate 100 has a different conductivity type than the epitaxial layer 102. In some embodiments of the present application, well 104 is doped with a second conductivity type, for example, and the second conductivity type is p-type. In case the second conductivity type is p-type, the dopant having the second conductivity type may be, for example, boron, aluminum, gallium, indium, thallium, magnesium. In some embodiments, the doping concentration of the well 104 is in a range of between about 1E16atoms/cm3 to about 1E18atoms/cm 3.

It should be noted that the protruding structure 102P is defined in the present application as the portion of the epitaxial layer 102 protruding above the top surface of the well 104. In some embodiments, as shown in fig. 1, the insulating structure 106 disposed on the sidewalls of the protruding structures 102P extends to overlap a portion of the top surface of the well 104. As shown in fig. 1, the insulating structure 106 may expose a top surface of the protruding structure 102P. In some embodiments, the insulating structure 106 does not vertically overlap the top surface of the protruding structure 102P, and the top ends of the insulating structure 106 are substantially flush with the top surface of the protruding structure 102P.

As shown in fig. 1, the insulating structure 106 may be located between the protruding structure 102P and the upper electrode layer 108. In some embodiments, the epitaxial layer 102, the insulating structure 106, and the upper electrode layer 108 may form a metal-insulator-semiconductor (MIS) structure near the sidewalls of the protruding structure 102P. In this way, the field effect accumulation layer 102E of carriers may be formed when the semiconductor structure 10 is turned on to reduce the on-resistance of the semiconductor structure 10, as will be discussed later.

The material of the insulating structure 106 may include silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, hafnium aluminum dioxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, other suitable high-k dielectric materials, or a combination of the foregoing. In some embodiments, the insulating structure 106 comprises an oxide having an element in common with the epitaxial layer 102. For example, in one particular embodiment, the epitaxial layer 102 comprises silicon or silicon carbide and the insulating structure 106 comprises silicon oxide.

With continued reference to fig. 1, in some embodiments, there is a trench structure surrounding the protruding structure 102P in an upper portion of the epitaxial layer 102, and the upper electrode layer 108 fills in the trench structure. In some embodiments, as shown in fig. 1, a portion of the insulating structure 106 extends between the well 104 and the upper electrode layer 108.

By disposing the upper electrode layer 108 on the well 104 and around the protruding structure 102P, ohmic contact may be formed between the upper electrode layer 108 and the well 104, and schottky contact may be formed between the upper electrode layer 108 and the top surface of the protruding structure 102P. In this way, the schottky contact can be used to reduce the voltage drop and have a faster response speed while reducing the leakage of the semiconductor structure 10 by using the well 104. In addition, although not shown in fig. 1, in some embodiments, the semiconductor structure 10 further includes a silicide layer at an interface between the well 104 and the upper electrode layer 108 to improve ohmic contact properties between the upper electrode layer 108 and the well 104.

The upper electrode layer 108 may Be or include, for example, platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), gold (Au), iron (Fe), nickel (Ni), (Be), chromium (Cr), cobalt (Co), antimony (Sb), iridium (Ir), molybdenum (Mo), osmium (Os), thorium (Th), vanadium (V), some other metal or metal nitride, or a combination of the foregoing.

The lower electrode layer 110 may be or include the same or similar material as the upper electrode layer 108. For example, the lower electrode layer 110 may Be or include, for example, platinum (Pt), titanium (Ti), titanium nitride (TiN), tantalum (Ta), tantalum nitride (TaN), tungsten (W), tungsten nitride (WN), gold (Au), iron (Fe), nickel (Ni), (Be), chromium (Cr), cobalt (Co), antimony (Sb), iridium (Ir), molybdenum (Mo), osmium (Os), thorium (Th), vanadium (V), some other metal or metal nitride, or a combination of the foregoing.

The operation of the semiconductor structure 10 will be discussed below in terms of the case where the doping type of the substrate 100 and the epitaxial layer 102 is n-type and the doping type of the well 104 is p-type. However, in practice, those skilled in the art may also adjust the doping types of the substrate 100, the epitaxial layer 102, and the well 104 according to the design requirements, which is not limited by the present application. The upper electrode 108 disposed around the protrusion structure 102P and the lower electrode 110 disposed under the substrate 100 may be used as an anode and a cathode of the trench junction barrier schottky device, respectively, when forward bias is applied to the semiconductor structure 10. Electrons generated in the epitaxial layer 102 due to the MIS structure may form the field effect accumulation layer 102E when the semiconductor structure 10 is turned on in a forward operation to reduce the on-resistance of the semiconductor structure 10. In addition, the MIS structure can reduce leakage current through the generation of the depletion region at the time of reverse operation.

Referring to fig. 2, a conventional Trench Junction Barrier Schottky (TJBS) diode 20. The difference from the semiconductor structure 10 of the present application is that the well 104 of the conventional trench junction barrier schottky diode 20 extends further to the sidewall of the protruding structure 102P without an insulating structure between the protruding structure 102P and the upper electrode layer 110. In operation of the conventional trench junction barrier schottky diode 20, the surface electric field of the epitaxial layer 102 adjacent to the upper electrode layer 108 is reduced due to the protruding structure 102P of the epitaxial layer 102, which can reduce leakage current compared to the conventional junction barrier schottky diode. However, the presence of the protruding structure 102P also results in an increase in the overall resistance of the current in the epitaxial layer 102 (particularly the resistance from the portion of the protruding structure 102P) such that the conventional trench junction barrier schottky diode 20 has a higher starting resistance.

In contrast, the semiconductor structure 10 of the present application has a MIS structure formed of the epitaxial layer 102, the insulating structure 106, and the upper electrode layer 108. The field effect accumulation layer 102E formed when the semiconductor structure 10 is turned on can reduce the on-resistance of the semiconductor structure 10 while reducing the leakage current. In addition, the semiconductor structure 10 of the present application has a breakdown voltage comparable to that of conventional junction barrier schottky diodes and trench junction barrier schottky diodes. Thus, the semiconductor structure 10 of the present application is capable of providing lower leakage current and lower on-resistance under typical voltage conditions (e.g., 600V-1200V bias between the upper electrode layer 108 and the lower electrode layer 110).

Furthermore, compared to the conventional Trench Junction Barrier Schottky (TJBS) diode 20 of fig. 2, the semiconductor structure 10 of the present application has a MIS structure, which can reduce the contact area between the metal and the well 104 and the surface area of the well 104 itself, so that the reverse recovery of the semiconductor structure 10 can be faster. Therefore, the semiconductor structure 10 of the present application can have better reverse recovery properties, such as a shorter recovery time (recovery time), when turned off. In this way, the semiconductor structure 10 can reduce the power loss and the heat generation of the diode in the process from the on state to the complete off state, which is beneficial to the application under high frequency.

Fig. 3A-3G are cross-sectional views illustrating various stages of a method of forming a semiconductor structure 10, in accordance with some embodiments of the present application. Although fig. 3A to 3G are described with reference to a method, it should be understood that the structures shown in fig. 3A to 3G are not limited to the above-described method, but may be independent of the above-described method.

As shown in fig. 3A, an epitaxial layer 102' having a first conductivity type (e.g., n-type) may be deposited on a substrate 100 having the first conductivity type. Epitaxial layer 102' may comprise the same or similar material as substrate 100, such as silicon, germanium, silicon carbide, gallium nitride, gallium oxide, gallium arsenide, silicon germanium carbide, other suitable materials, or combinations of the foregoing. In some embodiments of the present application, epitaxial layer 102' comprises silicon carbide, for example. The formation of the epitaxial layer 102 'from silicon carbide enables doping of the epitaxial layer 102' with dopants that are suitable for the band range of silicon carbide and have a low activation energy.

The epitaxial layer 102' may be deposited by a process such as chemical vapor deposition (chemical vapor deposition, CVD), physical vapor deposition (physical vapor deposition, PVD), atomic layer deposition (atomic layer deposition, ALD), pulsed laser deposition (pulsed laser deposition, PLD), some other deposition process, or a combination of the foregoing.

In some embodiments, the epitaxial layer 102' is in-situ doped to have a first conductivity type (e.g., n-type). In some other embodiments, the epitaxial layer 102 'is doped with a dopant having the first conductivity type after the epitaxial layer 102' is deposited. For example, the epitaxial layer 102' may be doped by ion implantation, thermal diffusion, other suitable processes, or a combination of the foregoing. The doped epitaxial layer 102 'may have the same first conductivity type as the substrate 100, and the dopant concentration in the epitaxial layer 102' is less than the dopant concentration in the substrate 100.

Next, referring to fig. 3B to 3D, a well 104 having a second conductive type (e.g., P-type) may be formed in the epitaxial layer 102', and a patterning process may be performed to form a protruding structure 102P at an upper portion of the epitaxial layer 102. In some embodiments, the well 104 is buried in the epitaxial layer 102 'prior to the patterning process of the epitaxial layer 102' and is exposed from an upper portion of the epitaxial layer 102 after the patterning process, as discussed below with reference to fig. 3B-3D.

Referring to fig. 3B, the well 104 having the second conductive type may be formed to have portions spaced apart from each other at an upper portion of the epitaxial layer 102'. The formation of the well 104 may include forming a patterned masking layer (not shown) (e.g., positive/negative photoresist, hard mask, etc.) over the epitaxial layer 102'. A masking layer (not shown) may be formed on the epitaxial layer 102' (e.g., by a spin coating process), exposed to a pattern (e.g., by a photolithographic process, such as photolithography, extreme ultraviolet lithography, etc.), and developed to form a patterned masking layer. Thereafter, after the patterned masking layer is in place, the unmasked portions of the upper portion of epitaxial layer 102' may be doped to form wells 104 by ion implantation, thermal diffusion, other suitable processes, or a combination of the foregoing. The patterned masking layer may then be stripped. The doped well 104 may have a second conductivity type (e.g., p-type) opposite the first conductivity type of the epitaxial layer 102'.

Referring next to fig. 3C, epitaxial material may be further deposited to grow epitaxial layer 102 'such that epitaxial layer 102' covers well 104. In further growth of the epitaxial layer 102', materials and processes similar to those of the epitaxial layer 102' in the portion below the top surface of the well 104 may be used, which are not described further herein.

Referring next to fig. 3D, a patterning process may be performed on the epitaxial layer 102' to form the epitaxial layer 102 having the protruding structures 102P, and the trench structures 102T may be formed around the protruding structures 102P. As shown in fig. 3D, the well 104 may be exposed at the bottom of the trench structure 102T after the patterning process.

The process for forming the protrusion structures 102P and the trench structures 102T includes forming a patterned masking layer (not shown) (e.g., positive/negative photoresist, hard mask, etc.) over the epitaxial layer 102' prior to patterning. A masking layer (not shown) may be formed on the epitaxial layer 102' (e.g., by a spin coating process), exposed to a pattern (e.g., by a photolithographic process, such as photolithography, extreme ultraviolet lithography, etc.), and developed to form a patterned masking layer. After that, after the patterned masking layer is in place, an etching process is performed on the epitaxial layer 102' according to the patterned masking layer.

The etching process removes the unmasked portions of the epitaxial layer 102' to form the protruding structures 102P and the trench structures 102T surrounding the protruding structures 102P. In some embodiments, the etching process may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching (reactive ion etching, RIE) process, other suitable etching processes, or a combination of the foregoing.

The patterned masking layer may then be stripped. In some embodiments, the etching process described above is performed until a portion of the well 104 is also removed. As shown in fig. 3D, in some embodiments, the top of the well 104 near the protruding structure 102P is higher than the top surface away from the protruding structure 102P. In this way, it is ensured that there is substantially no remaining epitaxial layer 102' on the top surface of the well 104.

Although the well 104 is formed prior to the patterning process of the epitaxial layer 102' in the embodiment of fig. 3B-3D, the present application is not limited thereto. In other embodiments, the well 104 is formed in the epitaxial layer 102 after the patterning process of the epitaxial layer 102'. In such an embodiment, the epitaxial layer 102 is exposed at the bottom of the trench structure 102T after the patterning process described above. Next, the portion of the epitaxial layer 102 exposed at the bottom of the trench structure 102T may be doped with a dopant having the second conductivity type to form the well 104.

Doping with dopants of the second conductivity type may include forming masking layers (not shown) (e.g., positive/negative photoresist, hard mask, etc.) on the top and sides of the protruding structures 102P. A masking layer (not shown) may be blanket formed (e.g., by a spin coating process) over the epitaxial layer 102 having the protruding structures 102P, exposed to a pattern (e.g., by a photolithographic process such as photolithography, extreme ultraviolet lithography, etc.), and developed to form a patterned masking layer covering only the top and sides of the protruding structures 102P. This patterned masking layer exposes epitaxial layer 102 at the bottom of trench structure 102T.

Thereafter, after the patterned masking layer is in place, the epitaxial layer 102 at the bottom of the trench structure 102T and the unmasked portion may be doped by ion implantation, thermal diffusion, other suitable process, or a combination thereof to form the well 104. The patterned masking layer may then be stripped. The doped well 104 may have a second conductivity type opposite the first conductivity type of the epitaxial layer 102'.

After the protruding structure 102P is formed, as shown in fig. 3E and 3F, an insulating structure 106 may be formed on the sidewalls of the protruding structure 102P. The formation of the insulating structure 106 may include conformally depositing an insulating layer 106 'over the protruding structures 102P and the well 104, and then the insulating layer 106' may be removed from portions on the top surfaces of the protruding structures 102P and the well 104.

The material of the insulating layer 106' may include silicon oxide, hafnium oxide, zirconium oxide, aluminum oxide, hafnium aluminum dioxide alloy, hafnium silicon oxide, hafnium silicon oxynitride, hafnium tantalum oxide, hafnium titanium oxide, hafnium zirconium oxide, other suitable high-k dielectric materials, or a combination of the foregoing. In some embodiments, insulating layer 106' comprises an oxide having an element in common with epitaxial layer 102. For example, in one particular embodiment, the epitaxial layer 102 comprises silicon or silicon carbide and the insulating layer 106' comprises silicon oxide. The insulating layer 106' may be deposited by, for example, CVD, PVD, ALD, a spin-on process, some other deposition process, or a combination of the foregoing.

As shown in fig. 3E, the removing of the portion of the insulating layer 106' may include forming a spacer 107 on the insulating layer 106' to prevent the insulating layer 106' covering the portion of the sidewall of the protruding structure 102P from being removed in a subsequent etching process. In some embodiments, the spacers 107 may partially overlap the well 104 in a vertical direction to form an insulating structure 106 that extends to a top surface of the well 104. The spacers 107 may comprise a material that is etch selective to the insulating layer 106', such as an oxide (e.g., siO 2), a nitride (e.g., siN), an oxynitride (e.g., siON), some other dielectric material, or a combination of the foregoing.

The formation of the spacers 107 may include, for example, a deposition process and a patterning process. The material for the spacers 107 may be deposited by, for example, CVD, PVD, ALD, a spin-on process, some other deposition process, or a combination of the foregoing. The deposited material for the spacers 107 will cover the protruding structures 102P and the wells 104, and then a patterning process may be performed to form the spacers 107 such that the formed spacers 107 expose the insulating layer 106' at the bottom of the trench structures 102T and above the protruding structures 102P.

After forming the spacers 107, referring to fig. 3E and 3F, an etching process may be performed to remove portions of the insulating layer 106' exposed from the spacers 107, and then the spacers 107 may be removed to form the insulating structure 106. In some embodiments, the etching process of the insulating layer 106' and the spacers 107 may be or include, for example, a wet etching process, a dry etching process, a reactive ion etching process, other suitable etching processes, or a combination of the foregoing.

Although fig. 3E and 3F illustrate a method of forming the insulating structure 106 by using the spacers 107, the method of forming the insulating structure 106 of the present application is not limited thereto. In some embodiments, the insulating structure 106 is an oxide that oxidizes the epitaxial layer 102 by heating to form on the sidewalls of the protruding structures 102P. More specifically, by performing a heat treatment, the material of the surface of the epitaxial layer 102 may be oxidized to form the insulating structure 106 comprising an oxide. Next, portions of the insulating structure 106 may be removed to expose a top surface of the protruding structure 102P, so that the epitaxial layer 102 may be electrically connected with a subsequently formed upper electrode layer 108. In some particular embodiments, epitaxial layer 102 comprises a silicon-containing material (e.g., silicon germanium, silicon carbide, silicon nitride, silicon oxynitride, silicon oxycarbide, etc.), and the insulating structure comprises silicon oxide.

After forming the insulating structure 106, referring to fig. 3G, an upper electrode layer 108 surrounding the protruding structure 102P may be formed, and the upper electrode layer 108 may be electrically connected to the epitaxial layer 102 and the well 104. In some embodiments where the well 104 comprises silicon, a heat treatment may be performed to form a silicide between the upper electrode layer 108 and the well 104 to improve ohmic contact properties between the upper electrode layer 108 and the well 104. The upper electrode layer 108 may be deposited by, for example ALD, PVD, CVD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing.

Next, the semiconductor structure on which the upper electrode layer 108 has been formed may be flipped over, and a lower electrode layer 110 opposite to the epitaxial layer 102 is formed on the substrate 100. The lower electrode layer 110 may be deposited by, for example ALD, PVD, CVD, sputtering, electrochemical plating, electroless plating, some other deposition process, or a combination of the foregoing.

In summary, the present application provides a semiconductor structure and a method for forming the same, which embeds a metal-insulator-semiconductor (MIS) structure in a trench junction barrier schottky diode to form a field effect accumulation layer of carriers when conducting. Further, the upper electrode layer of the semiconductor structure is electrically connected with the well between the protruding structures of the semiconductor epitaxial layer (e.g., the bottom of the trench), and an ohmic contact is formed at the interface between the upper electrode layer and the well. Thus, the semiconductor structure of the present application has a breakdown voltage comparable to that of a conventional junction barrier schottky or trench junction barrier schottky diode, and has various electrical improvements. For example, the semiconductor structure of the present application can have a smaller leakage current than a conventional junction barrier schottky diode and a lower on-resistance than a conventional trench junction barrier schottky diode. In addition, the semiconductor structure of the application has better reverse recovery property, can reduce power loss and heat productivity of the diode in the process from the on state to the complete off state of the diode, and is beneficial to the application under high frequency.

The foregoing outlines features of several embodiments so that those skilled in the art may better understand the aspects of the embodiments of the present invention. Those skilled in the art will appreciate that other processes and structures can be readily utilized as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments presented herein. It will also be understood by those skilled in the art that such equivalent processes and structures do not depart from the spirit and scope of the present invention, and that various changes, substitutions and alterations can be made herein without departing from the spirit and scope of the invention.

Claims

1. A semiconductor structure, the semiconductor structure comprising:

A substrate having a first conductivity type;

an epitaxial layer disposed on the substrate and having the first conductivity type, wherein a protruding structure is disposed on an upper portion of the epitaxial layer;

A well disposed in the epitaxial layer, the well having a second conductivity type;

an insulating structure arranged on the side wall of the protruding structure;

an upper electrode layer surrounding the protruding structure, and electrically connected to the epitaxial layer and the well; and

And the lower electrode layer is arranged below the substrate and opposite to the epitaxial layer.

2. The semiconductor structure of claim 1, wherein the insulating structure is located between the protruding structure and the upper electrode layer.

3. The semiconductor structure of claim 1, wherein a trench structure surrounding the protruding structure is provided in the upper portion of the epitaxial layer, and the upper electrode layer is filled in the trench structure.

4. The semiconductor structure of claim 1, wherein a portion of the insulating structure extends between the well and the upper electrode layer.

5. The semiconductor structure of claim 1, wherein the epitaxial layer comprises silicon carbide.

6. The semiconductor structure of claim 1, wherein the substrate comprises silicon or silicon carbide.

7. The semiconductor structure of claim 1, wherein a dopant concentration in the epitaxial layer is less than a dopant concentration in the substrate.

8. The semiconductor structure of claim 1, wherein the insulating structure comprises an oxide having an element in common with the epitaxial layer.

9. The semiconductor structure of claim 1, further comprising a silicide layer at an interface between said well and said upper electrode layer.

10. A method of forming a semiconductor structure, the method comprising:

Depositing an epitaxial layer having a first conductivity type on a substrate having the first conductivity type;

Forming a well of a second conductivity type in the epitaxial layer;

Performing a patterning process to form a protruding structure on an upper portion of the epitaxial layer;

forming an insulating structure on the sidewalls of the protruding structure;

Forming an upper electrode layer surrounding the protruding structure, and electrically connected to the epitaxial layer and the well; and

A lower electrode layer is formed on the substrate opposite the epitaxial layer.

11. The method of forming a semiconductor structure of claim 10, wherein the well is buried in the epitaxial layer prior to the patterning process and is exposed from the upper portion of the epitaxial layer after the patterning process.

12. The method of forming a semiconductor structure of claim 10, wherein the well is formed in the epitaxial layer after the patterning process.

13. The method of forming a semiconductor structure of claim 10, wherein the forming of the insulating structure comprises:

conformally depositing an insulating layer over the protruding structures and the well; and

The insulating layer is removed for portions on top surfaces of the protruding structures and the wells.

14. The method of forming a semiconductor structure of claim 13, wherein the removing the insulating layer of portions on top surfaces of the protruding structures and the wells comprises:

forming a spacer on the insulating layer;

Performing an etching process to remove the insulating layer exposed from the spacers; and

The spacers are removed.

15. The method of forming a semiconductor structure of claim 10, wherein the insulating structure is an oxide formed on a sidewall of the protruding structure by heating the epitaxial layer.