CN118197926A

CN118197926A - Package and method for manufacturing the same

Info

Publication number: CN118197926A
Application number: CN202410198814.4A
Authority: CN
Inventors: 余振华; 吴俊毅
Original assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Current assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date: 2023-02-22
Filing date: 2024-02-22
Publication date: 2024-06-14

Abstract

A method of manufacturing a package includes forming a first redistribution structure on a first substrate; forming a waveguide structure on a second substrate, wherein the waveguide structure comprises a waveguide; bonding the waveguide structure to the first redistribution structure using a dielectric-to-dielectric bond; removing the second substrate; forming a second redistribution structure over the waveguide structure; and connecting the photonic package to the second redistribution structure, wherein the photonic package is optically coupled to the waveguide. Embodiments of the present invention also provide a package.

Description

Package and method for manufacturing the same

Technical Field

Embodiments of the present invention relate to packages and methods of manufacturing the same.

Background

Electrical signals and processing are one technique for signal transmission and processing. High bandwidth networks and high performance computing have become increasingly popular and are widely used in advanced packaging applications, particularly in servers, a.i. (artificial intelligence), supercomputers, and related products. However, many existing solutions using copper interconnects are unable to meet low insertion loss requirements, low delay requirements, and low power consumption requirements while providing increased bandwidth and data rates.

Disclosure of Invention

Some embodiments of the invention provide a method of manufacturing a package, the method comprising: forming a first redistribution structure on a first substrate; forming a waveguide structure on a second substrate, wherein the waveguide structure comprises a plurality of waveguides; bonding the waveguide structure to the first redistribution structure using a dielectric-to-dielectric bond; removing the second substrate; forming a second redistribution structure over the waveguide structure; and connecting the photonic package to the second redistribution structure, wherein the photonic package is optically coupled to the plurality of waveguides.

Further embodiments of the present invention provide a method of manufacturing a package, the method comprising: forming a first interposer, comprising: forming a plurality of first waveguides over a first substrate; forming a first dielectric layer over the plurality of first waveguides; and annealing the plurality of first waveguides; and bonding the first dielectric layer to the first redistribution structure; and connecting the die to the first interposer, wherein the die is electrically coupled to the first redistribution structure and optically coupled to the plurality of first waveguides.

Still further embodiments of the present invention provide a package comprising: an interconnect structure, wherein the interconnect structure comprises: a first metallization layer on the substrate; a second metallization layer over the first metallization layer, wherein the second metallization layer is electrically connected to the first metallization layer; a waveguide layer sandwiched between the first metallization layer and the second metallization layer, the waveguide layer comprising at least one waveguide; and a bonding layer sandwiched between the first metallization layer and the waveguide layer; and a first device over the second metallization layer, wherein the first device comprises a photonic component optically coupled to the waveguide layer, wherein the first device is electrically connected to the second metallization layer.

Still further embodiments of the present invention provide photonic semiconductor devices and methods of making the same.

Drawings

Aspects of the disclosure may be best understood from the following detailed description when read in connection with the accompanying drawings. It is noted that the various components are not drawn to scale according to standard practice in the industry. In fact, the dimensions of the various features may be arbitrarily increased or reduced for clarity of discussion.

Fig. 1A, 1B, and 1C illustrate cross-sectional views of intermediate steps in forming a photonic package, in accordance with some embodiments.

Fig. 2A, 2B, and 2C illustrate cross-sectional views of intermediate steps in forming a wiring structure, according to some embodiments.

Fig. 3A and 3B illustrate cross-sectional views of intermediate steps in forming an optical routing structure, according to some embodiments.

Fig. 4A, 4B, and 4C illustrate cross-sectional views of intermediate steps in forming an interconnect structure, in accordance with some embodiments.

Fig. 5A, 5B, 5C, and 5D illustrate cross-sectional views of intermediate steps in forming a photonic structure, in accordance with some embodiments.

Fig. 6 illustrates a cross-sectional view of a photonic system in accordance with some embodiments.

Fig. 7A, 7B, and 7C illustrate cross-sectional views of intermediate steps in forming an interconnect structure and a photonic system, in accordance with some embodiments.

Fig. 8A, 8B, 8C, 8D, 8E, and 8F illustrate cross-sectional views of intermediate steps in forming an interconnect structure, according to some embodiments.

Fig. 9A, 9B, 9C, 9D, 9E, and 9F illustrate cross-sectional views of intermediate steps in forming an interconnect structure, according to some embodiments.

Detailed Description

The following disclosure provides many different embodiments, or examples, of the different components used to implement the application. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component over or on a second component may include embodiments in which the first component and the second component are formed in direct contact, and may also include embodiments in which additional components may be formed between the first component and the second component, such that the first component and the second component may not be in direct contact. Further, the present disclosure may repeat reference numerals and/or characters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.

Moreover, spatially relative terms such as "below …," "below …," "lower," "above …," "upper," and the like may be used herein for ease of description to describe one element or component's relationship to another element(s) or component(s) as illustrated. Spatially relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation depicted in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spatially relative descriptors used herein interpreted accordingly.

In this disclosure, various aspects of packages and their formation are described. According to some embodiments, three-dimensional (3D) or 2.5D packages including both optical and electrical devices and methods of forming the same are provided. In particular, a photonic interposer or photonic structure is formed that includes a silicon nitride waveguide. In some embodiments, the photonic structure is formed by forming a structure with conductive wiring on a first substrate and a structure with a silicon nitride waveguide on a second substrate. The wiring structure and the waveguide structure are bonded together to form a photonic structure. By forming the conductive wiring and the silicon nitride waveguide on separate substrates, a high-temperature thermal process can be performed on the silicon nitride waveguide without damaging the conductive wiring to improve the optical characteristics of the silicon nitride waveguide. Photonic structures formed in this manner can provide reduced optical loss, improved efficiency, and improved high-speed communication of the photonic system. According to some embodiments, intermediate stages of forming the package and structure are shown. Some variations of some embodiments are discussed. Like reference numerals are used to designate like elements throughout the various views and illustrative embodiments.

Fig. 1A, 1B, and 1C illustrate cross-sectional views of intermediate steps in forming a photonic package 100 (see fig. 1C) according to some embodiments. In some embodiments, photonic package 100 acts as an input/output (I/O) interface between optical signals and electrical signals in a photonic system. For example, one or more of the photonic packages 100 may be used in a photonic system, such as photonic system 600 (see fig. 6) or another photonic system. The photonic package 100 shown in fig. 1A to 1C is a representative example, and other photonic packages are possible.

Turning to fig. 1A, according to some embodiments, the waveguide 104, the photonic component 106, and the electrical wiring 114 are formed within a plurality of dielectric layers 108. In some embodiments, a substrate (not separately indicated) may be provided first. The substrate may be, for example, a buried oxide ("BOX") substrate that includes a buried oxide layer and a semiconductor layer over the buried oxide layer. In other embodiments, the substrate may be, for example, glass, ceramic, dielectric, semiconductor, or the like, or a combination thereof. In some embodiments, the substrate may be a semiconductor substrate, such as a bulk semiconductor, etc., which may be doped (e.g., with a p-type or n-type dopant) or undoped. The substrate may be a wafer, such as a silicon wafer (e.g., a 12 inch silicon wafer). Other substrates, such as a multilayer substrate or a gradient substrate, may also be used. In some embodiments, the semiconductor material of the substrate may include silicon; germanium; a compound semiconductor including silicon carbide, gallium arsenide, gallium phosphide, indium arsenide, and/or indium antimonide; an alloy semiconductor comprising SiGe, gaAsP, alInAs, alGaAs, gaInAs, gaInP and/or GaInAsP; or a combination thereof. The oxide layer may be, for example, silicon oxide or the like.

In some embodiments, one or more semiconductor layers of the substrate are patterned to form a plurality of photonic components 106, which photonic components 106 may also be referred to as silicon devices. Some examples of photonic components 106 include waveguides 104, photonic devices, optical modulators, mode converters, photodetectors, grating couplers, and the like. The semiconductor layer may be patterned using suitable photolithography and etching techniques, which may involve an etching process that uses photoresist to define the pattern. According to some embodiments, photonic component 106 is physically and/or optically coupled to waveguide 104 to optically interact with waveguide 104 through optical signals. The waveguide 104 may be formed with the photonic component 106 (e.g., from the same semiconductor layer) or may be formed in a separate fabrication step. For example, a photodetector may be optically coupled to the waveguide 104 to detect an optical signal within the waveguide 104 and generate an electrical signal corresponding to the optical signal. The modulator may also receive the electrical signal and modulate the optical power within the waveguide 104 to generate a corresponding optical signal. In this manner, the photonic component 106 may input optical signals from the waveguide 104 or output optical signals to the waveguide 104. According to other embodiments, the photonic component 106 may include other active or passive components, such as a laser diode, an optical demultiplexer, a grating coupler, an edge coupler, or other types of photonic components or devices.

In some embodiments, the multilayer waveguide 104 may be formed in the dielectric layer 108. The waveguides 104 may be optically coupled to other waveguides 104 in the same layer and/or in adjacent layers. For example, the waveguide 104 may be optically coupled using an edge coupler, a grating coupler, a mode converter, or other type of optical coupling structure. The waveguide 104 may be formed of similar materials or different materials. For example, in some embodiments, the waveguide 104 may be formed of silicon. For example, the silicon waveguide may be formed by depositing a silicon layer and then patterning the silicon layer using suitable photolithography and etching techniques. A respective dielectric layer may be deposited over each layer of the silicon waveguide. In some embodiments, the waveguide 104 may be formed of silicon nitride. For example, a silicon nitride waveguide may be formed by depositing a silicon nitride layer and then patterning the silicon nitride layer using suitable photolithography and etching techniques. The deposition process may include CVD, PECVD, LPCVD, PVD, and the like. In other embodiments, the waveguide 104 may be formed of silicon oxynitride, a polymer, or other materials. Other materials are also possible. The photonic package 100 may include one type of waveguide or multiple types of waveguides. In some cases, nitride waveguides may be advantageous over silicon waveguides, as described in more detail below.

The dielectric layer 108 may comprise one or more suitable materials, such as silicon oxide, polymers, spin-on glass, flowable oxides, and the like. The dielectric layer 108 may be formed using suitable techniques such as CVD, flowable CVD, PVD, spin coating, lamination, and the like. In some embodiments, one or more layers of the dielectric layer 108 may be planarized using a Chemical Mechanical Polishing (CMP) process or the like.

Still referring to fig. 1A, according to some embodiments, electrical wiring 114, vias 112, bond pads 116, and/or bond pads 118 may be formed in or on each dielectric layer 108. The electrical wiring 114 may include wires, conductive vias, conductive contacts, redistribution layers, metallization layers, and the like. In some embodiments, electrical wiring 114 may electrically contact photonic component 106 and may provide interconnection therebetween. In some embodiments, the through-holes 112 may be formed to extend through one or more dielectric layers 108 to electrically connect different regions of the electrical wiring 114. Bond pads 116/118 may be formed on an upper or lower surface of dielectric layer 108 to allow electrical connection to other structures, dies, substrates, components, etc.

The electrical wiring 114, the through-holes 112, the bond pads 116, and/or the bond pads 118 may be formed in one or more suitable processes. For example, the process may include a damascene process, a dual damascene process, or another suitable process. As another example, the formation of the through-holes may include etching through the one or more dielectric layers 108 to form openings, and then filling the openings with a conductive material (such as titanium nitride, tantalum nitride, titanium, copper, tungsten, cobalt, ruthenium, etc., or combinations thereof). There may or may not be a dielectric liner formed of various conductive materials used in any of the conductive components surrounding those conductive components. In some embodiments, bond pad 116 and/or bond pad 118 may be a conductive pad, a conductive post, or the like. Other conductive components, arrangements, or configurations are possible.

In fig. 1B, one or more electronic die 122 are bonded to bond pads 116, according to some embodiments. The electronic die 122 may be, for example, a semiconductor device, die, or chip that communicates with the photonic component 106 using electrical signals. One electronic die 122 is shown in fig. 1B, but in other embodiments, the photonic package 100 may include two or more electronic dies 122. In some cases, multiple electronic die 122 may be incorporated into a single photonic package 100 in order to reduce processing costs. The electronic die 122 may include die connectors 124, and the die connectors 124 may be, for example, conductive pads, conductive pillars, or the like.

The electronic die 122 may include integrated circuits for interfacing with the photonic component 106, such as circuits for controlling the operation of the photonic component 106. For example, the electronic die 122 may include a controller, a driver, a transimpedance amplifier, or the like, or a combination thereof. In some embodiments, the electronic die 122 may also include a CPU. In some embodiments, the electronic die 122 includes circuitry for processing electrical signals received from the photonic component 106, such as for processing electrical signals received from the photonic component 106 including a photodetector. In some embodiments, electronic die 122 may control the high frequency signaling of photonic component 106 based on an electrical signal (digital or analog) received from another device or die. In some embodiments, the electronic die 122 may be an Electronic Integrated Circuit (EIC) or the like that provides serializer/deserializer (SerDes) functionality. In this manner, the electronic die 122 may be part of an I/O interface between optical and electrical signals within the photonic package 100, and the photonic package 100 described herein may be considered a system-on-a-chip (SoC) device or a system-on-integrated-circuit (SoIC) device.

In some embodiments, the electronic die 122 is bonded to the redistribution structure by dielectric-to-dielectric bonding and/or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, etc.). In such embodiments, covalent bonds may be formed between bonding layers, such as between the topmost dielectric layer 108 and a surface dielectric layer (not separately shown) of the electronic die 122. During bonding, metal-to-metal bonding may also occur between die connectors 124 of electronic die 122 and conductive pads 116.

In fig. 1C, a dielectric material 126 is formed over the electronic die 122 and the dielectric layer 108, according to some embodiments. Dielectric material 126 may be formed of silicon oxide, silicon nitride, a polymer, or the like, or a combination thereof. The dielectric material 126 may be formed by CVD, PVD, ALD, a spin-on dielectric process, or the like, or a combination thereof. In some embodiments, the dielectric material 126 may be formed by HDP-CVD, FCVD, or the like, or a combination thereof. In some embodiments, the dielectric material 126 may be a gap fill material, which may include one or more of the above exemplary materials. Other dielectric materials formed by any acceptable process may be used. The dielectric material 126 may be planarized using a planarization process such as a CMP process, a polishing process, or the like. In some embodiments, the planarization process may expose the electronic die 122 such that the surface of the electronic die 122 and the surface of the dielectric material 126 are coplanar.

Further, in fig. 1C, an optional support 125 is attached to the structure according to some embodiments. The support 125 is a rigid structure attached to the structure to provide structural or mechanical stability. The use of the support 125 may reduce warpage or bending, which may improve the performance of an optical structure such as the waveguide 104 or the photonic component 106. The support 125 may include one or more materials, such as silicon (e.g., silicon wafer, bulk silicon, etc.), silicon oxide, metal, organic core material, etc., or another type of material. The support 125 may be attached to the structure (e.g., to the dielectric material 126 and/or the electronic die 122) using an adhesive layer, direct bonding, or another suitable technique. The support 125 may also have a lateral dimension (e.g., length, width, and/or area) that is greater than, about equal to, or less than the lateral dimension of the structure.

Fig. 2A, 2B, and 2C illustrate the formation of a wiring structure 200 according to some embodiments. In some embodiments, the wiring structure 200 includes a redistribution structure 210 that may be electrically connected to the via 204. In this manner, wiring structure 200 may provide electrical wiring and electrical interconnections for the photonic system. In some embodiments, the wiring structure 200 may include passive or active devices. In some embodiments, the wiring structure 200 may be another type of structure, such as an integrated fan-out structure, an interconnect substrate, an interposer, and the like. Fig. 2A illustrates a substrate 202 according to some embodiments. The substrate 202 may be, for example, a glass substrate, a ceramic substrate, a dielectric substrate, an organic substrate (e.g., an organic core), a semiconductor substrate (e.g., a semiconductor wafer), etc., or a combination thereof. The substrate 202 may be referred to as having a front side or surface (e.g., the side facing upward in fig. 2A) and a back side or surface (e.g., the side facing downward in fig. 2A).

In fig. 2B, a via 204 is formed in the front side of the substrate 202, according to some embodiments. For example, the via 204 may be formed by forming an opening in the front side of the substrate 202 and then filling the opening with a conductive material. The openings may extend partially into the substrate 202 and may be formed using suitable photolithographic and etching techniques. In some embodiments, a liner (not shown), such as a diffusion barrier layer, an adhesive layer, or the like, may be first formed in the opening. In some embodiments, a seed layer (not shown), which may include copper, copper alloy, or the like, may then be deposited in the opening. A conductive material such as plating, electroless plating, or the like may be used to form the via 204 in the opening. The conductive material may comprise, for example, a metal or metal alloy, such as copper, silver, gold, tungsten, cobalt, aluminum, or alloys thereof. A planarization process (such as a CMP process or mechanical polishing) may be performed to remove excess conductive material so that the top surfaces of the via 204 and the substrate 202 are flush. This is an example and other materials or techniques are possible.

In fig. 2C, a redistribution structure 210 is formed on the front side of the substrate 202 and on the vias 204, according to some embodiments. The redistribution structure 210 includes a dielectric layer 212 and conductive features 214 formed in the dielectric layer 212 that provide interconnects and electrical routing. Dielectric layer 212 may be, for example, an insulating layer or a passivation layer, and may include one or more materials similar to the materials of dielectric layer 108 described above, such as silicon oxide, silicon nitride, a polymer, a molding material, a sealant, or may include a different material than dielectric layer 108. In some embodiments, each dielectric layer 212 may have a thickness in the range of about 100nm to about 3000 nm. The conductive features 214 may include conductive lines, conductive vias, metallization layers, redistribution layers, etc., and the conductive features 214 may be formed by a damascene process (e.g., single damascene, dual damascene, etc.). The conductive member 214 may comprise a conductive material such as copper. In some embodiments, the conductive material of conductive feature 214 may have a thickness in the range of about 100nm to about 3000nm or have a width in the range of about 100nm to about 4000 nm. Other materials, thicknesses, dimensions, or techniques are possible. Conductive member 214 may be electrically connected to via 204. The redistribution structure 210 may include a layer of conductive features 214 or multiple layers of conductive features 214. In some embodiments, the topmost dielectric layer 212 (e.g., the dielectric layer 212 on the front side of the wiring structure 200) may be a material suitable for dielectric-to-dielectric bonding, such as silicon oxide, silicon oxynitride, silicon carbonitride, or another suitable bonding material formed using CVD or another suitable technique. In some embodiments, individual wiring structures 200 may then be singulated from the substrate 202.

Fig. 3A and 3B illustrate the formation of an optical routing structure 300 according to some embodiments. In some embodiments, the optical routing structure 300 includes a waveguide structure 310, the waveguide structure 310 including one or more waveguides 314 formed in one or more dielectric layers 316. In this manner, optical routing structure 300 may provide optical routing and optical interconnection for photonic systems. In some embodiments, optical routing structure 300 may include passive or active devices. In some embodiments, the optical routing structure 300 may be another type of structure, such as an integrated fan-out structure, an interconnect substrate, an interposer, and the like. Fig. 3A illustrates a substrate 302 according to some embodiments. The substrate 302 may be, for example, a glass substrate, a ceramic substrate, a dielectric substrate, an organic substrate (e.g., an organic core), a semiconductor substrate (e.g., a semiconductor wafer), etc., or a combination thereof. Substrate 302 may be referred to as having a front side or surface (e.g., the side facing upward in fig. 3A) and a back side or surface (e.g., the side facing downward in fig. 3A). In some embodiments, the optical routing structure 300 is then bonded to the wiring structure 200 to form an interconnect structure 400 (see fig. 4C).

In fig. 3B, a waveguide structure 310 is formed on the front side of the substrate 302, according to some embodiments. In some embodiments, the waveguide structure 310 may include one or more silicon nitride waveguides 314 (also referred to as "nitride waveguides 314") formed in respective dielectric layers 316. Dielectric layer 316 may comprise a suitable dielectric material, such as silicon oxide, and dielectric layer 316 may be deposited using a suitable technique. In some embodiments, each dielectric layer 316 may have a thickness in the range of about 50nm to about 5000 nm. In some embodiments, the topmost dielectric layer 316 (e.g., the dielectric layer 316 on the front side of the waveguide structure 310) may be a material suitable for dielectric-to-dielectric bonding, such as silicon oxide, silicon oxynitride, silicon carbonitride, or other suitable bonding material formed using CVD or another suitable technique.

The silicon nitride waveguide 314 may be formed, for example, by first depositing a silicon nitride layer on the dielectric layer 316. The silicon nitride layer may be formed using a suitable deposition technique, such as CVD, PECVD, LPCVD, PVD a. The silicon nitride layer may then be patterned using acceptable photolithography and etching techniques to form one or more nitride waveguides 314. For example, in some embodiments, a hard mask layer may be formed over a silicon nitride layer and patterned. An etching process may then be used to transfer the pattern of the hard mask layer to the silicon nitride layer. The etching process may include, for example, a dry etching process and/or a wet etching process. The etching process may be selective to silicon nitride relative to silicon oxide or other materials. The silicon nitride layer may be etched to form a recess defining nitride waveguide 314, wherein sidewalls of the remaining unrecessed portions define sidewalls of nitride waveguide 314. In some embodiments, more than one photolithography and etch sequence may be used in order to pattern the silicon nitride layer. A dielectric layer 316 may be deposited over nitride waveguide 314 and this process may be repeated if desired to form a multilayer nitride waveguide 314. In some embodiments, nitride waveguide 314 may have a thickness in the range of about 50nm to about 2000nm or have a width in the range of about 60nm to about 4000 nm. Other materials, thicknesses, dimensions, or techniques are also possible. In some embodiments, dielectric layer 316 may be planarized (e.g., using a CMP process, etc.) prior to forming upper nitride waveguide 314 or after forming lower nitride waveguide 314.

The nitride waveguide 314 or waveguides 314 may be patterned from a silicon nitride layer. If multiple nitride waveguides 314 are formed, the multiple nitride waveguides 314 may be separate, spaced apart nitride waveguides 314 or the multiple nitride waveguides 314 may be connected as a single continuous structure. In some embodiments, one or more nitride waveguides 314 form a continuous ring. In some embodiments, nitride waveguide 314 may include other photonic components, such as grating couplers, edge couplers, or couplers (e.g., mode converters) that allow optical signals to be transmitted between two nitride waveguides 314 and/or between nitride waveguides 314 and external optical structures or photonic components. In some embodiments, individual optical routing structures 300 may be singulated from substrate 302.

In some cases, a waveguide formed of silicon nitride (e.g., nitride waveguide 314) may be more advantageous than a waveguide formed of silicon. For example, silicon nitride has a higher dielectric constant than silicon, and thus nitride waveguides may have a greater optical internal confinement than silicon waveguides. This may also allow the performance or leakage of the nitride waveguide to be less sensitive to process variations, less sensitive to dimensional uniformity, and less sensitive to surface roughness (e.g., edge roughness or linewidth roughness). The reduced process sensitivity may allow nitride waveguides to be manufactured more easily or less expensively than silicon waveguides. These characteristics may allow nitride waveguides to have lower propagation losses (e.g., lower transmission losses or smaller optical loss coefficients) than silicon waveguides. In some cases, the propagation loss (dB/cm) of the nitride waveguide may be between about 0.1% and about 50% of the silicon waveguide. In some cases, nitride waveguides may also be less sensitive to ambient temperature than silicon waveguides. For example, a nitride waveguide may have a sensitivity to temperature as little as about 1% of the sensitivity of a silicon waveguide to temperature. In this way, in some cases, nitride waveguides may be more suitable than silicon waveguides for transmitting optical signals over relatively longer distances.

In some embodiments, a thermal process, such as annealing, is performed on the waveguide structure 310. The thermal process may include a temperature in the range of about 600 ℃ to about 1500 ℃, although other temperatures are also possible. The thermal process may include nitrogen (e.g., the ambient environment of N ₂₎, etc., or may include a low pressure environment such as vacuum. In some embodiments, the thermal process may be performed for between about 120 seconds and about 3 hours. Other parameters are also possible.

In some cases, performing a thermal process on a silicon nitride waveguide (e.g., nitride waveguide 314) may reduce defects and impurities within the silicon nitride, which may improve the performance of the silicon nitride waveguide. For example, annealing nitride waveguide 314 may reduce propagation loss of nitride waveguide 314, which may allow for more efficient transmission of optical signals or optical power. In this manner, annealing nitride waveguide 314 may allow for improved device performance, improved signal-to-noise ratio of the optical signal, improved transmission over longer distances, more efficient optical signal transmission, or reduced power consumption. In some cases, performing the thermal process at a higher temperature (e.g., greater than about 1000 ℃) may improve the performance of nitride waveguide 314 as compared to performing the thermal process at a lower temperature (e.g., less than about 1000 ℃). However, in some cases, exposing the conductive components (e.g., the redistribution structure 210) to these higher temperatures may result in thermal damage, such as thermally induced defects, undesired diffusion of conductive materials, or other problems. By forming the waveguide structure 310 and the redistribution structure 210 on separate substrates, the thermal process may be performed on the waveguide structure 310 at a higher temperature without subjecting the redistribution structure 210 to the higher temperature. In this way, high performance nitride waveguides 314 may be formed without risking thermal damage to the redistribution structure 210. Accordingly, the nitride waveguide 314 that is annealed at a higher temperature may be referred to herein as a "high performance nitride waveguide".

In fig. 4A, 4B, and 4C, the wiring structure 200 is bonded to the optical routing structure 300 to form an interconnect structure 400, according to some embodiments. The interconnect structure 400 allows both electrical interconnects from the redistribution structure 210 and optical interconnects from the waveguide structure 310. In this manner, interconnect structure 400 may be considered a "hybrid interconnect structure" or a "hybrid interposer. As described above, the interconnect structure 400 allows for higher performance optical interconnects without resulting in reduced electrical communication performance. In some embodiments, the wire structure 200 and/or the optical routing structure 300 may be singulated before or after being bonded together.

In fig. 4A, optical routing structure 300 is flipped upside down and bonded to wiring structure 200 according to some embodiments. The optical routing structure 300 is flipped up and down so that the front side of the optical routing structure 300 faces the front side of the wiring structure 200. The waveguide structure 310 of the optical routing structure 300 is then bonded to the redistribution structure 210 of the wiring structure 200 by dielectric-to-dielectric bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, etc.). In such embodiments, covalent bonds may be formed between the topmost dielectric layers, such as between the topmost bonding material of dielectric layer 212 of redistribution structure 210 and the topmost bonding material of dielectric layer 316 of waveguide structure 310. In some embodiments, a plurality of interconnect structures 400 may be formed over the substrate 202, and then the plurality of interconnect structures 400 may be singulated to form individual interconnect structures 400.

In some embodiments, an optional surface treatment is performed on the topmost dielectric layer 212 of the redistribution structure 210 and/or the topmost dielectric layer 316 of the waveguide structure 310 prior to performing the bonding process. The surface treatment may include, for example, an activation process, a cleaning process, a dry process, a wet process, a plasma process, an exposure to an inert gas, an exposure to H ₂, an exposure to N ₂, an exposure to O ₂, and the like, or a combination thereof. However, any suitable activation process may be utilized. The optical routing structure 300 is then aligned with the wiring structure 200 and placed in physical contact with the wiring structure 200. For example, the topmost dielectric layer 212 of the redistribution structure 210 may be placed in physical contact with the topmost dielectric layer 316 of the waveguide structure 310. Then, the optical routing structure 300 and the wiring structure 200 may be subjected to a heat treatment and/or a contact pressure to join the optical routing structure 300 and the wiring structure 200. In this manner, the dielectric-to-dielectric bonding of the optical routing structure 300 and the wiring structure 200 forms a bonding structure or "combined interposer". In some embodiments, the bonded structure is baked, annealed, pressed, or otherwise treated to strengthen or ultimately complete the bond.

In fig. 4B, the substrate 302 of the optical routing structure 300 is removed, according to some embodiments. For example, the substrate 302 may be removed using a planarization process (e.g., a CMP process, a grinding process, etc.) and/or an etching process (e.g., wet or dry etching). Removing substrate 302 may expose waveguide structure 310, as shown in fig. 4B.

In fig. 4C, additional conductive features 414 are formed in additional dielectric layer 416, according to some embodiments. An additional conductive feature 414 and an additional dielectric layer 416 may be formed on the top surface of waveguide structure 310. The additional conductive features 414 may include conductive lines, conductive vias, redistribution layers, metallization patterns, bond pads, vias, and the like. In some cases, the additional conductive features 414 and the additional dielectric layer 416 may be considered as a redistribution structure. For example, the additional conductive feature 414 may include a bond pad 424 located at a top surface of the additional dielectric layer 416. In some embodiments, the bond pads 424 may have a pitch in the range of about 4000nm and about 9000nm, although other pitches or other bond pad 424 sizes are possible. The additional conductive features 414 may also include through vias that extend through the waveguide structure 310 and electrically connect with the conductive features 214 of the redistribution structure 210. In this manner, additional conductive feature 414 may be electrically connected to conductive feature 214. The redistribution structure 210, the waveguide structure 310, the additional conductive features 414, and the additional dielectric layer 416 may be collectively referred to herein as a hybrid structure 410.

The additional conductive features 414 may be formed using materials or techniques similar to those previously described, such as those described with respect to the conductive features 214 of the redistribution structure 210 or the electrical wiring 114 of the photonic package 100. In some embodiments, additional conductive features 414 may be formed using a different material or technique than conductive features 214 or electrical wiring 114. Additional dielectric layer 416 may be formed using materials or techniques similar to those previously described, such as those described with respect to dielectric layers 108, 212, or 316. In some embodiments, additional dielectric layer 416 may be formed using a different material or technique than dielectric layer 108, 212, or 316. In some embodiments, the topmost additional dielectric layer 416 may be a material suitable for dielectric to dielectric bonding, such as silicon oxide, silicon oxynitride, silicon carbonitride, or another suitable material formed using CVD or another suitable technique. In some cases, this topmost bonding material may be similar to the topmost bonding material of dielectric layer 212 and/or dielectric layer 316.

In some embodiments, one or more optocouplers 404 may be formed in the additional dielectric layer 416 of the hybrid structure 410. The optical coupler 404 may facilitate optical coupling between the nitride waveguide 314 and the above components, such as the above photonic components, photonic devices, photonic packages, laser dies, optical fibers, grating couplers, waveguides, and the like. In this way, optical signals and/or optical power may be transmitted between nitride waveguide 314 and the structure above. In some embodiments, the optocoupler 404 may be formed by etching a recess in the additional dielectric layer 416 and then filling the recess with a suitable material. Suitable materials may be, for example, silicon nitride, silicon oxide, optical adhesives, polymers, spin-on glass, or other materials. In some embodiments, a planarization process (e.g., a CMP process, etc.) may be performed such that the respective top surfaces of the hybrid structure 410 are approximately flush. As shown in fig. 5D, the waveguide structure 310, the redistribution structure 210, the additional dielectric layer 416, and/or the substrate 202 may have coplanar sidewalls.

Fig. 5A, 5B, 5C, and 5D illustrate the formation of photonic structure 500 in accordance with some embodiments. In fig. 5A, photonic package 100, photonic die 510, and semiconductor die 520 are attached to interconnect structure 400 according to some embodiments. In other embodiments, a different number, arrangement, or type of photonic packages 100, photonic die 510, or semiconductor die 520 may be attached to interconnect structure 400. In other embodiments, interconnect structure 400 may be devoid of photonics die 510 or semiconductor die 520.

In some embodiments, photonic package 100, photonic die 510, and/or semiconductor die 520 are bonded to interconnect structure 400 by dielectric-to-dielectric bonding and/or metal-to-metal bonding (e.g., direct bonding, fusion bonding, oxide-to-oxide bonding, hybrid bonding, etc.). In such embodiments, covalent bonds may be formed between bonding layers, such as between the topmost dielectric layer 416 and a surface dielectric layer (not separately shown) of each of the photonic package 100, the photonic die 510, and/or the semiconductor die 520. During bonding, metal-to-metal bonding may also occur between bond pads 424 of interconnect structure 400 and bond pads of photonic package 100, bond pads of photonic die 510, and/or bond pads of semiconductor die 520. In this manner, photonics die 510 and/or semiconductor die 520 may be electrically connected to interconnect structure 400.

The photonic package 100 may be similar to the photonic package 100 previously described with respect to fig. 1A-1C. In some embodiments, the waveguide 104 of the photonic package 100 may be optically coupled to the waveguide 314 of the interconnect structure 400. An optical coupler (e.g., similar to optical coupler 404) between photonic package 100 and waveguide 314 is not shown in fig. 5A, but may be present in other embodiments. In this manner, optical signals and/or optical power may be transmitted between waveguide 104 of photonic package 100 and waveguide 314 of interconnect structure 400.

Photonics die 510 may be, for example, a chip, a die, a system-on-chip (SoC) device, a system-on-integrated-circuit (SoIC) device, a package, or the like, or a combination thereof. In some embodiments, photonics die 510 may include a laser diode, an LED, a photonic component (e.g., photodetector, modulator, mode converter, etc.), a waveguide, or other photonic device or photonic component. In some embodiments, photonics die 510 is optically coupled to waveguide 314 of interconnect structure 400, and optical signals and/or optical power may be transmitted between photonics die 510 and waveguide 314. In some embodiments, optical coupler 404 may facilitate optical coupling between photonics die 510 and waveguide 314. For example, in some embodiments, photonics die 510 includes a laser diode that provides optical power to waveguide 314. In some embodiments, optical power may also be provided to photonic package 100 from waveguide 314. This is an example and other photonics die 510 are possible.

Semiconductor die 520 may be, for example, a chip, a die, a system on a chip (SoC) device, a system on integrated circuit (SoIC) device, a package, or the like, or a combination thereof. Semiconductor die 520 may include one or more processing devices such as a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), an Application Specific Integrated Circuit (ASIC), a High Performance Computing (HPC) die, or the like, or a combination thereof. Semiconductor die 520 may include one or more memory devices, which may be volatile memory, such as Dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), high Bandwidth Memory (HBM), another type of memory, and the like.

In fig. 5B, photonic package 100, photonic die 510, and semiconductor die 520 are encapsulated with encapsulant 502, according to some embodiments. The sealant 502 may be a molding compound, an epoxy, or the like, and the sealant 502 may be applied by compression molding, transfer molding, or the like. An encapsulant 502 may be formed over interconnect structure 400 such that photonic package 100, photonic die 510, and semiconductor die 520 are buried or covered. The encapsulant 502 may then be cured. The encapsulant 502 may be planarized using a planarization process (e.g., a CMP process, etc.). In some embodiments, the planarization process exposes the top surfaces of photonic package 100, photonic die 510, and/or semiconductor die 520. In other embodiments, one or more of photonic package 100, photonic die 510, and semiconductor die 520 may remain covered. In some embodiments, the exposed top surfaces of photonic package 100, photonic die 510, and semiconductor die 520 (if present) are approximately flush with the top surface of encapsulant 502. In some embodiments, encapsulant 502 may cover sidewalls of one or more of photonic package 100, photonic die 510, and/or semiconductor die 520. In other embodiments, after the encapsulant 502 is formed, one or more sidewalls of the photonic package 100, the photonic die 510, and/or the semiconductor die 520 may remain exposed.

In fig. 5C, the backside of interconnect structure 400 is thinned to expose via 204, according to some embodiments. The backside of the interconnect structure 400 (e.g., the backside of the substrate 202) may be removed using a planarization process (e.g., a CMP process, a grinding process, etc.), an etching process, or a combination thereof. In some embodiments, after thinning, the surfaces of the via 204 and the substrate 202 may be approximately flush. In some embodiments, the substrate 202 may have a thickness in the range of about 20 μm to about 150 μm after thinning, although other thicknesses are possible.

In fig. 5D, conductive pads 530 are formed on the exposed vias 204 and substrate 202, according to some embodiments. Conductive pad 530 may be a conductive pad or a conductive post electrically connected to hybrid structure 410 through via 204. In some embodiments, conductive pad 530 includes an Under Bump Metallization (UBM). The conductive pads 530 may be formed of a conductive material such as copper, another metal or metal alloy, or the like, or a combination thereof. The material of the conductive pads 530 may be formed by a suitable process, such as plating. For example, in some embodiments, the conductive pads 530 are metal pillars (such as copper pillars) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on top of the conductive pad 530. The metal cover layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process. In some embodiments, a passivation layer (not shown) may be formed over the substrate 202 to surround or partially cover the conductive pads 530.

In fig. 6, a photonic structure 500 is attached to an interconnect substrate 650 to form a photonic system 600, according to some embodiments. The interconnect substrate 650 provides additional routing and stability for the photonic structure 500. In some embodiments, the interconnect substrate 650 may be, for example, an interposer, a cored substrate, "a semi-finished substrate," a Printed Circuit Board (PCB), or the like. In some cases, the interconnect substrate 650 may be devoid of active devices. In some embodiments, the interconnect substrate 650 may include wiring layers (e.g., wiring layers 652 and 654) formed on the core substrate 656. The routing layers 652/654 may include conductive lines, conductive vias, etc., formed in various dielectric layers. The cored substrate 656 may comprise a material such as an organic substrate (e.g., an organic core), a flavourant laminated film (ABF), a pre-impregnated composite fiber ("prepreg") material, an epoxy, a molding compound, an epoxy molding compound, a glass fiber reinforced resin material, a Printed Circuit Board (PCB) material, a silica filler, a polymeric material, a polyimide material, paper, glass fibers, non-woven fiberglass fabric, glass, ceramic, other laminates, and the like, or combinations thereof. In some embodiments, the cored substrate may be a double sided Copper Clad Laminate (CCL) substrate or the like. Wiring layers 652 and 654 on opposite sides of the core substrate 656 may be electrically connected through the core substrate 656 by conductive vias 658. In some cases, the conductive vias 658 may be filled with an insulating fill material. In some embodiments, the interconnect substrate 650 may include a passivation layer 660 formed over one or more sides of the interconnect substrate 650. The passivation layer 660 may include a material such as nitride, oxide, polyimide, low temperature polyimide, solder resist, combinations thereof, and the like. Once the passivation layer 660 is formed, the passivation layer 660 can be patterned (e.g., using a suitable photolithography and etching process) to expose portions of the wiring layers 652 and 654.

Still referring to fig. 6, according to some embodiments, conductive connections 602 are formed on the topmost wiring layer 652, and the photonic structure 500 is connected to the interconnect substrate 650 through the conductive connections 602. The conductive connections 602 may be Ball Grid Array (BGA) connections, solder balls, metal pillars, controlled collapse chip connection (C4) bumps, micro bumps, bumps formed by electroless nickel-electroless palladium immersion gold (ENEPIG) technology, or the like. The conductive connection 602 may include a conductive material such as solder, copper, aluminum, gold, nickel, silver, palladium, tin, or the like, or a combination thereof. In some embodiments, the conductive connection 602 is formed by initially forming a solder layer by such common methods as evaporation, plating, printing, solder transfer, ball placement, and the like. Once the solder layer is formed on the structure, reflow may be performed to shape the material into the desired bump shape. In another embodiment, the conductive connection 602 is a metal pillar (such as a copper pillar) formed by sputtering, printing, electroplating, electroless plating, CVD, or the like. The metal posts may be solderless and have substantially vertical sidewalls. In some embodiments, a metal cap layer (not shown) is formed on top of the conductive connection 602. The metal cover layer may include nickel, tin-lead, gold, silver, palladium, indium, nickel-palladium-gold, nickel-gold, etc., or combinations thereof, and may be formed by a plating process. In some embodiments, the conductive connection 662 may also be formed on the bottommost wiring layer 654. The conductive connection 662 may be similar to one or more of the examples described above with respect to the conductive connection 602.

The conductive pads 530 of the photonic structure 500 may be placed on the conductive connections 602. Once in physical contact, a reflow process may be utilized to bond the conductive connection 602 to the conductive pad 530. Accordingly, photonic structure 500 may be physically and electrically connected to interconnect substrate 650. In some embodiments, an underfill 604 may be deposited between the photonic structure 500 and the interconnect substrate 650, and the underfill 604 may surround the conductive connection 602. In this way, a photonic system 600 that incorporates both electrical wiring and high performance silicon nitride waveguides can be formed.

Fig. 7A, 7B, and 7C illustrate the formation of photonic structure 700 and photonic system 750 in accordance with some embodiments. Photonic structure 700 is similar to photonic structure 500 except that photonic package 100, photonic die 510, and semiconductor die 520 are connected to interconnect structure 400 by conductive connections 702 rather than by direct bonding. For example, referring to fig. 7A, conductive connection 702 may be formed on a bond pad 424 of interconnect structure 400 (referring to fig. 4C). The conductive connection 702 may be similar to the conductive connection 602 previously described or other conductive connections described herein. After photonic package 100, photonic die 510, and semiconductor die 520 are placed on conductive connection 702, a reflow process may be performed to bond photonic package 100, photonic die 510, and semiconductor die 520 to interconnect structure 400. In this manner, photonic package 100, photonic die 510, and semiconductor die 520 may be physically and electrically connected to the interconnect structure.

In fig. 7B, an underfill 704 may be deposited between photonic package 100, photonic die 510, and/or semiconductor die 520, and interconnect structure 400. The underfill 704 may also surround the conductive connection 702. A sealant 502 can then be deposited over the assembly, similar to the sealant 502 described with respect to fig. 5B. In some embodiments, photonic package 100 and/or photonic die 510 may be optically coupled to waveguide 314 of interconnect structure 400. In some embodiments, photonic package 100 and/or photonic die 510 may be optically coupled through underfill 704. In other embodiments, the underfill 704 may not be present in the optical coupling path, or another suitable material (e.g., optical adhesive, etc.) may be deposited in the optical coupling path prior to depositing the underfill 704. In other embodiments, some components may be directly bonded to interconnect structure 400 while other components are connected to interconnect structure 400 using conductive connections 702. In this way, photonic structure 700 utilizing conductive connections may be formed.

In fig. 7C, photonic structure 700 is connected to interconnect substrate 650 to form photonic system 750, according to some embodiments. The photonic structure 700 may be bonded to the interconnect substrate 650 using the conductive connection 602, similar to the process described previously with respect to fig. 6. The interconnect substrate 650 may also be similar to the interconnect substrate 650 previously described with respect to fig. 6. Thus, the photonic structure 700 may be physically and electrically connected to the interconnect substrate 650. In some embodiments, an underfill 604 may be deposited between the photonic structure 700 and the interconnect substrate 650, and the underfill 604 may surround the conductive connection 602. In this way, a photonic system 750 that incorporates both electrical wiring and high performance silicon nitride waveguides can be formed.

Fig. 8A-8F illustrate the formation of a photonic structure 800 in accordance with some embodiments. Photonic structure 800 is similar to photonic structure 500 except that waveguides are formed on wiring structure 200 to form hybrid wiring structure 810. Fig. 8A illustrates a wiring structure 200 according to some embodiments. The wiring structure 200 shown in fig. 8A may be similar to the wiring structure 200 shown in fig. 2C. For example, the redistribution structure 210 may be formed over the substrate 202, wherein the redistribution structure 210 includes conductive features 214 formed in a dielectric layer 212.

In fig. 8B, silicon nitride waveguides 814 are formed over the redistribution structure 210, according to some embodiments. In this way, the hybrid wiring structure 810 can be formed. The silicon nitride waveguide 814 may be formed using techniques similar to those previously described with respect to the nitride waveguide 314 described with respect to fig. 3B. Fig. 8B shows a single layer of nitride waveguide 814 formed in a dielectric layer. In other embodiments, the nitride waveguide 814 may include a multi-layer nitride waveguide 814 formed in a plurality of dielectric layers. In some cases, nitride waveguide 814 may be coupled to other adjacent nitride waveguides 814. In some embodiments, the topmost dielectric layer may be a material suitable for dielectric to dielectric bonding, such as silicon oxide, silicon oxynitride, silicon carbonitride, or another suitable bonding material formed using CVD or another suitable technique.

In some embodiments, nitride waveguide 814 is not annealed. In other embodiments, the nitride waveguide 814 is annealed at a relatively low temperature, such as a temperature less than about 300 ℃. Annealing the nitride waveguide 814 at a lower temperature may reduce the risk of thermal damage (e.g., to the redistribution structure 210). However, in some cases, nitride waveguide 814 may have a greater optical loss than high performance nitride waveguide 314 of waveguide structure 310. Accordingly, in some embodiments, nitride waveguide 814 may be used to transmit optical signals and/or optical power over a smaller distance than high performance nitride waveguide 314.

In fig. 8C, waveguide structure 310 is bonded to hybrid wiring structure 810, according to some embodiments. A dielectric-to-dielectric bond may be used to bond waveguide structure 310 to hybrid wiring structure 810, which may be similar to the bond described in fig. 4A. In some embodiments, after bonding, nitride waveguide 814 may be optically coupled to nitride waveguide 314. In fig. 8D, the substrate 302 is removed using a planarization process, an etching process, and the like, which may be similar to the process described previously with respect to fig. 4B. The waveguide structure 310 may be exposed by removing the substrate 302.

In fig. 8E, additional conductive features 414 are formed on waveguide structure 310 to form interconnect structures 850, according to some embodiments. Additional conductive features 414 may be formed in additional dielectric layer 416 using materials or techniques similar to those previously described with respect to fig. 4C. For example, the additional conductive features 414 may include wires, conductive vias, redistribution layers, metallization patterns, bond pads 424, through vias, and the like. In some embodiments, one or more optocouplers 404 may also be formed.

In fig. 8F, photonic package 100, photonic die 510, and semiconductor die 520 are bonded to interconnect structure 850 to form photonic structure 800, according to some embodiments. The photonic package 100, the photonic die 510, and the semiconductor die 520 may be similar to the photonic package 100, the photonic die 510, and the semiconductor die 520 previously described, and may be bonded using techniques similar to those previously described. For example, bonding may utilize a direct bonding process or may utilize conductive connections. A sealant 502 may be deposited over the assembly. Additionally, in some embodiments, the substrate 202 may be thinned to expose the vias 204, and conductive pads 530 may be formed on the backside of the substrate 202. In this way, photonic structure 800 may be formed, with photonic structure 800 utilizing high performance nitride waveguide 314 for longer range communications and nitride waveguide 813 for shorter range communications.

Fig. 9A-9F illustrate the formation of a photonic structure 900 including a plurality of waveguide structures 910 according to some embodiments. Fig. 9A-9E illustrate the formation of an interconnect structure 950, the interconnect structure 950 being similar to the interconnect structure 400, except that the interconnect structure 950 includes a plurality of waveguide structures 910 instead of the single waveguide structure 310. The photonic structure 900 is similar to the photonic structure 500 except that multiple waveguide structures 910 are used instead of a single waveguide structure 310. In some cases, smaller waveguide structures may have less stress, warpage, or bending than larger waveguide structures. Accordingly, the use of multiple smaller waveguide structures 910 may reduce the risk of cracking, warping, or other stress-related problems. Thus, in some cases, yield and performance may be improved.

In fig. 9A, a plurality of regions of nitride waveguide 914 are formed over substrate 902. The substrate 902 may be similar to the substrate 302 previously described with respect to fig. 3A. The nitride waveguide 914 may be formed using materials and techniques similar to those previously described with respect to the waveguide structure 310 (see fig. 3B). For example, one or more layers of nitride waveguide 914 may be formed in dielectric layer 916. In some embodiments, a high temperature anneal is performed on nitride waveguide 914 to improve optical characteristics, similar to the high temperature anneal described previously with respect to waveguide 314. Regions of nitride waveguide 914 may be separated by regions of dielectric layer 916 that are free of nitride waveguide 914. In some cases, these areas without waveguides may be considered as "scribe areas".

In fig. 9B, a singulation process is performed to singulate the structures into individual waveguide structures 910 located on individual portions of the substrate 902. Each waveguide structure 910 includes a nitride waveguide 914 formed in a dielectric layer 916. Singulation may be performed using a mechanical saw, a plasma cutting process, a laser cutting process, an etching process, or a combination thereof. In some cases, singulating the larger waveguide structure into smaller waveguide structures 910 in this manner may allow the waveguide structures 910 to have reduced overall stress.

In fig. 9C, a plurality of waveguide structures 910A-910B are bonded to the wiring structure 200, according to some embodiments. The wiring structure 200 may be similar to the wiring structure 200 previously described. Fig. 9C shows two waveguide structures 910A-910B, but more or fewer waveguide structures 910 may be joined in other embodiments. The waveguide structures 910 may be similar or different. For example, the waveguide structure 910 may have different dimensions, waveguide configurations, or thicknesses. In other embodiments, one or more of the waveguide structures 910 may be devoid of waveguides. The waveguide structures 910A-910B may be bonded to the redistribution structure 210 using dielectric-to-dielectric bonding or the like, which may be similar to the bonding process described previously with respect to fig. 4A.

In fig. 9D, the substrate 902 is removed from over the waveguide structures 910A-910B and a filler material 952 is deposited over the structures, according to some embodiments. The substrate 902 may be removed using a thinning process, a planarization process, an etching process, or a combination thereof, which may be similar to the process described previously with respect to fig. 4A. Removing the substrate 902 may expose the waveguide structures 910A-910B. The filler material 952 may be an oxide, nitride, sealant, molding material, polymer, spin-on glass, or another suitable dielectric material. In some embodiments, the planarization process is performed such that the fill material 952 and the top surfaces of the waveguide structures 910A-910B are flush.

In fig. 9E, additional conductive features 954 and additional dielectric layers 956 are formed over waveguide structures 910A-910B and filler material 952, according to some embodiments. Additional conductive features 954 and additional dielectric layer 956 may be formed using materials or techniques similar to those used to form additional conductive features 414, bond pads 424, and dielectric layer 416 described with respect to fig. 4C. Additional conductive members 954 may make electrical contact with the redistribution structure 210. In other embodiments, additional conductive members 954 may extend into filler material 952. In some embodiments, one or more optocouplers 955 may be formed in the additional dielectric layer 956.

In other embodiments, the additional conductive members 954 and the additional dielectric layer 956 may be formed on the waveguide structures 910 prior to singulation of the waveguide structures 910 such that each waveguide structure 910 (e.g., 910A or 910B) has its own additional conductive members 954 and additional dielectric layer 956 thereon. In such an embodiment, the waveguide structure 910 and the additional dielectric layer 956 thereon may have coplanar sidewalls. In addition, a filler material 952 may extend on sidewalls of each additional dielectric layer 956 and may separate the additional dielectric layers 956 respectively formed on adjacent waveguide structures 910. In such an embodiment, the top surfaces of the filler material 952 and each respective additional dielectric layer 956 may be flush.

In fig. 9F, photonic package 100, photonic die 510, and semiconductor die 520 are bonded to interconnect structure 950 to form photonic structure 900, according to some embodiments. In the exemplary embodiment of fig. 9F, semiconductor die 520 is bonded over waveguide structure 910A, and photonic package 100 and photonic die 510 are bonded over waveguide structure 910B. The photonic package 100, the photonic die 510, and the semiconductor die 520 may be similar to the photonic package 100, the photonic die 510, and the semiconductor die 520 previously described, and the photonic package 100, the photonic die 510, and the semiconductor die 520 may be bonded using techniques similar to those previously described. For example, bonding may utilize a direct bonding process or may utilize conductive connections. A sealant 502 may be deposited over the assembly. Additionally, in some embodiments, the substrate 202 may be thinned to expose the vias 204, and conductive pads 530 may be formed on the backside of the substrate 202. The photonic structure 900 shown in fig. 9F is an example, and different numbers, arrangements, or configurations of waveguide structures 910 or components (e.g., dies, packages, or conductive parts) are also possible.

Advantages that embodiments may achieve. Embodiments described herein allow for the formation of photonic systems with improved yield, improved efficiency, improved signal fidelity, and reduced optical loss. By forming the nitride waveguide separately from the conductive wiring, the nitride waveguide can be annealed at a high temperature that can improve the quality of the nitride waveguide, but can damage the conductive wiring. For example, high temperature annealing of nitride waveguides can reduce optical losses and improve optical transmission and coupling characteristics. Thus, the benefits of high temperature annealing can be achieved without the risk of damaging other parts or components. In this way, components of the photonic system may communicate more efficiently and over longer distances using optical signals, which may improve operation, power consumption, and speed of the photonic system. For example, the transmitted optical signal may have less signal attenuation, less crosstalk, and less switching noise at high frequencies. Optical communications using the techniques described herein may allow for lower latency and higher bandwidth communications, may facilitate optical computation, or facilitate quantum computation.

According to an embodiment, a method includes forming a first redistribution structure on a first substrate; forming a waveguide structure on a second substrate, wherein the waveguide structure comprises a waveguide; bonding the waveguide structure to the first redistribution structure using a dielectric-to-dielectric bond; removing the second substrate; forming a second redistribution structure over the waveguide structure; and connecting the photonic package to the second redistribution structure, wherein the photonic package is optically coupled to the waveguide. In an embodiment, the method comprises performing a heat treatment process on the waveguide structure before bonding the waveguide structure to the first redistribution structure. In an embodiment, the heat treatment comprises an annealing temperature of greater than 1000 ℃. In an embodiment, the waveguide is a silicon nitride waveguide. In an embodiment, the second redistribution structure is electrically connected to the waveguide structure. In an embodiment, the method includes forming a through via in the first substrate, wherein the through via is electrically connected to the first redistribution structure. In an embodiment, the method includes connecting the first substrate to the interconnect substrate, wherein the through via is electrically connected to the interconnect substrate. In an embodiment, the photonic package is connected to the second redistribution structure by solder bumps.

According to an embodiment, a method includes forming a first interposer, the forming the first interposer including: forming a first waveguide over a first substrate; forming a first dielectric layer over the first waveguide; and annealing the first waveguide; bonding the first dielectric layer to the first redistribution structure; and connecting the die to the first interposer, wherein the die is electrically coupled to the first redistribution structure and optically coupled to the first waveguide. In an embodiment, forming the first interposer includes forming a second redistribution structure over the first waveguide. In an embodiment, the first redistribution structure comprises a second waveguide. In an embodiment, the first waveguide has a smaller optical transmission loss than the second waveguide. In an embodiment, the first waveguide comprises silicon nitride. In an embodiment, connecting the die to the first interposer includes bonding the die to the first interposer using dielectric-to-dielectric bonding and metal-to-metal bonding. In an embodiment, the method includes connecting a first interposer to an organic core substrate, wherein the first interposer is electrically connected to the organic core substrate. In an embodiment, the method includes connecting a second interposer to the organic core substrate, wherein the second interposer is electrically connected to the organic core substrate, wherein the second interposer is laterally adjacent to the first interposer.

According to an embodiment, a package includes an interconnect structure, wherein the interconnect structure includes: a first metallization layer on the substrate; a second metallization layer over the first metallization layer, wherein the second metallization layer is electrically connected to the first metallization layer; a waveguide layer sandwiched between the first metallization layer and the second metallization layer, the waveguide layer comprising at least one waveguide; and a bonding layer sandwiched between the first metallization layer and the waveguide layer; and a first device over the second metallization layer, wherein the first device comprises a photonic component optically coupled to the waveguide layer, wherein the first device is electrically connected to the second metallization layer. In an embodiment, the package includes a second device located above the second metallization layer and adjacent to the first device, wherein the second device is electrically connected to the second metallization layer. In an embodiment, the first device comprises a laser diode. In an embodiment, the waveguide layer and the substrate have coplanar sidewalls.

The foregoing outlines features of a drop-off embodiment so that those skilled in the art may better understand aspects of the present disclosure. Those skilled in the art should appreciate that they may readily use the present disclosure as a basis for designing or modifying other processes and structures for carrying out the same purposes and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art should also realize that such equivalent constructions do not depart from the spirit and scope of the present disclosure, and that they may make various changes, substitutions, and alterations herein without departing from the spirit and scope of the present disclosure.

Claims

1. A method of manufacturing a package, comprising:

Forming a first redistribution structure on a first substrate;

forming a waveguide structure on a second substrate, wherein the waveguide structure comprises a plurality of waveguides;

bonding the waveguide structure to the first redistribution structure using a dielectric-to-dielectric bond;

Removing the second substrate;

forming a second redistribution structure over the waveguide structure; and

And connecting a photonic package to the second redistribution structure, wherein the photonic package is optically coupled to the plurality of waveguides.

2. The method of claim 1, further comprising performing a heat treatment process on the waveguide structure prior to bonding the waveguide structure to the first redistribution structure.

3. The method of claim 2, wherein the heat treatment comprises an annealing temperature of greater than 1000 ℃.

4. The method of claim 1, wherein the plurality of waveguides are silicon nitride waveguides.

5. The method of claim 1, wherein the second redistribution structure is electrically connected to the waveguide structure.

6. The method of claim 1, further comprising forming a through via in the first substrate, wherein the through via is electrically connected to the first redistribution structure.

7. The method of claim 6, further comprising connecting the first substrate to an interconnect substrate, wherein the through via is electrically connected to the interconnect substrate.

8. The method of claim 1, wherein the photonic package is connected to the second redistribution structure by solder bumps.

9. A method of manufacturing a package, comprising:

forming a first interposer, comprising:

Forming a plurality of first waveguides over a first substrate;

Forming a first dielectric layer over the plurality of first waveguides; and

Annealing the plurality of first waveguides; and

Bonding the first dielectric layer to a first redistribution structure; and

A die is connected to the first interposer, wherein the die is electrically coupled to the first redistribution structure and optically coupled to the plurality of first waveguides.

10. A package, comprising:

an interconnect structure, wherein the interconnect structure comprises:

a first metallization layer on the substrate;

A second metallization layer over the first metallization layer, wherein the second metallization layer is electrically connected to the first metallization layer;

a waveguide layer sandwiched between the first metallization layer and the second metallization layer, the waveguide layer comprising at least one waveguide; and

A bonding layer sandwiched between the first metallization layer and the waveguide layer; and

A first device over the second metallization layer, wherein the first device comprises a photonic component optically coupled to the waveguide layer, wherein the first device is electrically connected to the second metallization layer.