CN118197391A - Techniques for analyzing and reporting accurate data to synchronize multiple signals in a memory chip - Google Patents

Abstract

A test and measurement system includes a multi-stack test subsystem including a plurality of test and measurement instruments, each instrument coupled to a Device Under Test (DUT) to receive a plurality of test signals from the DUT during a test mode of operation. One test and measurement instrument is designated as the master instrument and the rest are designated as extension test and measurement instruments. The master instrument transmits control signals to each of the expansion instruments to synchronize the test and measurement instruments to simultaneously acquire a plurality of test signals provided by the DUT. The automation engine is coupled to the multi-stack test subsystem to receive the acquired plurality of test signals from the host instrument and analyze the acquired test signals to perform a validation test on each of the plurality of test signals and simultaneously display results of the validation test on the plurality of test signals.

Description

Techniques for analyzing and reporting accurate data to synchronize multiple signals in a memory chip

Cross Reference to Related Applications

The present disclosure claims the benefit of indian patent application No. in202221072283 entitled "method and system for performing parallel processing of multiple data signals in a memory device" filed on 12/14 of 2022, the disclosure of which is incorporated herein by reference in its entirety.

Technical Field

The present disclosure relates generally to verification testing of integrated circuits or semiconductor chips, and more particularly to a method and system for synchronous parallel capture of signals from a Device Under Test (DUT) during verification testing.

Background

Electronic devices are widely used in industries such as automotive, industrial automation, telecommunications, and computer systems. Many of these electronic devices include some type of memory system to store firmware and software for system operation as well as for storing data (e.g., for data acquisition, data recording, and myriad other applications). These memory systems may include one or more of a variety of different types of memory devices, including Dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), and many variations of both core types of memory devices, such as Synchronous DRAM (SDRAM), double Data Rate (DDR) SDRAM, quad Data Rate (QDR) SRAM, and other types of memory that may be suitable for particular applications. Many of these memory devices, such as DDR SDRAM, utilize a data strobe signal (DQS) signal that is transmitted along with a data signal DQ during operation of the device. The transitions of the data strobe signal DQS and the data signals DQ are properly aligned to enable devices receiving the DQ signals to properly capture these signals during read and write operations. During a read operation, the DDR SDRAM provides DQS and DQ signals on the data bus at DDR SDRM, and another electronic device (e.g., a processor) coupled to the data bus captures the DQ signals using the DQS signal. During a write operation, the DDR SDRAM receives the DQS signal and the DQ signal being written from the processor and captures the received DQ signal with the DQS signal.

Testing of memory devices such as DDR SDRAM and other types of memory devices and other types of integrated circuits that utilize a data bus that includes the data strobe signal DQS and the data signal becomes complicated by the multiple data signals DQ that need to be acquired along with the data strobe signal DQS. The device under test, whether a memory device or other type of integrated circuit, may be referred to as a DUT in this specification. Existing test procedures typically capture or acquire the DQS signal at one time and capture or acquire one of the DQ signals. Thus, only one pair of signals, namely the DQS signal and one DQ signal, is acquired at a time, which increases the time required to test and verify the DQS signal and proper operation of all DQ signals. For example, current DDR SDRAM may include thirty-two (32) DQ signals. The test procedure may involve manually connecting selected DQ signals to test ports on a test and measurement instrument (e.g., an oscilloscope), further increasing the test time required and being prone to error in forming new interconnections with each data signal DQ. Variations in the DQS signal may occur during different occurrences of the generation of the signal, and thus such sequential methods of acquiring one of the currently generated DQS signal and the DQ signal may experience errors due to variations in the sequentially generated DQS signal. For example, variations in temperature, supply voltage, and other operating parameters may result in variations in the DQS signal that is sequentially generated during testing. Furthermore, while some current techniques may acquire more than one data signal DQ at a time along with the DQS signal, these techniques are limited and do not enable comprehensive verification testing as desired by users of these memory devices or other integrated circuits.

There is a need for improved techniques for verification testing of memory devices and other integrated circuits that overcome at least some of the above-described disadvantages experienced by conventional verification testing techniques.

Drawings

Aspects, features, and advantages of the examples of the present disclosure will become apparent from the following description of the examples with reference to the accompanying drawings in which:

Fig. 1 is a simplified functional block diagram of a test and measurement system including a multi-stack test subsystem including a plurality of test and measurement instruments synchronized to capture parallel signals from a Device Under Test (DUT) during a verification test of the DUT, according to some embodiments of the disclosure.

Fig. 2 is a sequence diagram illustrating the operation of components of the test and measurement system of fig. 1, according to some embodiments of the present disclosure.

FIG. 3 illustrates an example eye diagram of data signals and data strobe signals acquired by a multi-stack test subsystem and displayed by an automation engine of the test and measurement system of FIG. 1, according to some embodiments of the present disclosure.

Fig. 4A, 4B, and 4C are exploded eye diagrams of selected ones of the eye diagrams of fig. 3 to more clearly illustrate the eye diagram parameters calculated for each data signal captured from the DUT of fig. 1, in accordance with some embodiments of the present disclosure.

Fig. 5 illustrates a skewed eye diagram between each of a plurality of data signals captured from the DUT of fig. 1 and a data strobe signal, in accordance with some embodiments of the disclosure.

Fig. 6, 7 and 8 illustrate several exemplary graphical displays generated by the automation engine of the test and measurement system of fig. 1 that provide a user with simultaneous information regarding whether parameters calculated for data signals captured from DUTs pass or fail associated test criteria in accordance with some embodiments of the present disclosure.

It will be appreciated by those skilled in the art that any block diagrams herein represent conceptual views of illustrative methods embodying the principles of the disclosure. Similarly, it will be appreciated that any flow charts, flow diagrams, and the like represent various processes which may be substantially represented in computer readable media and so executed by a computer or processor, whether or not such computer or processor is explicitly shown.

Detailed Description

Embodiments of the present disclosure utilize synchronized multiple test and measurement instruments to capture or acquire multiple test signals in parallel from a DUT and analyze the acquired test signals to perform verification tests on the DUT and display the results of the analysis to a user. These test signals may be, for example, data signals DQ and data strobe signals DQs of a memory device such as DDR SDRAM. In this way, methods and systems according to embodiments of the present disclosure enable a user to see, for each data signal of interest in a DUT, a state indicating whether the data signal has passed or failed the corresponding verification test. This simplifies the testing process for the user, eliminates the need for sequential acquisition of the data signals of interest and errors that such sequential acquisition may introduce, and eliminates the need for manual reconfiguration of the test system and the accompanying errors that may result. The user can see if a given DUT passes the verification test in a single test cycle of the DUT, where a test cycle is the time during which the system acquires test signals from the DUT, analyzes those acquired signals, and displays the analysis results to the user. This reduces the time required to test the DUT. However, a user may perform multiple test cycles on a given DUT and take action to compensate or adjust the characteristics of individual test signals that failed the verification test. After taking appropriate corrective actions, the user may again perform verification tests on the DUT to see if those actions correct one or more test signals that did not initially pass the verification tests.

FIG. 1 is a simplified functional block diagram of a test and measurement system 100 including a multi-stack test subsystem 102, the multi-stack test subsystem 102 including a plurality of test and measurement instruments 104A-104D that are synchronized to capture parallel test signals from a Device Under Test (DUT) during a verification test, in accordance with some embodiments of the present disclosure. The multi-stack test subsystem includes N test and measurement instruments 104A-D, where n=4 in the example embodiment of fig. 1. Other embodiments of the system 100 may include more or fewer test and measurement instruments 104A-N (i.e., N < 4 or N > 4). Each of the test and measurement instruments 104 may be, for example, an oscilloscope, and is configured to be coupled to the DUT 106 to receive a plurality of test signals from the DUT during a test mode of operation. In the example embodiment of FIG. 1, DUT 106 is a test board that includes one or more DDR SDRAMs and the test signals received by test and measurement instruments 104A-D include data signals DQ0-DQ14 and data strobe signal DQS. In some embodiments, the DUT 106 may include different types of memory devices and the test signals provided to the test and measurement instruments 104A-D may include different signals from one or more DDR SDRAM of the DUT. For example, in some embodiments, the test signals from the DDR SDRAM of the DUT 106 include a command address signal CA and a chip select signal CS.

One of the test and measurement instruments 104A-D is designated as the master test and measurement instrument, while the remainder of the test and measurement instruments are designated as extension test and measurement instruments. The test and measurement instrument 104A is the master instrument and the test and measurement instruments 104B-D are extensions in the test and measurement system 100. The designation as a master instrument or an extension instrument configures each of the test and measurement instruments 104A-D to be a master or extension test and measurement instrument, respectively. The test and measurement instruments 104A-D designated as master instruments, i.e., test and test instrument 104A in FIG. 1, are configured to transmit control signals to each of the expansion test and measurement instruments 104B-D to synchronize all of the test and measurement instruments to simultaneously acquire DQS and DQ0-DQ14 signals provided by the DUT 106.

Communication between the main test and measurement instrument 104A and each of the extended test and measurement instruments 104B-D occurs through a communication link 107 in the test and measurement system 100. In some embodiments, communication link 107 is a UltraSync multi-element time synchronization bus of Tektronix. The master test and measurement instrument 104A transmits control signals from the master instrument to each of the extension test and measurement instruments 104B-D over the communication link 107 to synchronize all of the instruments. In some embodiments of test and measurement system 100, master test and measurement instrument 104A provides a sample clock signal over communication link 107 for use by each of test and measurement instruments 104A-D in synchronizing the simultaneous acquisition of DQS and DQ signals provided by DUT 106. The master test and measurement instrument 107 also provides trigger signals to control the start and stop of the test cycle, i.e., the acquisition of DQS and DQ signals by the test and measurement instruments 104A-D. The main test and measurement instrument also controls the transmission of data from each of the extension test and measurement instruments 104B-D to the main test and test instrument via the communication link 107. The data transmitted over the communication link 107 for each of the extended test and measurement instruments corresponds to the data of the DQ0-DQ14 signals acquired by the extended test and test instruments 104B-D.

Once the test and measurement instruments 104A-D have acquired DQS and DQ0-DQ14 signals from the DUT 106 during the current test cycle of the test and measurement system 100, each of the extended test and measurement instruments 104B-D provides a corresponding subset of DQS and DQ0-DQ14 signals to the main test and measurement instrument 104A. The master test and measurement instrument 104A aggregates the acquired DQ3-14 signals received from the expansion test and measurement instruments 104B-D and DQS and DQ0-2 signals acquired by the master test and measurement instrument and provides these aggregated acquired signals to an automation engine 108 coupled to the multi-stack test subsystem 102. Upon receiving the acquired DQS and DQ0-DQ14 signals from the test and measurement instrument 104A, the automation engine 108 is configured to analyze the acquired DQS and DQ0-DQ14 signals to perform a validation test on each of these signals and thereafter display the results of the validation test on these signals simultaneously. The user may view these display results provided by the automation engine 108 and immediately determine whether the DUT 106 has passed or failed the verification test and identify which, if any, of the DQS and DQ0-DQ14 signals failed the test.

The automation engine 108 executes an analysis algorithm 110 to analyze the acquired DQS and DQ0-DQ14 signals. In different embodiments of the test and measurement system 100, the particular analysis algorithm 110 executed by the automation engine 108 to analyze the acquired DQS and DQ0-DQ14 signals may vary. The user may view these concurrently displayed results provided by the automation engine 108 to determine whether each of the DQS and DQ0-DQ14 signals of the DUT 106 have passed or failed the validation test and may also view the various parameters calculated by the analysis algorithm 110 for each of these signals. For example, the automation engine 108 may execute the analysis algorithm 110 to generate an eye pattern for each of the acquired DQS and DQ0-DQ14 signals, and may also determine an eye height, an eye width, and a mask for the generated eye pattern for each of these signals. In embodiments of the present disclosure, the automation engine 108 may be implemented using one or more processors, and in various implementations, the one or more processors may reside on one or more of the plurality of test and measurement instruments 104A-D, or may reside on one or more external computing devices including cloud-based processors, or may be distributed between one or more of the plurality of test and measurement instruments 104A-D and the one or more external computing devices.

Fig. 2 is a sequence diagram illustrating a sequence of operation of components of the test and measurement system 100 of fig. 1, according to some embodiments of the present disclosure. The overall operation of the test and measurement system 100 according to some embodiments of the present disclosure will now be described in more detail with reference to fig. 1 and 2. To begin a test cycle of the DUT 106, the DUT is placed in a verification test mode of operation. This is not explicitly shown in fig. 2 and will vary depending on the type of DUT 106 being tested. In the case where the DUT is DDR SDRAM, the verification test mode of placing the device in operation will be understood by those skilled in the art, and therefore details are not described herein. Briefly, in DDR SDRAM, a typical memory access operation includes an activate command to access a particular row in a particular bank in a memory device, and address bits associated with a read or write command identify a starting column for burst data transfers from memory cells in the active row. Each burst in the burst data transfer is provided as a corresponding data word on the data bus data signals DQ0-DQ14, and the DQs signal is provided along with the data signals to enable devices receiving the data signals to properly capture or acquire the signals. The DQS signal is used as a differential "burst clock" and is provided along with the data signals DQ0-DQ14 on the data bus during read and write operations. Data is transferred on both the rising and falling edges of the DQS signal, and thus twice per cycle of DQS, and thus is a Double Data Rate (DDR) designation.

DDR SDRAM has a data bus that typically includes 8, 16, or 32 data signals DQ. DQ0-DQ14 of DUT 106 are used by way of example in this specification and represent an example embodiment in which DUT 106 is a DDR SDRAM having a 16-bit data bus that carries data signals DQ0-DQ 15. Each of the test and measurement instruments 104A-104D has four input test ports, which is true for many conventional oscilloscopes. Each test port on the test and measurement instruments 104A-D is configured to couple to a test point on the DUT 106 to obtain a test signal provided to the DUT at the test point. The DQS signal plus fifteen DQ signals DQ0-DQ14 equals sixteen test signals, which is the number of test ports available on the four test and measurement instruments 104A-104D. Such a configuration of DUT 106 is provided by way of example only, and in further embodiments of the present disclosure, other configurations may include more or fewer data signals DQ and more or fewer test and measurement instruments 104, or test and measurement instruments including more or fewer test ports.

When placed in a verify test mode of operation, DUT 106 begins to provide a test data pattern for each of the DQ0-DQ14 signals along with the DQS signal. The frequency of the DQS signal is typically the same as the frequency of the clock signal provided to the memory device. Typically, the test data pattern for each of the DQ0-DQ14 signals is a series of alternating logic 0 and logic 1 (e.g., 1010101010 …), or some other pseudo-random bit sequence. At operation 200 in fig. 2, the automation engine 108 sends an acquisition request to the primary test and measurement instrument 104A to initiate a test cycle. In response to the acquisition request, the master test and measurement instrument 104A sends an acquisition instruction to the extension test and measurement instruments 104B, 104C, and 104D in operation 202. In response to the get request from the automation engine 108 and the get instructions provided by the master test and measurement instrument 104A to the expansion test and measurement instruments 104B-D, each of the master and expansion test and test instruments 104A-D gets the corresponding DQS and DQ0-DQ14 signals provided by the DUT 106 in operations 202-208. At operation 210, each test and measurement instrument saves data of the corresponding acquired DQS and DQ0-DQ14 signals to a data memory, which represents a storage of the corresponding signals acquired by each of the test and measurement instruments 104A-D.

After storing the corresponding acquired DQS and DQ signals, each of the expansion test and measurement instruments 104B-D provides a response to the main test and measurement instrument 104A including data corresponding to the acquired signals of the expansion test and measurement instrument. The master test and measurement instrument 104A then aggregates the responses from the expansion test and measurement instruments 104B-D along with data corresponding to the acquired DQS and DQ0-2 signals acquired by the master test and test instrument 104A, which corresponds to the data of the acquired DQ3-14 signals. These aggregated responses from all of the test and measurement instruments 104A-D are then provided to the agent at operation 212. The agent may be considered a component of the automation engine 108 of fig. 1 whose functionality facilitates the transfer of aggregated responses from the primary test and measurement instrument 104A and the provision of these aggregated responses to the automation engine 108. In the automation engine 108, the aggregated responses are provided to an analysis algorithm 110 for analysis to perform validation testing of the acquired DQS and DQ signals.

FIG. 3 illustrates example eye diagrams of data signals DQ0-7 and data strobe signal DQS acquired by multi-stack test subsystem 102 and displayed by automation engine 108 of test and measurement system 100 of FIG. 1, according to some embodiments of the present disclosure. In fig. 3, only the eye diagrams of the data signals DQ0 through DQ7 are shown, and only the data signals DQ8 through DQ14 are omitted for simplicity of the drawing. The eye diagram shows the voltage of each signal along the vertical axis and the time along the horizontal axis. These eye diagrams are examples of displays generated by the automation engine 108 of FIG. 1 that provide the user with simultaneous information regarding the validation test results of DQ0-DQ7 and DQS signals acquired from the DUT 106 during the validation test. Fig. 3 shows the eye pattern of each of the data signals DQ0-DQ7 and the eye mask of each of these signals, and also shows the eye pattern of the DQs signal. An eye diagram is created by repeatedly acquiring digital signals over a plurality of time intervals and then superimposing multiple acquisitions of these digital signals. The eye mask defines an acceptable boundary of the eye pattern and effectively shows a "no allowed area" so that verification of the signal fails if any portion of the eye pattern is present in the eye mask. Eye patterns and eye shields for digital signals are well understood by those of skill in the art and are therefore not described in detail herein.

In the upper left corner of fig. 3, an eye diagram 300 for the DQ0 signal and an eye mask 302 for DQ0 are shown, and an eye diagram 304 for the DQs signal is also shown. Only the eye patterns 300, 304 and eye patch 302 (RxMask) of the data signal DQ0 are labeled in fig. 3 to simplify the drawing. The display of these eye diagrams provides the user with a visual representation of the validation test results of each DQ0-7 signal and DQS signal being tested, allowing the user to more carefully examine the characteristics of each of these signals and examine the cause of any signal failure, e.g., a portion of eye diagram 300 of the DQ0 signal is present in eye mask 302. There is no failure in any of the eye diagrams shown in fig. 3. Fig. 3 also shows the eye patterns of the data signals DQ0-7 and the eye pattern of the DQs signal, and shows the eye height parameter EH for each of these eye patterns. Fig. 3 also shows the eye patterns of the data signals DQ0-7 and the eye pattern of the DQs signal, and shows the eye width parameter EW for each of these eye patterns. In some embodiments, the automation engine 108 may generate separate displays showing eye diagrams for each of the DQ0-7 signals showing the eye mask 302 (RxMask), eye height parameter EH, and eye width parameter EW.

Fig. 4A-4C are exploded eye diagrams of selected ones of the eye diagrams of fig. 3 to more clearly illustrate the eye diagram parameters that may be calculated by the analysis algorithm 110 of the automation engine 108 for each of the DQ0-DQ14 and DQs signals captured from the DUT 106 of fig. 1, in accordance with some embodiments of the present disclosure. Fig. 4A-4C specifically show eye diagrams of DQ0 signals. Again, these eye diagrams show the voltage of each signal along the vertical axis and the time along the horizontal axis. Fig. 4A shows an eye diagram 400 of the DQ0 signal and an eye diagram 402 of the DQs signal. The eye height EH parameter of eye diagram 400 is shown and gives a range between the lowest and highest measured voltages of the open eye of the DQ0 signal, where the open eye of the signal is defined by the vertical eye height EH parameter and the horizontal eye width EW parameter as shown in fig. 4B. Fig. 4B shows an eye pattern 400 of the DQ0 signal and an eye pattern 402 of the DQs signal, and the eye width EW of the eye pattern 400 shows the open eye duration of the eye pattern. Fig. 4C shows eye mask EM (i.e., rxMask) of eye pattern 400, which effectively corresponds to the forbidden region in eye pattern 400 of DQ0 signals, as described above. If any portion of eye diagram 400 exists in eye mask EM, verification of the DQ0 signal fails.

FIG. 5 shows eye diagrams 500-DQ0 through 500-DQ7 for each of the DQ0-DQ7 signals, and eye diagrams (labeled only in the top graph) for DQS signal 502. For simplicity of the drawing, only DQ0-DQ7 signals are shown, not all DQ0-DQ14. In each of the graphs of fig. 5, voltage is indicated on the vertical axis and time is indicated on the horizontal axis. FIG. 5 illustrates skew between the DQS signal and each of the eye diagrams 500-DQ0 through 500-DQ7 to enable a worst case skew to be identified. The transitions of the DQS signal are indicated by vertical lines 504 in FIG. 5, and the skew of each DQ0-DQ7 signal is defined by the time difference between the time at vertical line 504 and the transition of the corresponding DQ0-DQ7 signal, as indicated in the corresponding eye diagrams 500-DQ0 through 500-DQ 7. In this example, the worst case skew occurs between the DQS signal and eye diagram 500-DQ6, while the shortest skew occurs with eye diagram 500-DQ 2. In some embodiments, the analysis algorithm 110 executed by the automation engine 108 of fig. 1 also calculates a skew offset, defined as the magnitude of the difference between the shortest skew and the longest skew. Again, the display of eye diagrams 500-DQ0 through 500-DQ7 allows the user to view the validation test results of all DQ and DQs signals from DUT 106 simultaneously and to quickly evaluate the validation test results based on these visual presentations.

Fig. 6-8 illustrate several exemplary graphical displays generated by the automation engine 108 of fig. 1 in executing the analysis algorithm 110 in accordance with some embodiments of the present disclosure. These graphical displays are provided by way of example to illustrate the types of validation test information that automation engine 108 may provide to a user to visually indicate whether parameters calculated for DQS and DQ0-DQ14 signals captured from DUT 106 pass or fail the associated test criteria analyzed by analysis algorithm 110. Fig. 6 shows the input voltage swing VIHLAc of the DQ signal, the high value TdiPW _high of the input pulse width and the low value diPW _low of the input pulse width of the DQ signal, and the slew rate SRIN-diVW _rise of the rising edge of the DQ signal. Fig. 7 and 8 show tables showing skew values calculated between individual ones of the DQ signals and the DQs signal as discussed above with respect to fig. 5. Fig. 7 shows skew values in picoseconds in the second column of DQ0-DQ5 signals. Fig. 8 shows skew values of DQ3-DQ7 signals. When comparing the skew values shown in the tables of fig. 7 and 8, it can be seen that the DQ6 signal exhibits a maximum skew value of 601.64087676 picoseconds (ps). The shortest skew value of 560.77103533ps for DQ2 is shown in FIG. 5. A skew offset parameter tDQ DQ that is equal to 40.8698414ps is shown in fig. 8, and corresponds to the magnitude of the difference between the shortest skew value and the longest skew value (i.e., (601.64087676 ps-560.77103533 ps) = 40.8698414 ps).

Aspects of the disclosure may operate on specifically created hardware, firmware, digital signal processors, or specifically programmed general-purpose computers including processors operating in accordance with programmed instructions. The term controller or processor as used herein is intended to include microprocessors, microcomputers, application Specific Integrated Circuits (ASICs), and special purpose hardware controllers. One or more aspects of the present disclosure can be embodied in computer-usable data and computer-executable instructions, for example, in one or more program modules that are executed by one or more computers (including monitoring modules) or other devices. Generally, program modules include routines, programs, objects, components, data structures, etc. that perform particular tasks or implement particular abstract data types when executed by a processor in a computer or other device. The computer-executable instructions may be stored on a non-transitory computer-readable medium such as a hard disk, an optical disk, a removable storage medium, a solid state memory, a Random Access Memory (RAM), and the like. As will be appreciated by one of skill in the art, the functionality of the program modules may be combined or distributed as desired in various aspects. Furthermore, the functionality may be embodied in whole or in part in firmware or hardware equivalents such as integrated circuits, FPGAs, and the like. Particular data structures may be used to more effectively implement one or more aspects of the present disclosure, and such data structures are contemplated within the scope of the computer-executable instructions and computer-usable data described herein.

In some cases, the disclosed aspects may be implemented in hardware, firmware, software, or any combination thereof. The disclosed aspects may also be implemented as instructions carried by or stored on one or more non-transitory computer-readable media, which may be read and executed by one or more processors. Such instructions may be referred to as a computer program product. As discussed herein, computer-readable media refers to any medium that can be accessed by a computing device. By way of example, and not limitation, computer readable media may comprise computer storage media and communication media.

Computer storage media refers to any medium that can be used to store computer readable information. By way of example, and not limitation, computer storage media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), flash memory or other memory technology, compact disk read-only memory (CD-ROM), digital Video Disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, and any other volatile or non-volatile, removable or non-removable media implemented in any technology. Computer storage media does not include signals themselves and transitional forms of signal transmission.

Communication media refers to any medium that can be used for communication of computer readable information. By way of example, and not limitation, communication media may include coaxial cables, fiber optic cables, air, or any other medium suitable for the communication of electrical, optical, radio Frequency (RF), infrared, acoustic, or other types of signals.

Example

Illustrative examples of the technology disclosed herein are provided below. Configurations of techniques may include any one or more of the examples described below, as well as any combination of these examples.

Example 1 is a method for testing a Device Under Test (DUT) in a test and measurement system. The method includes placing a DUT in a test mode of operation, the DUT providing a plurality of test signals during operation in the test mode, synchronizing a plurality of test and measurement instruments, each of the plurality of test and measurement instruments coupled to the DUT to receive a selected one of the plurality of test signals, simultaneously acquiring the plurality of test signals provided by the DUT by the synchronized plurality of test and measurement instruments, analyzing the acquired plurality of test signals to perform a verification test on each of the plurality of test signals, and simultaneously displaying results of the verification test on each of the plurality of test signals.

Example 2 is the method of example 1, wherein the test signal includes a plurality of data signals and a data strobe signal.

Example 3 is the method of example 1, wherein the test signal includes a plurality of command address signals and a chip select signal.

Example 4 is a method according to any of the preceding example methods, wherein the DUT is a Double Data Rate (DDR) memory.

Example 5 is a method according to any one of the preceding example methods, wherein each of the plurality of test and measurement instruments comprises an oscilloscope.

Example 6 is a method according to any one of the preceding examples, wherein simultaneously acquiring, by the plurality of test and measurement systems, the plurality of test signals provided by the DUT further comprises generating an eye pattern for each of the plurality of test signals.

Example 7 is a method according to any one of the preceding example methods, wherein analyzing the acquired plurality of test signals further comprises determining an eye height, an eye width, and a mask of the generated eye pattern for each of the plurality of test signals.

Example 8 is a method according to any one of the preceding example methods, wherein concurrently displaying the results of the verification test further comprises displaying the generated eye pattern for each of the plurality of test signals and the determined eye height, eye width, and mask.

Example 9 is a method according to any one of the preceding examples, wherein concurrently displaying the results of the verification test further comprises displaying an indication of whether the test signal waveform passed or failed the verification test for the plurality of test signals.

Example 10 is a method according to any one of the preceding example methods, wherein synchronizing the plurality of test and measurement instruments includes designating one of the plurality of test and measurement instruments as a master test and measurement instrument and the remainder of the plurality of test and measurement instruments as extended test and measurement instruments, and transmitting control signals from the master test and measurement instrument to each of the plurality of extended test and measurement instruments to control simultaneous acquisition of a plurality of test signals provided by the DUT.

Example 11 is the method of example 10, wherein transmitting the control signal from the main test and measurement instrument to each of the plurality of extended test and measurement instruments includes providing, by the main test and measurement instrument, a sample clock signal for synchronizing acquisition of the plurality of test signals provided by the DUT by the plurality of test and measurement instruments simultaneously, providing a trigger signal to control start and stop of acquisition of the plurality of test signals by the plurality of test and measurement instruments, and controlling transmission of data from each of the plurality of extended test and measurement instruments to the main test and measurement instrument, the transmitted data of each of the plurality of extended test and measurement instruments corresponding to the data of the plurality of test signals acquired by the extended test and measurement instruments.

Example 12 is the test and measurement system of example 11, comprising a multi-stack test subsystem including a plurality of test and measurement instruments, each of the plurality of test and measurement instruments configured to be coupled to a Device Under Test (DUT) to receive a plurality of test signals from the DUT during a test mode of operation, one of the plurality of test and measurement instruments designated as a master test and measurement instrument and a remaining portion of the plurality of test and measurement instruments designated as an extended test and measurement instrument, the master test and measurement instrument configured to transmit control signals to each of the plurality of extended test and measurement instruments to synchronize the plurality of test and measurement instruments to simultaneously acquire a plurality of test signals provided by the DUT, and an automation engine coupled to the multi-stack test subsystem to receive the acquired plurality of test signals from the master instrument of the plurality of test and measurement instruments, the automation engine configured to analyze the acquired plurality of test signals to simultaneously verify the plurality of test signals to each of the plurality of test and test results.

Example 13 is the test and measurement system of example 12, wherein the DUT is a Double Data Rate (DDR) memory.

Example 14 is the test and measurement system of example 13, wherein the test signal includes a plurality of data signals and a data strobe signal.

Example 15 is the test and measurement system of example 13, wherein the test signal includes a plurality of command address signals and a chip select signal.

Example 16 is a test and measurement system according to any one of the preceding examples, wherein each of the plurality of test and measurement instruments includes an oscilloscope.

Example 17 is a test and measurement system according to any one of the preceding examples, wherein the automation engine is configured to generate an eye pattern for each of the acquired plurality of test signals.

Example 18 is a test and measurement system according to any one of the preceding examples, wherein the automation engine is configured to determine eye heights, eye widths, and masks of eye patterns of the generated plurality of test signals.

Example 19 is a test and measurement system comprising a multi-stack test subsystem, the multi-stack test subsystem comprising a plurality of extended test and measurement instruments, each test and measurement instrument configured to be coupled to a Device Under Test (DUT) to receive a plurality of test signals from the DUT during a verification test mode of operation, a master test and measurement instrument coupled to the plurality of extended test and measurement instruments, the master test and test instrument configured to be coupled to the DUT to receive a plurality of test signals from the DUT during the verification test mode of operation, and the master test and measurement instrument further configured to transmit control signals to each of the plurality of extended test and measurement instruments to synchronize the plurality of test and measurement instruments to simultaneously acquire a plurality of test signals provided by the DUT, and an automation engine coupled to the multi-stack test subsystem to receive the acquired plurality of test signals from the master instrument of the plurality of test and measurement instruments, the automation engine configured to analyze the acquired plurality of test signals to perform the verification test on each of the plurality of test signals and to simultaneously display the verification test results of the plurality of test signals.

Example 20 is the test and measurement system of example 19, wherein the master test and measurement instrument is configured to transmit control signals including sample clock signals for synchronizing the simultaneous acquisition of multiple test signals provided by the DUT by the multiple test and measurement instruments; a trigger signal for controlling the start and stop of the acquisition of a plurality of test signals by the plurality of test and measurement instruments; and a signal for controlling data transmission from each of the plurality of extended test and measurement instruments to the main test and measurement instrument, the transmitted data of each of the plurality of extended test and measurement instruments corresponding to data of a plurality of test signals acquired by the extended test and measurement instrument.

The above description is presented only to illustrate example embodiments of the disclosure and is not intended to be limiting. Since modifications of the disclosed embodiments incorporating the teachings herein may occur to persons skilled in the art, the disclosure should be interpreted to include all aspects within the scope of the disclosure.

The previously described versions of the disclosed subject matter have many advantages that are described or will be apparent to one of ordinary skill. Even so, such advantages or features are not all required in all versions of the disclosed apparatus, systems or methods.

Furthermore, this written description references specific features. It should be understood that all of the features disclosed in the specification, including the claims, abstract and drawings, and all of the steps in any method or process so disclosed, may be combined in any combination, except combinations where at least some of such features and/or steps are mutually exclusive. Each feature disclosed in this specification, including the claims, abstract and drawings, may be replaced by alternative features serving the same, equivalent or similar purpose, unless expressly stated otherwise.

Furthermore, when a method having two or more defined steps or operations is referred to in the present application, the defined steps and operations may be performed in any order or simultaneously unless the context excludes these possibilities.

Although specific examples of the disclosure have been illustrated and described for purposes of description, it will be appreciated that various modifications may be made without departing from the spirit and scope of the disclosure. Accordingly, the disclosure should not be limited except as by the appended claims.

Claims (20)

1. A method for testing a Device Under Test (DUT) in a test and measurement system, comprising:

placing the DUT in a test mode of operation, the DUT providing a plurality of test signals during operation in the test mode;

Synchronizing a plurality of test and measurement instruments, each of the plurality of test and measurement instruments coupled to the DUT to receive a selected one of the plurality of test signals;

simultaneously acquiring, by the synchronized plurality of test and measurement instruments, the plurality of test signals provided by the DUT;

analyzing the acquired plurality of test signals to perform a verification test on each of the plurality of test signals; and

While displaying the results of the verification test for each of the plurality of test signals.

2. The method of claim 1, wherein the test signal comprises a plurality of data signals and a data strobe signal.

3. The method of claim 1, wherein the test signals comprise a plurality of command address signals and chip select signals.

4. The method of claim 1, wherein the DUT is a Double Data Rate (DDR) memory.

5. The method of claim 1, wherein each of the plurality of test and measurement instruments comprises an oscilloscope.

6. The method of claim 1, wherein simultaneously acquiring, by the plurality of test and measurement systems, the plurality of test signals provided by the DUT further comprises generating an eye pattern for each of the plurality of test signals.

7. The method of claim 6, wherein analyzing the acquired plurality of test signals further comprises determining an eye height, an eye width, and a mask of the generated eye pattern for each of the plurality of test signals.

8. The method of claim 7, wherein concurrently displaying the results of the verification test further comprises displaying the generated eye pattern and eye height, eye width, and mask determined for each of the plurality of test signals.

9. The method of claim 1, wherein simultaneously displaying results of the verification test further comprises displaying an indication of whether the test signal waveform has passed or failed the verification test for the plurality of test signals.

10. The method of claim 1, wherein synchronizing the plurality of test and measurement instruments comprises:

Designating one of the plurality of test and measurement instruments as a master test and measurement instrument and designating the remaining portion of the plurality of test and measurement instruments as an extension test and measurement instrument; and

Control signals are communicated from the main test and measurement instrument to each of the plurality of extended test and measurement instruments to control the simultaneous acquisition of the plurality of test signals provided by the DUT.

11. The method of claim 10, wherein transmitting control signals from the main test and measurement instrument to each of the plurality of extended test and measurement instruments comprises:

Providing, by the master test and measurement instrument, a sample clock signal for synchronizing the simultaneous acquisition by the plurality of test and measurement instruments of a plurality of test signals provided by the DUT;

providing a trigger signal to control the plurality of test and measurement instruments to acquire the start and stop of the plurality of test signals; and

Controlling transmission of data from each of the plurality of extended test and measurement instruments to the main test and measurement instrument, the transmitted data for each of the plurality of extended test and measurement instruments corresponding to data of the plurality of test signals acquired by the extended test and measurement instrument.

12. A test and measurement system comprising:

A multi-stack test subsystem comprising a plurality of test and measurement instruments, each of the plurality of test and measurement instruments configured to be coupled to a Device Under Test (DUT) to receive a plurality of test signals from the DUT during a test mode of operation, one of the plurality of test and measurement instruments designated as a master test and measurement instrument and the remainder of the plurality of test and measurement instruments designated as an extension test and measurement instrument, the master test and measurement instrument configured to transmit control signals to each of the plurality of extension test and measurement instruments to synchronize the plurality of test and measurement instruments to simultaneously acquire the plurality of test signals provided by the DUT; and

An automation engine coupled to the multi-stack test subsystem to receive the acquired plurality of test signals from the master of the plurality of test and measurement instruments, the automation engine configured to analyze the acquired plurality of test signals to perform a verification test on each of the plurality of test signals and simultaneously display results of the verification test on the plurality of test signals.

13. The test and measurement system of claim 12, wherein the DUT is a Double Data Rate (DDR) memory.

14. The test and measurement system of claim 13, wherein the test signal comprises a plurality of data signals and a data strobe signal.

15. The test and measurement system of claim 13, wherein the test signals include a plurality of command address signals and chip select signals.

16. The test and measurement system of claim 12, wherein each of the plurality of test and measurement instruments comprises an oscilloscope.

17. The test and measurement system of claim 12, wherein the automation engine is configured to generate an eye pattern for each of the acquired plurality of test signals.

18. The test and measurement system of claim 17, wherein the automation engine is configured to determine eye heights, eye widths, and masks for the generated eye patterns of the plurality of test signals.

19. A test and measurement system comprising:

A multi-stack test subsystem comprising:

A plurality of extended test and measurement instruments, each configured to be coupled to a Device Under Test (DUT) to receive a plurality of test signals from the DUT during a verification test mode of operation;

A main test and measurement instrument coupled to the plurality of extended test and measurement instruments, the main test and measurement instrument configured to be coupled to the DUT to receive a plurality of test signals from the DUT during a verification test mode of operation, and the main test and measurement instrument further configured to transmit control signals to each of the plurality of extended test and measurement instruments to synchronize the plurality of test and measurement instruments to simultaneously acquire the plurality of test signals provided by the DUT; and

An automation engine coupled to the multi-stack test subsystem to receive the acquired plurality of test signals from the master of the plurality of test and measurement instruments, the automation engine configured to analyze the acquired plurality of test signals to perform a verification test on each of the plurality of test signals and simultaneously display results of the verification test on the plurality of test signals.

20. The test and measurement system of claim 19, wherein the primary test and measurement instrument is configured to transmit control signals comprising:

A sample clock signal for synchronizing the simultaneous acquisition of a plurality of test signals provided by the DUT by the plurality of test and measurement instruments;

a trigger signal for controlling the start and stop of the acquisition of the plurality of test signals by the plurality of test and measurement instruments; and

A signal for controlling data transmission from each of the plurality of extended test and measurement instruments to the main test and measurement instrument, the transmitted data of each of the plurality of extended test and measurement instruments corresponding to data of a plurality of test signals acquired by the extended test and measurement instrument.