CN118171615A

CN118171615A - Method and system for remapping local circuits in FPGA layout stage

Info

Publication number: CN118171615A
Application number: CN202410375037.6A
Authority: CN
Inventors: 耿孝谨; 葛坤峰; 刘榜
Original assignee: Shanghai Anlu Information Technology Co ltd
Current assignee: Shanghai Anlu Information Technology Co ltd
Priority date: 2024-03-29
Filing date: 2024-03-29
Publication date: 2024-06-11

Abstract

The application relates to FPGA logic synthesis and layout design technology, and discloses a method and a system for remapping local circuits in an FPGA layout stage, wherein the method comprises the following steps: according to the problem that the logic level is too high or the local utilization rate is too high in the circuit observed in the layout stage, sub-circuits are selected to be extracted based on the corresponding specific rules; remapping the extracted sub-circuits, firstly scattering the lookup table structure of the sub-circuits into a gate-level netlist, and then selecting a corresponding remapping strategy according to excessively high logic level or excessively high utilization rate to obtain a remapped optimized sub-circuit; and performing incremental layout on the sub-circuits after the remapping, determining the initial positions of key devices of the sub-circuits by using the positions of boundary ports of the original circuits, and calling a layout device to only layout the devices in the sub-circuits. The application can realize the rapid and targeted circuit optimization in the layout stage, improves the mapping effect, improves the circuit performance and has important technical progress significance.

Description

Method and system for remapping local circuits in FPGA layout stage

Technical Field

The application relates to the technical field of integrated circuit design automation, in particular to an FPGA logic synthesis and layout design technology.

Background

The FPGA automatic design flow can be divided into two main stages of logic synthesis and physical realization. The final step of logic synthesis is to map the synthesized circuit netlist onto hardware resources supported by the chip, after this step is completed, the physical implementation stage will begin, responsible for laying out the mapped devices to legal locations of the chip, and completing the wiring connection. In the logic synthesis stage, the circuit is mapped into a netlist capable of being placed at one time, and the mapping quality directly determines the performance index after physical implementation. The ideal mapping result should use the minimum logic resource to achieve the shortest logic level, so as to reduce the chip energy consumption and increase the working frequency, but the balance between the logic resource and the logic level needs to be maintained.

As FPGA circuit designs become more complex, circuit mapping faces higher challenges, especially when supporting circuit designs of millions of look-up table sizes. The traditional mapping method globally processes the whole circuit to strive for an equalization result, but once the mapping is completed, the locally adjusted space is limited. Common problems during layout stages include excessive logic levels in local circuits or excessive local area densities, which can degrade layout quality and thus affect circuit performance. Conventional solutions include adjusting logic synthesis strategies to improve sub-circuits, or adjusting layout strategies to optimize the layout of the problem sub-circuits, in the face of mapping problems that can only be discovered during the layout phase. For example, if the logic level of a module is too high, the logic level may be reduced by logic synthesis adjustment attempts or its physical location may be optimized during layout. However, these conventional solutions often have difficulty in quickly improving the problem circuit without significantly affecting the overall design.

Disclosure of Invention

The application aims to provide a method and a system for remapping local circuits in an FPGA layout stage, so as to solve the problems in the background art.

The application discloses a method for remapping local circuits in an FPGA layout stage, which comprises the following steps:

extracting: according to the problem that the logic level is too high or the local utilization rate is too high in the circuit observed in the layout stage, sub-circuits are selected to be extracted based on the corresponding specific rules;

A remapping step: remapping the extracted sub-circuits, firstly scattering the lookup table structure of the sub-circuits into a gate-level netlist, and then selecting a corresponding remapping strategy according to excessively high logic level or excessively high utilization rate to obtain a remapped optimized sub-circuit;

Incremental layout step: and performing incremental layout on the sub-circuits after the remapping, determining the initial positions of key devices of the sub-circuits by using the positions of boundary ports of the original circuits, and calling a layout device to only layout the devices in the sub-circuits.

In a preferred embodiment, the specific rule corresponding to the rule is specifically:

If the logic level is too high, expanding based on the combination logic of the key time sequence path;

If the utilization rate is too high, expanding based on the combination logic in the region;

the expansion is performed by a lookup table connected by combinational logic, and the current expansion path is stopped when the non-combinational logic is encountered.

In a preferred embodiment, the remapping step specifically includes:

scattering the lookup table structure of the sub-circuit into a gate-level netlist;

Judging whether the problem of the sub-circuit is that the logic level is too high or the utilization rate is too high, and if the problem is that the logic level is too high, selecting a logic level optimization strategy for remapping; if the utilization rate is too high, selecting a utilization rate optimization strategy for remapping;

And remapping the gate-level netlist according to the selected strategy to obtain an optimized sub-circuit.

In a preferred embodiment, when there are a plurality of sub-circuits in the circuit that need remapping optimization, the method further comprises:

extracting the sub-circuits to be optimized by executing circuit extraction for multiple times, and obtaining a plurality of sub-circuits to be optimized;

Repeatedly executing the remapping step on each sub-circuit to be optimized, and realizing parallel remapping of a plurality of sub-circuits;

And repeating the incremental layout step for all the sub-circuits after the sub-circuits to be optimized are subjected to remapping.

In a preferred embodiment, the incremental layout step specifically includes:

Determining the initial position of a key device of the sub-circuit by utilizing the position of the boundary port of the original circuit;

calculating a boundary box of a sub-circuit formed by the initial positions of the key devices, and setting the initial positions of the rest devices in the sub-circuit as the central area of the boundary box;

And calling a layout device to execute incremental layout on the devices in the sub-circuit only so as to adapt to the change of the number of the devices and the connection relation of the new sub-circuit, wherein the positions of the devices outside the sub-circuit are kept unchanged in the incremental layout process, thereby realizing the optimization of the internal layout of the sub-circuit without affecting other parts of the whole circuit.

In a preferred embodiment, the critical devices comprise new devices connected to the boundary input output ports of the sub-circuit, wherein the initial position of each critical device is determined based on the known physical position of the boundary port and the critical device has a decisive role in the function or signal path of the sub-circuit, the critical device may be selected from the group consisting of: the lookup table is connected with the boundary port, the lookup table adjacent to the connected lookup table and the lookup table on the main logic path of the sub-circuit.

The application also discloses a system for remapping the local circuit in the FPGA layout stage, which comprises:

And a circuit extraction module: the method is used for selecting a sub-circuit to extract based on a corresponding specific rule according to the problem that the logic level of a circuit observed in a layout stage is too high or the local utilization rate is too high;

Remapping module: the method comprises the steps of carrying out remapping on an extracted sub-circuit, firstly scattering a lookup table structure of the sub-circuit into a gate-level netlist, and then selecting a corresponding remapping strategy according to excessively high logic level or excessively high utilization rate to obtain a remapped optimized sub-circuit;

incremental layout module: the method comprises the steps of performing incremental layout on a sub-circuit after remapping, determining the initial positions of key devices of the sub-circuit by utilizing the boundary port positions of an original circuit, and calling a layout device to only layout the devices in the sub-circuit;

Decision module: the method is used for checking whether the result after incremental layout achieves the optimization purpose and deciding whether to accept the remapping result, continuously checking other sub-circuits needing to be optimized, notifying a circuit extraction module, controlling the remapping iteration process, and processing a plurality of sub-circuits needing to be optimized in parallel when necessary.

a memory for storing computer executable instructions; and

A processor for implementing steps in a method as described hereinbefore when executing said computer executable instructions.

The application also discloses a computer readable storage medium having stored therein computer executable instructions which when executed by a processor implement the steps in the method as described hereinbefore.

The invention has the technical effects that:

(1) Aiming at the problems existing in the layout stage, the corresponding sub-circuits are extracted, different remapping strategies are allowed to be executed on different sub-circuits, the influence on other circuit parts is reduced, and the optimization efficiency is improved;

(2) Through the incremental layout, the whole circuit is prevented from being rearranged, the existing layout result is protected, and the optimization efficiency is further improved;

(3) And the remapping of a plurality of sub-circuits is supported to be processed in parallel, so that the optimization efficiency is greatly improved, and a more efficient problem solution is realized.

In conclusion, the technical scheme of the application can realize the rapid and targeted circuit optimization in the layout stage, improve the mapping effect and the circuit performance, and has important technical progress significance.

The numerous technical features described in the description of the present application are distributed among the various technical solutions, which can make the description too lengthy if all possible combinations of technical features of the present application (i.e., technical solutions) are to be listed. In order to avoid this problem, the technical features disclosed in the above summary of the application, the technical features disclosed in the following embodiments and examples, and the technical features disclosed in the drawings may be freely combined with each other to constitute various new technical solutions (these technical solutions are regarded as already described in the present specification) unless such a combination of technical features is technically impossible. For example, in one example, feature a+b+c is disclosed, in another example, feature a+b+d+e is disclosed, and features C and D are equivalent technical means that perform the same function, technically only by alternative use, and may not be adopted simultaneously, feature E may be technically combined with feature C, and then the solution of a+b+c+d should not be considered as already described because of technical impossibility, and the solution of a+b+c+e should be considered as already described.

Drawings

Fig. 1 is a flow diagram of a method for local circuit remapping in an FPGA layout stage according to a first embodiment of the present application.

Fig. 2 is a schematic diagram of sub-circuit expansion in a method of local circuit remapping at an FPGA layout stage according to a first embodiment of the application.

Fig. 3 is a flow chart of circuit extraction steps in a method for remapping local circuits in an FPGA layout stage according to a first embodiment of the present application.

Fig. 4 is a schematic diagram of the remap flow in the method of local circuit remapping in the FPGA layout stage according to the first embodiment of the application.

Fig. 5 is a schematic diagram of the remapping process in the method of FPGA layout stage local circuit remapping according to the first embodiment of the present application.

Fig. 6 is a flow diagram of an incremental layout in a method of FPGA layout stage local circuit remapping according to a first embodiment of the present application.

Fig. 7 is a schematic diagram of a system for remapping local circuits in an FPGA layout stage according to a second embodiment of the present application.

Detailed Description

In the following description, numerous specific details are set forth in order to provide a thorough understanding of the present application. It will be understood by those skilled in the art that the claimed application may be practiced without these specific details and with various changes and modifications from the embodiments that follow.

Description of the partial concepts:

FPGA (Field Programmable GATE ARRAY, field programmable logic array): this is a semi-custom circuit that is widely used in the field of application specific integrated circuits. The FPGA combines the high efficiency of the full custom circuit and the flexibility of the programmable logic device, and solves the problems of the limitation of the full custom circuit and the limited number of gates in the traditional programmable logic device.

Layout (Placement): layout is an important link of integrated circuit automation design, and the goal is to arrange all devices on proper positions on a chip reasonably, and simultaneously ensure that key design indexes such as line length, time sequence and the like are met.

Circuit remapping (Re-mapping): circuit remapping is the process of remapping a particular sub-circuit based on a completed circuit map. This is mainly used to optimize a specific performance index, and is an improvement and adjustment to the original circuit mapping.

Look Up Table (LUT): in the FPGA, the lookup table is a basic logic unit for realizing arbitrary input combination logic, and is a core component of the FPGA chip design.

Logic progression: the logic level defines the number of look-up tables traversed by a segment of pure combinational logic from input to output, while the maximum logic level specifies the maximum number of look-up tables on the longest path traversed.

The following outline of some of the innovative features of the present application:

After extensive research and analysis, the inventor of the present application considers that, aiming at the circuit mapping problem which can only be found in the layout stage, the existing methods mainly have two kinds: firstly, the logic synthesis strategy is adjusted to optimize the problem sub-circuit and remap, but the method can require multiple iterations and has low efficiency; secondly, the layout strategy is adjusted to improve the physical location of the problem subcircuit, which however does not address the problem at all. In view of these limitations, the present application proposes a solution to perform a local remapping of problem subcircuits at the layout stage. Unlike global mapping, local remapping allows selected sub-circuits to be handled separately, avoiding interference with the overall circuit, and reducing the creation of new problems. In addition, the scheme supports incremental layout of the remapped sub-circuits in the layout stage, and the whole circuit does not need to be rearranged, so that the repair efficiency is improved. The scheme can automatically process a plurality of sub-circuits with different problems, realizes the automation of the repairing process, and improves the efficiency and effect of the overall design.

For the purpose of making the objects, technical solutions and advantages of the present application more apparent, embodiments of the present application will be described in further detail below with reference to the accompanying drawings.

The first embodiment of the application relates to a method for remapping local circuits in an FPGA layout stage, the flow of which is shown in fig. 1, and the method comprises the following steps:

Step 10: extracting: according to the problem that the logic level is too high or the local utilization rate is too high in the circuit observed in the layout stage, sub-circuits are selected to be extracted based on the corresponding specific rules;

Step 20: a remapping step: remapping the extracted sub-circuits, firstly scattering the lookup table structure of the sub-circuits into a gate-level netlist, and then selecting a corresponding remapping strategy according to excessively high logic level or excessively high utilization rate to obtain a remapped optimized sub-circuit;

step 30: incremental layout step: and performing incremental layout on the sub-circuits after the remapping, determining the initial positions of key devices of the sub-circuits by using the positions of boundary ports of the original circuits, and calling a layout device to only layout the devices in the sub-circuits.

Optionally, in step 10, the specific rule corresponding to the specific rule specifically includes:

Optionally, the remapping step of step 20 specifically includes:

Optionally, when there are a plurality of sub-circuits in the circuit that need remapping optimization, the method of this embodiment further includes:

Optionally, the incremental layout step of step 30 specifically includes:

Optionally, the critical devices include new devices connected to the boundary input output ports of the sub-circuit, wherein the initial position of each critical device is determined based on the known physical position of the boundary port and the critical device has a decisive role in the function or signal path of the sub-circuit, the critical device may be selected from the group consisting of: the lookup table is connected with the boundary port, the lookup table adjacent to the connected lookup table and the lookup table on the main logic path of the sub-circuit.

The above embodiment has the following technical effects:

By locally remapping the key sub-circuits during the layout stage, problematic circuit portions can be optimized targeted without affecting other circuits, enabling a fast and efficient circuit performance improvement. Compared with global remapping, the remapping mechanism can avoid introducing new problems, shortens the optimization time and improves the quality of circuit mapping.

Furthermore, the incremental layout enables the remapped sub-circuits to rapidly complete the layout without global layout, thereby protecting other circuit layouts and further improving the repair efficiency.

Furthermore, parallel remapping and unified layout of multiple sub-circuits are supported, different problem circuits can be automatically processed, and overall optimization time is greatly shortened.

The embodiment realizes the quick repair of the circuit aiming at the mapping problem in the layout stage, and simultaneously reserves the balance of global mapping, so that the time sequence, the power consumption and the frequency index of the circuit are comprehensively improved. The embodiment has wide application, can effectively solve the mapping problem of different types of circuits in the layout stage, reduces the complex multiple global remapping requirement, and simplifies the design flow. The embodiment can be popularized and applied to layout optimization of various integrated circuit designs, and has good applicability.

In summary, the above embodiments can realize the rapid and targeted circuit optimization in the layout stage, improve the mapping effect, and improve the circuit performance, and have important technical progress significance.

In order to better understand the technical solution of the present application, the following description is given with reference to a specific example, in which details are listed mainly for the purpose of understanding, and are not intended to limit the scope of protection of the present application.

In this example, a method for implementing local remapping in a layout stage is provided, including the following steps:

Step 100: extraction step

The extraction of sub-circuits is performed according to the problems observed in the layout stage, and two common problems are taken as an example for description (the process is also applicable to other circuit problems which can be solved by remapping), and the logic level of the combined circuit is too high, so that the time sequence requirement is not met, and the wiring congestion caused by the local utilization is too high is serious. If the logic level is too high, expanding the circuit according to the combination logic passed by the key time sequence path as a basis until the scale reaches the requirement of the minimum remapping circuit; if the local utilization rate is too high, selecting a path with larger timing margin to expand based on the combination logic in the region until the scale reaches the requirement of a minimum remapping circuit;

Step 200: remapping step

Remapping the extracted sub-circuits, firstly scattering the sub-circuits in the form of a lookup table into a gate-level netlist, and then selecting a strategy for remapping which is prone to optimizing logic level or circuit area according to the problems existing in the circuit;

step 300: incremental layout step

The new sub-circuit after the remapping is distributed in an increment mode, and the number and the connection relation of the devices of the new sub-circuit are completely different from those of the original sub-circuit, so that the initial positions of part of devices are required to be determined firstly through the connection relation of the original circuit boundary, then the rest other devices are limited in the area formed by the devices with the determined positions, and a layout device is called to conduct the increment layout on the devices on the basis.

Alternatively, the above method may be implemented by a system including: the device comprises a circuit extraction module, a remapping module, an incremental layout module and a decision module. The steps described above for this example are described in further detail below in connection with the above-described exemplary systems implementing the steps.

In step 100 (extraction step), if the logic level is too high, the circuit is expanded based on the combinational logic passed by the critical timing path until the scale reaches the minimum remapping circuit requirement. That is, based on the combinational logic portion passed on the critical timing path (the critical path affecting the timing requirement), expansion is performed to obtain a complete sub-circuit until the sub-circuit scale reaches the minimum scale requirement required for remapping.

If the local utilization rate is too high, selecting a path with larger timing margin to expand based on the combinational logic in the region until the scale reaches the requirement of the minimum remapping circuit. That is, based on combinational logic in the over-utilized region, the path along which the timing margin is large (insensitive to timing effects) is expanded until the minimum re-map size requirement is reached.

That is, if the logic level is too high, the sub-circuits are extracted and expanded based on the combinational logic of the critical timing path; if the local utilization is too high, the sub-circuits are selected and expanded based on paths with larger timing margins until the minimum circuit scale required for remapping is met.

Alternatively, this step 100 may be implemented by the circuit extraction module of the system described above. Taking a critical path of extracting a high logic level as an example, the processing of the circuit extracting module specifically includes:

the first step:

The first step requires finding combinational logic on the critical path as the base subcircuit. The critical path is a timing path which needs to be concerned when optimizing, and generally, registers are used as the starting point and the end point of the path, and the combinational logic of other non-macro units except for the registers at the beginning and the end of the path are used as basic sub-circuits.

Specifically, in this step, a critical path in the FPGA design is first identified, which is a specific timing path, starting with registers and ending with combinational logic on the path. The combinational logic on this path, except for the head-to-tail registers, is selected as part of the underlying subcircuit. This is because logic on the critical path directly affects the timing performance of the circuit, and therefore requires special attention and optimization.

And a second step of:

The second step requires expansion on the basic sub-circuits (the purpose of remapping is to adjust the number of stages and area of the sub-circuits, which are typically too small to adjust space), with the rule that for each of the look-up table (LUT) devices in the basic sub-circuits, its output net load device, input net drive device, and input net bypass load device are incorporated into the sub-circuits, respectively. The sub-circuits that need to be explicitly extracted must be purely combinational logic, so that other devices or ports, except the look-up table logic, are treated as boundaries, and encountering a boundary stops the expansion on this path. As shown in fig. 2, the expansion is based on LUT1, LUT2 is a load device on the output line network, LUT3 is a drive device on the input line network, LUT4 is an input line network bypass load device, all of which are incorporated into the sub-circuit, and neither Register (REG) nor block memory (ERAM) are incorporated into the sub-circuit as boundaries.

Note that the specific expansion rules employed in this example are: for each lookup table (LUT) in the basic sub-circuit, a load LUT with an output end connected, a drive LUT with an input end connected and a load LUT with an input bypass are added into the sub-circuits respectively. But it is noted that the decimated sub-circuits must remain as pure combinational logic when expanded. Therefore, when other non-combinational logic devices such as registers and memories are encountered, the non-combinational logic devices are used as boundaries, and expansion of the path is stopped.

Fig. 2 gives a specific expansion example in which LUT1 is expanded as a basis, LUT2, LUT3, LUT4 are added to the sub-circuit due to the connection relationship, and register REG and memory ERAM are not added as boundaries.

In other words, in this step, the underlying sub-circuit will expand according to certain rules, primarily for the purpose of adjusting the logic level and area of the sub-circuit to accommodate the remapping needs. This expansion involves incorporating into the sub-circuit the relevant devices of each look-up table (LUT) in the sub-circuit, such as the load device of the output net, the drive device of the input net, and the bypass load device of the input net. The process of expansion ensures that the sub-circuits remain as pure combinational logic, so that devices or ports other than the look-up table are considered boundaries and expansion is stopped when these boundaries are encountered.

And a third step of:

And judging whether the size of the sub-circuit meets the requirement after the expansion operation is finished, and repeating the second step until the remapping requirement is met if the size of the sub-circuit does not meet the requirement.

After the expansion operation is completed, it is necessary to determine whether the obtained sub-circuit scale meets the minimum scale requirement of the remapping. The remapping requires a sub-circuit of a suitable size to exert the effect of adjustment and optimization, and if the expanded sub-circuit does not meet the scale requirement, the expansion operation of the second step needs to be repeated, and the expansion of the basic sub-circuit is performed again, so as to obtain a sub-circuit of a larger scale. The process of expanding and determining the size of the sub-circuit is repeated until the sub-circuit determined meets the minimum size requirement of the remapping operation, thereby obtaining a sub-circuit of suitable size for subsequent remapping.

It follows that this process may require multiple iterations to ensure that the final sub-circuit is suitable for remapping purposes.

Further, in step 200 (remapping step), the decimated sub-circuits are first converted from a look-up table (LUT) form to a gate level netlist form, enabling finer and flexible remapping of the circuits. Next, depending on the specific problems of the sub-circuits, such as an excessively high logic level or an excessively large circuit area, a corresponding remapping strategy is selected to solve the specific problems by optimizing the logic level or the circuit area, thereby improving the overall circuit performance.

More specifically, step 200 is to perform a remapping operation on the extracted sub-circuits. The first step in the remapping operation is to break up the look-up table (LUT) structure of the sub-circuits into a gate level netlist, so as to allow the sub-circuits to revert to a pre-mapped gate level form in preparation for remapping. Selecting different remapping strategies according to the problems of the sub-circuits, and selecting the remapping strategy for optimizing the logic level if the problems of the sub-circuits are that the logic level is too high; if the problem is that the circuit area is too large, then the remapping strategy that optimizes the area is selected. And finally, performing remapping operation on the gate-level netlist according to the selected strategy, and obtaining a new sub-circuit optimized for the corresponding problem after remapping is completed.

Alternatively, the step 200 may be implemented by a remapping module of the above system, where the remapping module specifically includes:

the first step:

the first step requires the sub-circuits to be broken up into a gate-level netlist recognizable by the mapper, which is to restore the mapped results before the mapping can be performed again on the basis of the restored results. The break-up operation can be regarded as the inverse of the mapping, and the gate-level netlist recognizable by the mapper is a logic circuit consisting of only two-input AND gates and inverters, which can represent any binary combinational logic in a complete form.

In particular, this step involves the restoration of the extracted sub-circuits to a gate level netlist form that can be processed by the mapper in order to restore the sub-circuits from a completed mapped state to a pre-mapped state for re-mapping. This restoration process essentially reverse-converts the sub-circuits from their mapped states back to a gate-level netlist of basic logic elements (two-input AND gates and inverters), which form may represent any binary combinational logic, providing the necessary basis for remapping.

And a second step of:

The second step needs to constrain the boundary of the sub-circuit and set policy tendency for the mapper, which aims to guide the remapping result to more focus on logic level or circuit area, so that the remapped circuit can reach the required target. The boundary constraint process is to mark the actual arrival time (actual ARRIVAL TIME) for the input port of the sub-circuit, and mark the required arrival time (required ARRIVAL TIME) and the maximum logic number for the output port, so that the mapped circuit is constrained to meet the time sequence requirement.

Specifically, in this step, explicit constraints are set on the boundaries of the sub-circuits, and the mapping strategy is adjusted to optimize the logic level or circuit area. This operation is intended to ensure that the remapping process meets performance objectives. The method is realized by marking the actual arrival time of the input port of the sub-circuit, marking the required arrival time of the output port and setting the maximum logic level number, so that the circuit after remapping is ensured to meet the time sequence requirement, and the remapping result is promoted to reach the expected optimization target.

And a third step of:

and thirdly, executing remapping operation by using the mapper, checking whether the logic level number and the circuit area meet the requirements or not according to the remapping result of the sub-circuit, and if not, readjusting the boundary constraint and the mapping strategy to execute remapping again. And iteratively executing the second step and the third step until the requirement is met or the iteration number reaches an upper limit.

As shown in fig. 4, which is a flow chart of sub-circuit remapping, three lookup tables with connection relations in the original sub-circuit are broken up into a combination logic composed of a two-input and gate and an inverter, and the two lookup tables are changed into two lookup tables after mapping remapping. The original two-stage critical paths (shown as LUT2 and LUT 3) marked by the dotted lines are remapped and then become a one-stage critical path (shown as LUT 4), so that the aim of optimization is fulfilled.

In this step, the mapper is first invoked to perform the remapping operation of the sub-circuits. After the mapping is completed, it is checked whether the logic level and the circuit area of the sub-circuit meet the requirements. If not, the boundary constraint and the mapping strategy need to be readjusted, and remapping is performed again. This process may require multiple iterations until the result meets the criteria or reaches an upper iteration limit. This ensures that the sub-circuit structure and performance is optimized to achieve a predetermined goal, such as in the case of fig. 4, reducing the three LUTs in the original sub-circuit to two LUTs after remapping, and reducing the critical path progression from two stages to one stage.

Fourth step:

and fourthly, replacing the original sub-circuit by the sub-circuit after remapping according to the connection relation of the boundary ports.

Specifically, in this step, the remapped sub-circuit will be used to replace the original sub-circuit. This is done by taking into account the connection between the boundary ports of the sub-circuits, ensuring that the replaced sub-circuits are properly connected to the rest of the circuit, thereby maintaining the function and performance of the overall circuit.

More specifically, this step replaces the remapped optimized sub-circuits back to the original circuit. In the replacement, the connection relation of the boundary ports of the sub-circuits is needed. The boundary ports of the sub-circuits remain unchanged before and after remapping for connection to outside the sub-circuits. And accurately replacing the sub-circuit after remapping optimization into the original circuit according to the connection relation of the ports. After replacement, the optimized sub-circuit replaces the original sub-circuit and becomes part of the circuit to achieve optimization of the original circuit. Fig. 5 shows the overall flow of the remapping module, wherein the fourth step is to replace the optimized sub-circuits back to the original circuit.

Further, in step 300 (incremental layout step), the new sub-circuits after remapping are incrementally laid out. This process first determines the initial position of some devices through the boundary connection of the original circuit, and then limits the remaining devices to the area constituted by these located devices. Finally, incremental placement is performed on the devices using a placer to accommodate changes in the number of devices and connection relationships of the new sub-circuit.

More specifically, in the incremental layout of the new sub-circuit obtained by remapping, since the number of devices and the connection relationship inside the sub-circuit after remapping have been changed and are not the same as those of the original sub-circuit, a new circuit is formed, so that the layout of the original sub-circuit cannot be directly followed, and the layout needs to be rearranged. But incremental placement is required considering that the circuit placement of the other parts cannot be changed. According to the connection relation of the boundary of the sub-circuit, the boundary port comprises the input and output of a register connected with the sub-circuit, the input and output of a macro unit module and the input and output of a top layer module, according to the positions of the boundary ports, the initial positions of the lookup tables directly connected with the boundary port after remapping (only one type of device of the lookup tables in the sub-circuit is optimized due to remapping), and then the initial positions of the rest devices are determined in the center of the constraint by taking the area surrounded by the lookup tables as the constraint. And calling a layout device on the basis, and performing layout optimization on devices in the sub-circuit only without changing the original layout condition outside the sub-circuit, thereby realizing incremental layout of the sub-circuit only.

Alternatively, the step 300 may be implemented by an incremental layout module of the above system, where the processing of the incremental layout module specifically includes:

All devices and connection relations in the remapped sub-circuit are newly generated and can completely replace the original sub-circuit. Because of the remapping implemented during the layout stage, it is necessary to determine the physical location of each device within the new sub-circuit, i.e., to incrementally layout the newly created devices.

The first step:

the first step is to determine the initial position of a part of devices from the positions of the boundary input/output ports. Since the original sub-circuit is physically located, the physical location on each port of the sub-circuit can be obtained. After remapping, each port will be connected with a new device, and then the initial positions of these devices are set as the positions of the connected boundary ports.

Specifically, this step determines the initial position of a part of the devices by the position of the boundary input output port. Because the original subcircuit already has physical location information, this information can be used directly to determine the physical location of each port. After the sub-circuits are remapped, each port will be connected to new devices whose initial positions are set at the positions of the corresponding boundary ports. This ensures that the new sub-circuit remains consistent in physical layout with the original sub-circuit.

In other words, the initial positions of some of the critical devices are determined based on the positions of the boundary input output ports of the sub-circuits. This is possible because the original sub-circuit has been laid out with specific physical location information for each port, the boundary ports of the sub-circuit remain unchanged after remapping, and each boundary port is connected to a new internal device after remapping. In order to quickly determine the location of these new devices, their initial location may be set directly to the location of the connected border port. Thus, the initial positions of a part of key devices can be directly obtained through the position information of the boundary ports. These critical devices will determine the main shape and framework of the sub-circuit.

And a second step of:

and the second step is to calculate the bounding box (bounding box) enclosed by the bounding ports. The boundary ports of the sub-circuits can reflect the general area in which the sub-circuit layout is located, but this is not a hard limit, but merely determines the initial position of the device.

Specifically, this step calculates a bounding box (bounding box) formed by the sub-circuit boundary ports. This bounding box reflects the general area in which the sub-circuit layout is located based on the physical location of the sub-circuit ports. While this bounding box provides a reference for the initial placement of the device, it is not strictly limited but is used to determine the initial layout position of the device.

And a third step of:

And thirdly, setting the central point of the area surrounded by the boundary box as the initial position of the rest devices.

In particular, this means that devices for which a specific location has not been determined will be initially placed near this center point, providing a starting reference point for the subsequent detailed layout.

More specifically, this step is to set the center point of the region within the bounding box as the initial position of the remaining devices. The positions of some key devices have been determined in the first two steps, forming a bounding box for the sub-circuit, and the positions of some devices within the sub-circuit need to be determined. In order to quickly give the initial positions of the residual devices, the initial positions of the residual devices can be directly set as the center point of the boundary box area, so that the initial positions of the residual devices can be quickly generated by utilizing the main area information of the sub-circuits reflected by the boundary box. This initial position is not the final position and the position of the device can also be adjusted in a subsequent layout optimization.

Fourth step:

The fourth step uses the layout device to perform incremental layout optimization on all devices in the sub-circuit. The incremental layout only moves devices inside the sub-circuit, protecting the device locations outside the sub-circuit from being affected, thereby avoiding the possibility of introducing new problems.

Specifically, this step invokes the placer to perform incremental placement optimization on all devices within the sub-circuit. This incremental layout focuses on moving devices within the sub-circuit without affecting the device location outside the sub-circuit, thereby avoiding introducing new problems in other parts of the circuit.

In other words, in this step, the incremental layout only moves and adjusts the device position inside the sub-circuit, while the device position of the original layout outside the sub-circuit is protected and not affected, which has the advantage that it is possible to avoid introducing new problems by modifying the external layout of the sub-circuit. The incremental layout only locally adjusts the inside by protecting the outside of the sub-circuit, so that the layout of the sub-circuit is optimized, the original layout of the outside is not influenced, and the new problem possibly introduced by global layout optimization is avoided.

After this step has completed the incremental layout, the optimized sub-circuit layout is determined.

Further, the system may further include a decision module, where the decision module plays a role in the overall process (see fig. 7), and the role includes:

(1) Whether the result after the incremental layout achieves the aim of optimization is checked, and the result of receiving or backing the remapping can be selected according to the target of interest, namely whether the remapping result is received or not is determined according to the target of interest.

(2) And checking whether the problem that the optimization is required exists in the current circuit, for example, whether other sub-circuits are required to be optimized after the remapping of the current sub-circuit is finished, if so, notifying the circuit extraction module to continue the optimization of the next sub-circuit, namely, checking whether the current circuit is required to be optimized by the other sub-circuits, and if so, notifying the circuit extraction module to continue the extraction of the next sub-circuit.

(3) When the remapping iteration is repeated and the result meeting the requirement cannot be obtained, the decision module is responsible for adjusting parameters and recalling the circuit extraction module to extract the subcircuit, and the iteration between the circuit extraction module and the remapping module is controlled.

In order to improve the optimization efficiency, when a plurality of sub-circuits in the circuit need to be subjected to remapping optimization, the decision module can call the circuit extraction module for a plurality of times and decouple each sub-circuit needing to be optimized, so that boundaries among the sub-circuits are divided. At this time, the system can process the sub-circuits in parallel, and perform incremental layout uniformly after remapping of all the sub-circuits is completed.

In other words, if there are multiple sub-circuits to be optimized, the decision module may invoke the circuit extraction module multiple times and divide the sub-circuit boundaries so that the system may process the sub-circuits in parallel. After remapping of all sub-circuits is completed, the incremental layout is performed uniformly.

In summary, the specific functions of the decision module of the system may include:

result checking and decision:

The decision module firstly checks whether the result after incremental layout achieves the aim of optimization. It may decide whether to accept the remapping result or fall back to the previous state based on a specific index. This ensures that only optimization results meeting specific requirements will be adopted.

And (5) continuously optimizing and checking:

The decision module checks whether there are other sub-circuits in the current circuit that need to be optimized. If the decision module finds that the sub-circuits are needed to be optimized, the decision module informs the circuit extraction module to continue the sub-circuit optimization of the next round, so that all potential problems can be solved.

Iterative control and adjustment:

When the remapping still does not reach a satisfactory result after a plurality of iterations, the decision module is responsible for adjusting parameters and recalling the circuit extraction module to extract the subcircuits, and the iteration of the whole flow is controlled to find a better optimization result.

Parallel processing and efficiency improvement:

In order to improve the optimization efficiency, when the decision module finds that a plurality of sub-circuits needing remapping exist in the circuit, the decision module can call the circuit extraction module for a plurality of times, independently process each sub-circuit needing optimization, and divide boundaries among the sub-circuits. This allows the system to process multiple sub-circuits in parallel and finally to uniformly perform an incremental layout, thereby greatly improving overall processing speed and efficiency.

Therefore, the decision module plays a key role in up-down connection in the system, is not only responsible for checking and deciding results, but also controls the iteration of the flow and the parallel processing of a plurality of sub-circuits, and is a core component in the whole circuit optimization flow.

The innovation points in the above examples and the technical effects thereof include:

1) The specific rule extraction subcircuit is used for local remapping:

the effect is as follows: the method realizes targeted optimization, allows the application of respective remapping strategies to different sub-circuits, and improves the accuracy and efficiency of the optimization. In addition, local remapping avoids unnecessary effects on other parts of the circuit and reduces the complexity of the overall mapping.

2) The incremental layout is applied to the remapping subcircuit:

the effect is as follows: by incrementally laying out specific sub-circuits, a full re-layout can be prevented, thereby preserving existing layout results and improving overall layout efficiency.

3) Parallel remapping process for multiple sub-circuits:

The effect is as follows: and by utilizing good isolation and decoupling characteristics among the sub-circuits, parallel remapping and subsequent unified incremental layout of a plurality of sub-circuits are realized, and the efficiency of the whole optimization flow is obviously improved.

A second embodiment of the present application relates to a system for remapping local circuits in an FPGA layout stage, whose structure is shown in fig. 7, where the system for remapping local circuits in an FPGA layout stage includes:

The first embodiment is a method embodiment corresponding to the present embodiment, and the technical details in the first embodiment can be applied to the present embodiment, and the technical details in the present embodiment can also be applied to the first embodiment.

It should be noted that, those skilled in the art should understand that the implementation functions of the modules shown in the embodiments of the system for remapping FPGA layout stage local circuits described above may be understood with reference to the description related to the method for remapping FPGA layout stage local circuits described above. The functions of the modules shown in the above embodiment of the system for remapping local circuits in the FPGA layout stage may be implemented by a program (executable instructions) running on a processor, or may be implemented by specific logic circuits. The system for remapping local circuits in the FPGA layout stage according to the embodiment of the present application may also be stored in a computer readable storage medium if implemented in the form of software functional modules and sold or used as a stand-alone product. Based on such understanding, the technical solutions of the embodiments of the present application may be embodied in essence or a part contributing to the prior art in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to execute all or part of the methods described in the embodiments of the present application. And the aforementioned storage medium includes: a U-disk, a removable hard disk, a Read Only Memory (ROM), a magnetic disk, an optical disk, or other various media capable of storing program codes. Thus, embodiments of the application are not limited to any specific combination of hardware and software.

Accordingly, embodiments of the present application also provide a computer storage medium having stored therein computer executable instructions which when executed by a processor implement the method embodiments of the present application.

In addition, the embodiment of the application also provides a system for remapping the local circuits in the FPGA layout stage, which comprises a memory for storing computer executable instructions and a processor; the processor is configured to implement the steps of the method embodiments described above when executing computer-executable instructions in the memory. The Processor may be a central processing unit (Central Processing Unit, abbreviated as "CPU"), other general purpose Processor, digital signal Processor (DIGITAL SIGNAL Processor, abbreviated as "DSP"), application SPECIFIC INTEGRATED Circuit, application Specific Integrated Circuit (ASIC), etc. The aforementioned memory may be a read-only memory (ROM), a random access memory (random access memory RAM), a Flash memory (Flash), a hard disk, a solid state disk, or the like. The steps of the method disclosed in the embodiments of the present application may be directly embodied in a hardware processor for execution, or may be executed by a combination of hardware and software modules in the processor.

It should be noted that in the present patent application, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising" does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element. In the present patent application, if it is mentioned that an action is performed according to an element, it means that the action is performed at least according to the element, and two cases are included: the act is performed solely on the basis of the element and is performed on the basis of the element and other elements. Multiple, etc. expressions include 2, 2 times, 2, and 2 or more, 2 or more times, 2 or more.

All references mentioned in this disclosure are to be considered as being included in the disclosure of the application in its entirety so that modifications may be made as necessary. Further, it is understood that various changes or modifications of the present application may be made by those skilled in the art after reading the above disclosure, and such equivalents are intended to fall within the scope of the application as claimed.

Claims

1. The method for remapping the local circuit in the FPGA layout stage is characterized by comprising the following steps:

2. The method of claim 1, wherein the corresponding specific rule is specifically:

3. The method according to claim 2, wherein the remapping step specifically comprises:

4. The method of claim 2, wherein when there are a plurality of sub-circuits in the circuit that require remapping optimization, the method further comprises:

5. The method of claim 2, wherein the incremental layout step specifically comprises:

6. The method of claim 5, wherein the critical devices comprise new devices connected to boundary input output ports of the sub-circuit, wherein an initial position of each critical device is determined based on a known physical position of the boundary port and the critical device has a decisive role in a function or signal path of the sub-circuit, the critical device being selected from the group consisting of: the lookup table is connected with the boundary port, the lookup table adjacent to the connected lookup table and the lookup table on the main logic path of the sub-circuit.

7. A system for remapping local circuitry in an FPGA layout stage, comprising:

8. A system for remapping local circuitry in an FPGA layout stage, comprising:

a memory for storing computer executable instructions; and

A processor for implementing the steps in the method of any one of claims 1 to 6 when executing the computer executable instructions.

9. A computer readable storage medium having stored therein computer executable instructions which when executed by a processor implement the steps in the method of any one of claims 1 to 6.