CN118170327A - Solid state disk address mapping method, device and product - Google Patents
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Abstract
The embodiment of the application provides a solid state disk address mapping method, a device and a product, wherein the solid state disk address mapping method is applied to a solid state disk, a cache mapping table is loaded in a memory of the solid state disk, the method comprises the steps of acquiring a target request, updating access heat parameters corresponding to mapping items in the cache mapping table, wherein the mapping items are used for representing the mapping relation between page numbers of any logical page and page numbers of physical pages, and the access heat parameters corresponding to any mapping item are determined according to the access times of the mapping item and the distance between the logical page address range of the mapping item and the access address range corresponding to the target request; when the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is full, executing a rejection strategy according to the access heat parameter corresponding to each mapping item; and adding the target mapping item corresponding to the target request into the cache mapping table. The embodiment of the application aims to improve the read-write performance of the solid state disk.
Description
Technical Field
The embodiment of the application relates to the technical field of solid state disks, in particular to a solid state disk address mapping method, a solid state disk address mapping device and a solid state disk address mapping product.
Background
The solid state disk is a novel semiconductor storage device widely applied, and compared with the traditional mechanical hard disk, the solid state disk has the advantages of low delay, shock resistance, falling resistance, high reliability, large working temperature range and the like.
The solid state disk mainly comprises modules such as host interface logic, a buffer management layer, a flash memory conversion layer, a NAND flash memory chip array and the like, and because the solid state disk adopts a process of updating in different places, the flash memory physical address corresponding to the logical address sent by the operating system can be changed frequently, so as to ensure the integrity of data, and the solid state disk needs to be responsible for mapping between the logical address and the physical address.
Address mapping is generally divided into three basic types: the current common DFTL address mapping method has the flexibility of mapping based on pages, and reduces the memory space required by the mapping table.
However, in the DFTL address mapping method, there are many problems that any request is not considered in the time dimension and the space dimension in the process of loading or removing the mapping items of the logical page and the physical page in the CMT (CACHED MAPPING table, cache mapping table), so that the hit rate of the request in the CMT is low, and the read-write performance of the solid state disk is reduced.
Disclosure of Invention
The embodiment of the application provides a solid state disk address mapping method, a solid state disk address mapping device and a solid state disk address mapping product, aiming at improving the read-write performance of a solid state disk.
In a first aspect, an embodiment of the present application provides a method for mapping addresses of a solid state disk, which is applied to a solid state disk, where a cache mapping table is loaded in a memory of the solid state disk, and the method includes:
acquiring a target request, and updating access heat parameters corresponding to each mapping item in the cache mapping table, wherein the mapping item is used for representing the mapping relation between the page number of any logical page and the page number of a physical page, and the access heat parameters corresponding to any mapping item are determined according to the access times of the mapping item and the distance between the logical page address range of the mapping item and the access address range corresponding to the target request;
When the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is full, executing a rejection strategy according to the access heat parameters corresponding to the mapping items;
And adding the target mapping item corresponding to the target request into the cache mapping table.
Optionally, updating the access heat parameter corresponding to each mapping item in the cache mapping table includes:
for any mapping item, acquiring the access times of the mapping item in the cache mapping table;
Acquiring an intersection coefficient of a logical page address range of the mapping item and an access address range corresponding to the target request, wherein the intersection coefficient is used for representing the distance between the logical page address range of the mapping item and the access address range corresponding to the target request;
And updating the access heat parameter of the mapping item according to the access times, the intersection coefficient and the preset attenuation coefficient corresponding to the mapping item.
Optionally, acquiring an intersection coefficient of the logical page address range of the mapping item and the access address range corresponding to the target request includes:
When the logical page address range of the mapping item has no intersection with the access address range corresponding to the target request, the intersection coefficient is 0;
When the logical page address range of the mapping item has an intersection with the access address range corresponding to the target request, calculating an intersection coefficient according to the minimum address and the maximum address of the mapping item and the maximum access address and the minimum access address corresponding to the target request.
Alternatively, the formula for calculating the intersection coefficient is:
Wherein D is an intersection coefficient corresponding to the mapping item; the minimum address corresponding to the mapping item is obtained; The maximum address corresponding to the mapping item is obtained; /(I) A maximum access address for the target request; /(I)A minimum access address for the target request; /(I)And the capacity of the solid state disk is obtained.
Optionally, the calculation formula of the access heat parameter of any mapping item is:
Wherein n is the access times of the mapping item in the cache mapping table, and when any mapping item is loaded into the cache mapping table, n=1; For the access heat parameter when the access times of the mapping item in the cache mapping table are n, The access heat parameter is used for the mapping item when the access times of the mapping item in the cache mapping table is n; /(I)Is the attenuation coefficient; d is the intersection coefficient of the mapping term.
Optionally, executing the culling policy includes:
determining a mapping item to be removed in the cache mapping table;
Acquiring the mapping items to be removed in the translation block area of the solid state disk, and comparing the mapping items to be removed in the translation block area with the mapping items to be removed in the cache mapping table;
and deleting the mapping item to be removed from the cache mapping table when the mapping item to be removed from the translation block area is consistent with the mapping item to be removed from the cache mapping table.
Optionally, determining the mapping item to be removed in the cache mapping table includes:
And in the cache mapping table, the mapping item with the minimum access heat parameter is used as the mapping item to be removed.
Optionally, after comparing the mapping item to be removed in the translation block area with the mapping item to be removed in the cache mapping table, the method further includes:
And when the mapping items to be removed in the translation block area are inconsistent with the mapping items to be removed in the cache mapping table, executing a translation block area updating strategy, and deleting the mapping items to be removed in the cache mapping table.
Optionally, the translation block area update policy includes:
Determining a translation page where the mapping item to be removed is located in the translation block area according to a global translation directory set in the solid state disk, wherein the global translation directory comprises a mapping relation between a virtual translation page where any mapping item is located and the translation page where the mapping item is located;
Merging the mapping item to be removed in the cache mapping table and the translation page where the mapping item to be removed is located, and writing in a new translation page;
And replacing the mapping relation of the page numbers of the virtual conversion pages corresponding to the mapping items to be removed in the global conversion directory with the page numbers of the new translation pages.
Optionally, after updating the access heat parameter corresponding to each mapping item in the cache mapping table, the method further includes:
inquiring whether the cache mapping table contains a target mapping item corresponding to the target request;
and when the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is not full, adding the target mapping item corresponding to the target request into the cache mapping table.
Optionally, adding a target mapping item corresponding to the target request in the cache mapping table includes:
determining a translation page where a target mapping item corresponding to the target request is located in a translation block area of the solid state disk according to a global translation directory set in the solid state disk, wherein the global translation directory comprises a mapping relation between a virtual translation page where any mapping item is located and the translation page where the mapping item is located;
And acquiring the target mapping item corresponding to the target request from the translation page where the target mapping item is located, and adding the target mapping item into the cache mapping table.
Optionally, the process of determining the translation page where any mapping item is located in the translation block area of the solid state disk according to the global conversion directory set in the solid state disk includes:
Determining the page number of the virtual conversion page where the mapping item is located according to the page number of the logical page corresponding to the mapping item;
According to the page number of the virtual conversion page where the mapping item is located, the page number of the translation page corresponding to the page number of the virtual conversion page where the mapping item is located is queried in the global conversion directory;
And taking the translation page corresponding to the page number of the translation page where the mapping item is located as the translation page where the mapping item is located in the translation block area of the solid state disk.
Optionally, the process of determining the page number of the virtual conversion page where the mapping item is located according to the page number of the logical page corresponding to any mapping item includes:
page number of virtual conversion page= [ page number of the logical page mapping item size/page size ]
Wherein [ (i ] represents a rounding function).
Optionally, when the cache mapping table includes a target mapping item corresponding to the target request, the method further includes:
and determining whether to change the target mapping item corresponding to the target request in the cache mapping table according to the type of the target request.
Optionally, determining whether to change the target mapping item corresponding to the target request in the cache mapping table according to the type of the target request includes:
And when the type of the target request is a write request, updating a target mapping item corresponding to the target request in the cache mapping table after executing the target request.
Optionally, determining whether to change the target mapping item corresponding to the target request in the cache mapping table according to the type of the target request includes:
and when the type of the target request is a read request, not updating a target mapping item corresponding to the target request in the cache mapping table.
In a second aspect, an embodiment of the present application provides a solid state disk address mapping device, which is applied to a solid state disk, where a cache mapping table is loaded in a memory of the solid state disk, where the device includes:
The access heat parameter updating module is used for acquiring a target request and updating access heat parameters corresponding to each mapping item in the cache mapping table, wherein the mapping item is used for representing the mapping relation between the page number of any logic page and the page number of a physical page, and the access heat parameter corresponding to any mapping item is determined according to the access times of the mapping item and the distance between the logic page address range of the mapping item and the access address range corresponding to the target request;
The mapping item eliminating module is used for executing an eliminating strategy according to the access heat parameters corresponding to each mapping item when the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is full;
And the mapping item adding module is used for adding the target mapping item corresponding to the target request into the cache mapping table.
In a third aspect, an embodiment of the present application provides a solid state disk, where the solid state disk is used to execute the solid state disk address mapping method described in the first aspect of the embodiment.
In a fourth aspect, an embodiment of the present application provides a computer apparatus, including: the system comprises at least one processor and a memory, wherein the memory stores a computer program capable of running on the processor, and the processor executes the solid state disk address mapping method according to the first aspect of the embodiment when executing the program.
In a fifth aspect, an embodiment of the present application provides a non-volatile readable storage medium, where a computer program is stored, where the computer program, when executed by a processor, performs the method for mapping addresses of solid state hard disks according to the first aspect of the embodiment.
In a sixth aspect, an embodiment of the present application provides a computer program product, including a computer program/instruction, where the computer program/instruction implements the solid state disk address mapping method according to the first aspect of the embodiment when executed by a processor.
The beneficial effects are that:
And acquiring a target request, updating access heat parameters corresponding to each mapping item in the cache mapping table, executing a rejection strategy according to the access heat parameters corresponding to each mapping item when the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is full, and then adding the target mapping item corresponding to the target request in the cache mapping table.
According to the method, an access heat parameter is set for each mapping item in the cache mapping table, the access heat parameter is determined according to the access times of the mapping item and the distance between the logical page address range of the mapping item and the access address range corresponding to the target request, therefore, the access heat parameter can be determined according to the access frequency of any mapping item in the time dimension and the distance between any mapping item and the request access address range in the space dimension, when the cache mapping table is full, the mapping item to be removed is determined according to the access heat parameter, and the target mapping item is added in the cache mapping table, so that the heat of the mapping item contained in the cache mapping table is high and is more easily hit by the request, and the read-write performance of the solid state disk is reduced.
Drawings
In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings used in the description of the embodiments or the prior art will be briefly described below.
FIG. 1 shows a flow chart of steps of a solid state disk address mapping method provided by an embodiment of the application;
FIG. 2 is a schematic diagram of a cache mapping table according to an embodiment of the present application;
FIG. 3 is a schematic diagram of obtaining a target mapping item according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a translation block area update procedure according to an embodiment of the present application;
FIG. 5 shows a flowchart of the solid state disk address mapping method according to the embodiment of the present application;
FIG. 6 shows a functional block diagram of a solid state disk address mapping device according to an embodiment of the present application;
Fig. 7 shows a schematic architecture diagram of a solid state disk according to an embodiment of the present application;
FIG. 8 shows a schematic diagram of a computer device provided by an embodiment of the application;
FIG. 9 shows a schematic diagram of a non-volatile readable storage medium provided by an embodiment of the present application.
Detailed Description
The technical solutions in the embodiments of the present application will be described below with reference to the accompanying drawings in the embodiments of the present application.
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the following detailed description of the embodiments of the present application will be given with reference to the accompanying drawings. However, those of ordinary skill in the art will understand that in various embodiments of the present application, numerous technical details have been set forth in order to provide a better understanding of the present application. The claimed application may be practiced without these specific details and with various changes and modifications based on the following embodiments. The following embodiments are divided for convenience of description, and should not be construed as limiting the specific implementation of the present application, and the embodiments can be mutually combined and referred to without contradiction.
CMT: CACHED MAPPING table, cache mapping table;
GTD: global Translation Directory, global translation directory;
DFTL: the classical flash translation layer (flash translation layer, FTL) address mapping method DFTL (demand-based FTL) puts global mapping information in flash memory, only caches the mapping information most frequently used recently, and solves the contradiction of larger mapping information and limited cache capacity in page-level mapping strategy.
The solid state disk is a novel semiconductor storage device popular in the market, and compared with the traditional mechanical hard disk, the solid state disk has the advantages of low delay, shock resistance, falling resistance, high reliability, large working temperature range and the like, and is widely applied to the fields of notebook computers, enterprise data centers and the like at present; the solid state disk mainly comprises a host interface logic, a buffer management layer, a flash memory conversion layer, a NAND flash memory chip array and other modules. The flash memory conversion layer conceals the erasing operation of the flash memory, simulates the solid state disk into a traditional hard disk with only read-write operation so as to adapt to the current file system, but because the solid state disk adopts a method of updating in different places, when updating in different places, namely when updating by taking pages as granularity, when modifying the content of one logical page, the solid state disk needs to be rewritten on a new physical page instead of writing on the physical page corresponding to the logical page currently, so that the flash memory physical address corresponding to the logical address sent by the operating system can be changed frequently, and the solid state disk needs to be responsible for mapping between the logical address and the physical address in order to ensure the integrity of data.
Address mapping is generally divided into three basic types: page-level mapping, block-level mapping, and hybrid mapping; mapping each logical page to 1 physical page based on page address mapping, which is flexible in processing requests, but the whole mapping table is stored in the memory, and the high cost of the memory limits practical application; the block-based address mapping maps each logical block to 1 physical block, which significantly reduces the size of the mapping table, but logical pages can only be mapped to fixed pages in the physical blocks, thereby greatly reducing the flexibility and space utilization of the address mapping.
The mixed mapping comprises a DFTL address mapping method commonly used at present, which not only reserves mapping flexibility based on pages, but also reduces memory space required by a mapping table, wherein in the DFTL address mapping method, a physical block of a flash memory is divided into a translation block area and a data block area, the translation block area is used for storing a global mapping table, and mapping relations between all logical page addresses and physical page addresses of a solid state disk are stored; the data block area is used for storing conventional data; the partial mapping items are dynamically loaded into a cache mapping table CMT of the RAM according to the requirements so as to process the frequent access requests.
However, in the DFTL address mapping method, there are many problems that any request is not considered in the time dimension and the space dimension in the process of loading or removing the mapping items of the logical page and the physical page in the CMT, so that the hit rate of the request in the CMT is low, and the read-write performance of the solid state disk is reduced.
In order to improve the read-write performance of the solid state disk, the embodiment of the application provides a solid state disk address mapping method.
Referring to fig. 1, a step flow chart of a solid state disk address mapping method provided by the embodiment of the present application is applied to a solid state disk, a cache mapping table CMT is loaded in a memory of the solid state disk, a flash memory of the solid state disk includes a translation block area for storing mapping items between all logical page addresses and physical page addresses of the solid state disk, and the translation block area includes a plurality of translation pages, and the method may include the following steps:
S101: and acquiring a target request, and updating access heat parameters corresponding to each mapping item in the cache mapping table.
Because the memory space in the solid state disk is limited, the global mapping table of mapping items between all logical page addresses and physical page addresses in the translation block area of the solid state disk is generally larger and cannot be placed into the memory at one time, so that the partial mapping table is dynamically loaded into the memory according to the requirement to process frequent access requests, the cache mapping table, namely CMT, which stores the partial mapping items, is used for representing the mapping relation between the page number (D_LPN) of any logical page and the page number (D_PPN) of the physical page, and the mapping items are shown in the following table 1:
Table 1 examples of mapping entries
As shown in table 1, the page number of each logical page and the page number of the corresponding physical page have a mapping relationship, and for example, physical page 0 is used for storing data of logical page 5, physical page 1 is used for storing data of logical page 6, physical page 2 is used for storing data of logical page 1, physical page 3 is used for storing data of logical page 4, physical page 4 is used for storing data of logical page 2, physical page 5 is used for storing data of logical page 3, and physical page 6 is used for storing data of logical page 0.
The size of the page is generally related to the setting of the solid state disk, for example, the page size may be 2KB, the size of each mapping item may be set in a customized manner according to the practical application requirement, for example, the mapping item size may be 4 bytes, and if the addressing capability is 8TB, when knowing the page number of any page, the page size may be mapped to the logical address range corresponding to each page.
Referring to fig. 2, a schematic diagram of a cache mapping table provided in an embodiment of the present application is shown, in this embodiment, considering that, for one mapping item, access may be performed continuously in a time dimension, or the probability of an address near an access address range corresponding to a request being accessed is higher in a space dimension, so that in the cache mapping table, an access heat parameter is set for each mapping item, for example, the access heat parameter of the mapping item of d_lpn=3 and d_ppn=150 is 3.1, the access heat parameter of the mapping item of d_lpn=1 and d_ppn=240 is 0.1, and in the practical process, all the mapping items in the cache mapping table may be ordered according to the value of the access heat parameter.
After the target request is issued, updating access heat parameters for each mapping item in the cache mapping table, wherein the access heat parameters corresponding to any mapping item are determined according to the access times of the mapping item and the distance between the logical page address range of the mapping item and the access address range corresponding to the target request.
In a possible implementation manner, the process of updating the access heat parameter corresponding to each mapping item in the cache mapping table may include:
a1: and for any mapping item, acquiring the access times of the mapping item in the cache mapping table.
Specifically, when a mapping item is added to the cache mapping table, the number of accesses of the mapping item in the cache mapping table may be recorded.
A2: and acquiring intersection coefficients of the logical page address range of the mapping item and the access address range corresponding to the target request.
The intersection coefficient is used for representing the distance between the logical page address range of the mapping item and the access address range corresponding to the target request.
When the logical page address range of the mapping item has no intersection with the access address range corresponding to the target request, the intersection coefficient is 0.
When the logical page address range of the mapping item has an intersection with the access address range corresponding to the target request, calculating an intersection coefficient according to the minimum address and the maximum address of the mapping item and the maximum access address and the minimum access address corresponding to the target request.
For example, the formula for calculating the intersection coefficient may be:
Wherein D is an intersection coefficient corresponding to the mapping item; the minimum address corresponding to the mapping item is obtained; The maximum address corresponding to the mapping item is obtained; /(I) A maximum access address for the target request; /(I)A minimum access address for the target request; /(I)And the capacity of the solid state disk is obtained.
A3: and updating the access heat parameter of the mapping item according to the access times, the intersection coefficient and the preset attenuation coefficient corresponding to the mapping item.
Specifically, the formula for calculating the access heat parameter of each mapping item is:
Wherein n is the access times of the mapping item in the cache mapping table, and when any mapping item is loaded into the cache mapping table, n=1; For the access heat parameter when the access times of the mapping item in the cache mapping table are n, The access heat parameter is used for the mapping item when the access times of the mapping item in the cache mapping table is n; /(I)Is the attenuation coefficient; d is the intersection coefficient of the mapping term.
After the target request is issued, the access heat parameter of each mapping item is comprehensively determined in two aspects of time dimension and space dimension, so that the probability of each mapping item being accessed subsequently can be reflected.
S102: and when the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is full, executing a rejection strategy according to the access heat parameters corresponding to the mapping items.
After updating the access heat parameters of all the mapping items in the cache mapping table, inquiring whether the cache mapping table contains the target mapping item corresponding to the target request.
If the cache mapping table contains the target mapping item corresponding to the target request, the target request can be executed, and whether the target mapping item corresponding to the target request in the cache mapping table is changed is determined according to the type of the target request.
When the type of the target request is a read request, the data in the physical page is directly read according to the target mapping item, and the target mapping item corresponding to the target request in the cache mapping table is not updated.
When the type of the target request is a write request, after the target request is executed, the relationship between the logical page address and the physical page address corresponding to the target request is changed due to the off-site update, so that the target mapping item corresponding to the target request in the cache mapping table needs to be updated, that is, the physical page address in the target mapping item is updated.
If the cache mapping table does not contain the target mapping item corresponding to the target request, the target mapping item corresponding to the target request stored in the translation block area needs to be added into the cache mapping table.
In a possible implementation manner, in order to facilitate determining a translation page where any mapping item is located in a translation block area, a global translation directory GTD is further provided in the solid state disk, where the GTD includes a mapping relationship between a virtual translation page where any mapping item is located and the translation page where the mapping item is located, and specifically in this embodiment, a mapping relationship between a page number (m_vpn) of the virtual translation page and a page number (m_ppn) of the translation page is stored in the GTD; in this embodiment, the GTD is stored in a battery-equipped SRAM (Static Random-Access Memory), and the GTD stored therein can be constantly maintained as long as the SRAM is kept powered on.
In a possible implementation manner, according to a global conversion directory set in the solid state disk, the process of determining a translation page where any mapping item is located in a translation block area of the solid state disk includes:
b1: and determining the page number of the virtual conversion page where the mapping item is located according to the page number of the logical page corresponding to the mapping item.
The conversion relationship between the page number of the logical page corresponding to the mapping item and the page number of the virtual conversion page is: page number of virtual conversion page= [ page number of the logical page x map entry size/page size ], wherein [ ] represents a rounding function.
Taking the page size of 2KB as an example, the mapping entry size of 4 bytes, if the page number of the logical page of the target request is 1048, i.e., d_lpn=1048, the page number of the corresponding virtual translation page is: [1048×4 bytes/2 KB ] =2.
B2: and according to the page number of the virtual conversion page where the mapping item is located, searching the page number of the translation page corresponding to the page number of the virtual conversion page where the mapping item is located in the global conversion directory.
The global conversion directory stores mapping relations between page numbers of a plurality of virtual conversion pages and page numbers of translation pages, and after determining the page numbers of the virtual conversion pages where the mapping items are located, the page numbers of the corresponding translation pages can be queried.
B3: and taking the translation page corresponding to the page number of the translation page where the mapping item is located as the translation page where the mapping item is located in the translation block area of the solid state disk.
After locating the translation page where the mapping item is located, the required mapping item can be read on the translation page.
Referring to fig. 3, a schematic diagram of obtaining a target mapping entry provided by the embodiment of the present application is shown, and it is assumed that a page number of a logical page of a target request is 1048, that is, d_lpn=1048, and a mapping entry of d_lpn=1048 is not included in a current cache mapping table; according to d_lpn=1048, calculating to obtain page number m_vpn= [1048×4 bytes/2 KB ] =2 of the corresponding virtual conversion page, determining page number m_ppn=15 of the translation page corresponding to m_vpn=2 after the global conversion directory is queried, and then reading the mapping item corresponding to d_lpn=1048 in the translation page of m_ppn=15 in the translation block area, namely, the target mapping item corresponding to the target request is d_lpn=1048, and d_ppn=681 is recorded as the target mapping item (1048, 681).
When the cache mapping table does not contain the target mapping item, after the target mapping item is read on the translation page, the target mapping item needs to be added into the cache mapping table, firstly, whether the storage space of the cache mapping table is full needs to be judged, and if the storage space of the cache mapping table is the maximumIf the current storage space of the cache mapping table is greater than or equal to/>And when the characterization cache mapping table is full, deleting the existing mapping item in the cache mapping table, and separating the storage space for the target mapping item corresponding to the target request.
In one possible implementation, the culling policy is executed when the cache mapping table is full, the culling policy comprising the steps of:
C1: and determining mapping items to be removed in the cache mapping table.
Specifically, all mapping items in the cache mapping table are traversed, the mapping item with the smallest access heat parameter is used as the mapping item to be removed, the smallest access heat parameter indicates that the mapping item is not accessed in a short period or is far away from other requested access address ranges in a short period, and then the probability of being accessed is smaller, so that the mapping item can be deleted from the cache mapping table.
C2: and acquiring the mapping item to be removed in the translation block area of the solid state disk, and comparing the mapping item to be removed in the translation block area with the mapping item to be removed in the cache mapping table.
Because if the write request is executed, the corresponding mapping item in the cache mapping table is updated, and the mapping item stored in the translation block area is the latest mapping item at the moment, but the mapping item to be removed in the translation block area is still before updating, whether the mapping item to be removed in the translation block area is consistent with the mapping item to be removed in the cache mapping table needs to be compared.
And C3: and deleting the mapping item to be removed from the cache mapping table when the mapping item to be removed from the translation block area is consistent with the mapping item to be removed from the cache mapping table.
If the mapping items to be removed in the translation block area are consistent with the mapping items to be removed in the cache mapping table, the mapping relation that the mapping items to be removed are not updated is represented, and the mapping items to be removed are directly deleted in the cache mapping table.
And C4: and when the mapping items to be removed in the translation block area are inconsistent with the mapping items to be removed in the cache mapping table, executing a translation block area updating strategy, and deleting the mapping items to be removed in the cache mapping table.
If the mapping item to be removed in the translation block area is inconsistent with the mapping item to be removed in the cache mapping table, the mapping relation of the mapping item to be removed is changed after writing operation is performed, and the mapping item to be removed in the translation block area needs to be replaced with the mapping item to be removed, which changes in the cache mapping table.
Specifically, the translation block area update policy includes:
Determining a translation page where the mapping item to be removed is located in the translation block area according to a global conversion catalog set in the solid state disk, merging the mapping item to be removed in the cache mapping table with the translation page where the mapping item to be removed is located, and writing in a new translation page; and replacing the mapping relation of the page numbers of the virtual conversion pages corresponding to the mapping items to be removed in the global conversion directory with the page numbers of the new translation pages.
Referring to fig. 4, a schematic diagram of a translation block area updating process provided in this embodiment is shown, when a cache mapping table is full, a mapping item with a minimum access heat parameter in the cache mapping table is selected as a mapping item to be removed, and the mapping item to be removed is a mapping item corresponding to 0.1 with a minimum access heat parameter: d_lpn=1, d_ppn=240, noted as map item to be culled (1, 240).
According to the page number= [ page number of the logical page ] of the virtual conversion page, the page number m_vpn=0 of the virtual conversion page where the mapping item (1, 240) to be removed is located is calculated, the page number m_ppn=23 of the translation page corresponding to m_vpn=0 is determined in the global conversion directory, and then the mapping item of d_lpn=1 is obtained in the translation page of m_ppn=23 in the translation block area: (1, 120), the mapping items to be removed in the translation block area are inconsistent with the mapping items to be removed in the cache mapping table, and the relation between the logical page address and the physical page address of the mapping items to be removed is represented to be changed.
Then, a blank translation page in the translation block area, namely, a translation page m_ppn=25 is selected, the rest of mapping items in the translation page m_ppn=23 and mapping items to be eliminated in the cache mapping table are merged and then written into a new translation page, namely, a translation page m_ppn=25, and the translation page marked m_ppn=23 is invalid.
Finally, the mapping relation of the page number m_vpn=0 of the virtual conversion page corresponding to the mapping item (1, 240) to be removed is replaced by the page number m_ppn=25 of the new conversion page in the global conversion directory.
According to the method, when the mapping item with the minimum access heat parameter is removed from the cache mapping table, the corresponding mapping item in the translation block area is updated, so that the process that one mapping item is frequently changed in the cache mapping table to frequently update the translation page is avoided, and after the mapping item with high heat is changed for a plurality of times, the mapping relation which tends to be stable is updated into the translation page, so that the read-write performance of the solid state disk is improved, and the data processing process is reduced.
S103: and adding the target mapping item corresponding to the target request into the cache mapping table.
If the memory space of the cache mapping table is at mostIf the current storage space of the cache mapping table is smaller than/>And if the cache mapping table is not full, directly adding the target mapping item corresponding to the target request into the cache mapping table.
Or after the cache mapping table is full and the mapping item to be removed is deleted from the cache mapping table, adding the target mapping item corresponding to the target request into the cache mapping table.
In a possible implementation manner, one target request may correspond to one target mapping item or a plurality of target mapping items, if there are a plurality of target mapping items, a part of target mapping items may be located in the cache mapping table, a part of target mapping items are not located in the cache mapping table, and a plurality of target mapping items not located in the cache mapping table may be added to the cache mapping table.
Referring to fig. 5, a flowchart of an implementation of a method for mapping addresses of a solid state disk provided by an embodiment of the present application is shown, which specifically includes the following steps:
s1: and the solid state disk receives the target request and updates the access heat parameters of each mapping item in the cache mapping table.
S2: and judging whether the target mapping item of the target request is in the cache mapping table or not.
If yes, executing a target request; if not, step S3 is performed.
S3: and calculating the page number of the virtual conversion page corresponding to the target mapping item according to the page number of the logical page of the target mapping item, and determining the page number of the corresponding translation page in the global conversion directory.
S4: and acquiring the target mapping item in the corresponding translation page according to the page number of the translation page.
S5: it is determined whether the cache map is full.
If the cache map is not full, S12 is executed.
If the cache map is full, S6 is performed.
S6: and selecting the mapping item with the minimum access heat parameter as the mapping item to be removed.
S7: and calculating the page number of the virtual conversion page corresponding to the mapping item to be removed according to the page number of the logical page of the mapping item to be removed, and determining the page number of the corresponding translation page in the global conversion directory.
S8: and acquiring mapping items to be removed from the corresponding translation pages according to the page numbers of the translation pages.
S9: and judging whether the mapping item to be removed changes or not.
If so, S10 is performed.
If not, S11 is performed.
S10: merging the mapping items to be removed in the cache mapping table with the translation pages where the mapping items to be removed are located, writing in a new translation page, and replacing the mapping relation of the page numbers of the virtual translation pages corresponding to the mapping items to be removed in the global translation directory with the page numbers of the new translation page.
S11: deleting the mapping item to be removed from the cache mapping table.
S12: and adding a target mapping item in the cache mapping table.
According to the method, an access heat parameter is set for each mapping item in the cache mapping table, the access heat parameter is determined according to the access times of the mapping item and the distance between the logical page address range of the mapping item and the access address range corresponding to the target request, so that the access heat parameter can be determined according to the access frequency of any mapping item in the time dimension or according to the distance between any mapping item and the request access address range in the space dimension, and then the mapping item in the cache mapping table is removed based on the access heat parameter, so that the hit rate of an external request to the mapping item in the cache mapping table is improved, and the target of improving the read-write performance of the solid state disk is achieved.
Referring to fig. 6, a functional block diagram of a solid state disk address mapping device provided by an embodiment of the present application is applied to a solid state disk, where a cache mapping table is loaded in a memory of the solid state disk, and the device includes:
the access heat parameter updating module 100 is configured to obtain a target request, update access heat parameters corresponding to mapping entries in the cache mapping table, where the mapping entries are used to represent a mapping relationship between a page number of any logical page and a page number of a physical page, and the access heat parameters corresponding to any mapping entry are determined according to the number of accesses of the mapping entry and a distance between a logical page address range of the mapping entry and an access address range corresponding to the target request;
The mapping item rejecting module 200 is configured to execute a rejecting policy according to the access heat parameter corresponding to each mapping item when the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is full;
And the mapping item adding module 300 is configured to add a target mapping item corresponding to the target request to the cache mapping table.
Optionally, the access heat parameter updating module includes:
the access frequency determining unit is used for obtaining the access frequency of any mapping item in the cache mapping table;
An intersection coefficient determining unit, configured to obtain an intersection coefficient of a logical page address range of the mapping item and an access address range corresponding to the target request, where the intersection coefficient is used to characterize a distance between the logical page address range of the mapping item and the access address range corresponding to the target request;
and the access heat parameter determining unit is used for updating the access heat parameter of the mapping item according to the access times, the intersection coefficient and the preset attenuation coefficient corresponding to the mapping item.
Optionally, the intersection coefficient determining unit includes:
A first intersection coefficient determining subunit, configured to, when the logical page address range of the mapping item and the access address range corresponding to the target request have no intersection, set the intersection coefficient to 0;
And the second intersection coefficient determining subunit is used for calculating the intersection coefficient according to the minimum address and the maximum address of the mapping item, and the maximum access address and the minimum access address corresponding to the target request when the logical page address range of the mapping item is intersected with the access address range corresponding to the target request.
Optionally, the mapping item rejecting module includes:
the mapping item to be removed determining unit is used for determining the mapping item to be removed in the cache mapping table;
The comparison unit is used for acquiring the mapping items to be removed in the translation block area of the solid state disk and comparing the mapping items to be removed in the translation block area with the mapping items to be removed in the cache mapping table;
And the rejecting unit is used for deleting the mapping item to be rejected in the cache mapping table when the mapping item to be rejected in the translation block area is consistent with the mapping item to be rejected in the cache mapping table.
Optionally, the to-be-culled mapping item determining unit is configured to:
And in the cache mapping table, the mapping item with the minimum access heat parameter is used as the mapping item to be removed.
Optionally, the mapping item rejecting module further includes:
And the updating unit is used for executing a translation block area updating strategy when the mapping item to be removed in the translation block area is inconsistent with the mapping item to be removed in the cache mapping table, and deleting the mapping item to be removed in the cache mapping table.
Optionally, the updating unit is further configured to:
Determining a translation page where the mapping item to be removed is located in the translation block area according to a global translation directory set in the solid state disk, wherein the global translation directory comprises a mapping relation between a virtual translation page where any mapping item is located and the translation page where the mapping item is located;
Merging the mapping item to be removed in the cache mapping table and the translation page where the mapping item to be removed is located, and writing in a new translation page;
And replacing the mapping relation of the page numbers of the virtual conversion pages corresponding to the mapping items to be removed in the global conversion directory with the page numbers of the new translation pages.
Optionally, the apparatus further comprises:
The query module is used for querying whether the cache mapping table contains a target mapping item corresponding to the target request;
the mapping item adding module is further configured to add, when the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is not full, the target mapping item corresponding to the target request to the cache mapping table.
Optionally, the mapping item adding module includes:
The mapping item adding unit is used for determining a translation page where a target mapping item corresponding to the target request is located in a translation block area of the solid state disk according to a global conversion catalog set in the solid state disk, wherein the global conversion catalog comprises a mapping relation between a virtual conversion page where any mapping item is located and the translation page where the mapping item is located; and acquiring the target mapping item corresponding to the target request from the translation page where the target mapping item is located, and adding the target mapping item into the cache mapping table.
Optionally, the apparatus further comprises:
The page number conversion module is used for determining the page number of the virtual conversion page where the mapping item is located according to the page number of the logical page corresponding to the mapping item; according to the page number of the virtual conversion page where the mapping item is located, the page number of the translation page corresponding to the page number of the virtual conversion page where the mapping item is located is queried in the global conversion directory; and taking the translation page corresponding to the page number of the translation page where the mapping item is located as the translation page where the mapping item is located in the translation block area of the solid state disk.
Optionally, the apparatus further comprises:
And the target mapping item updating module is used for determining whether to change the target mapping item corresponding to the target request in the cache mapping table according to the type of the target request.
Optionally, the target mapping item updating module includes:
and the first target mapping item updating unit is used for updating the target mapping item corresponding to the target request in the cache mapping table after executing the target request when the type of the target request is a write request.
Optionally, the target mapping item updating module includes:
and the second target mapping item updating unit is used for not updating the target mapping item corresponding to the target request in the cache mapping table when the type of the target request is a read request.
Referring to fig. 7, an architecture schematic diagram of a solid state disk provided by an embodiment of the present application is shown, where the solid state disk includes a host interface module, a buffer management layer, a flash memory conversion layer, and a NAND flash memory chip array, and includes an access heat parameter calculating unit, where the solid state disk is used to execute the solid state disk address mapping method described in the embodiment, and the access heat parameter calculating unit is used to calculate an access heat parameter corresponding to any mapping item in a buffer mapping table.
Referring to fig. 8, a schematic diagram of a computer device according to an embodiment of the present application is shown, including: at least one processor 801, and a memory 802, where the memory 802 stores a computer program executable on the processor 801, and the processor 801 executes the solid state disk address mapping method according to the embodiment when executing the program.
Referring to fig. 9, a schematic diagram of a nonvolatile readable storage medium provided by an embodiment of the present application is shown, where a computer program 901 is stored in the nonvolatile readable storage medium 900, and the method for mapping addresses of solid state disks described in the embodiment is executed by a processor when the computer program 901 is executed by the processor.
The embodiment of the application also provides a computer program product, which comprises a computer program/instruction, and the computer program/instruction realizes the solid state disk address mapping method in the embodiment when being executed by a processor.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described by differences from other embodiments, and identical and similar parts between the embodiments are all enough to be referred to each other.
It will be apparent to those skilled in the art that embodiments of the present application may be provided as a method, apparatus, or computer program product. Accordingly, embodiments of the present application may take the form of an entirely hardware embodiment, an entirely software embodiment or an embodiment combining software and hardware aspects. Furthermore, embodiments of the application may take the form of a computer program product on one or more computer-usable storage media (including, but not limited to, disk storage, CD-ROM, optical storage, etc.) having computer-usable program code embodied therein.
Embodiments of the present application are described with reference to flowchart illustrations and/or block diagrams of methods, terminal devices (systems), and computer program products according to embodiments of the application. It will be understood that each flow and/or block of the flowchart illustrations and/or block diagrams, and combinations of flows and/or blocks in the flowchart illustrations and/or block diagrams, can be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general purpose computer, special purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, create means for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing apparatus to function in a particular manner, such that the instructions stored in the computer-readable memory produce an article of manufacture including instruction means which implement the function specified in the flowchart flow or flows and/or block diagram block or blocks.
These computer program instructions may also be loaded onto a computer or other programmable data processing apparatus to cause a series of operational steps to be performed on the computer or other programmable apparatus to produce a computer implemented process such that the instructions which execute on the computer or other programmable apparatus provide steps for implementing the functions specified in the flowchart flow or flows and/or block diagram block or blocks.
While preferred embodiments of the present application have been described, additional variations and modifications in those embodiments may occur to those skilled in the art once they learn of the basic inventive concepts. It is therefore intended that the following claims be interpreted as including the preferred embodiment and all such alterations and modifications as fall within the scope of the embodiments of the application.
Finally, it is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or terminal that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or terminal. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in a process, method, article, or terminal device that comprises the element.
The principles and embodiments of the present application have been described herein with reference to specific examples, the description of which is intended only to assist in understanding the methods of the present application and the core ideas thereof; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present application, the present description should not be construed as limiting the present application in view of the above.
Claims (21)
1. The solid state disk address mapping method is characterized by being applied to a solid state disk, wherein a cache mapping table is loaded in a memory of the solid state disk, and the method comprises the following steps:
acquiring a target request, and updating access heat parameters corresponding to each mapping item in the cache mapping table, wherein the mapping item is used for representing the mapping relation between the page number of any logical page and the page number of a physical page, and the access heat parameters corresponding to any mapping item are determined according to the access times of the mapping item and the distance between the logical page address range of the mapping item and the access address range corresponding to the target request;
When the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is full, executing a rejection strategy according to the access heat parameters corresponding to the mapping items;
And adding the target mapping item corresponding to the target request into the cache mapping table.
2. The method of claim 1, wherein updating the access heat parameter corresponding to each mapping entry in the cache mapping table comprises:
for any mapping item, acquiring the access times of the mapping item in the cache mapping table;
Acquiring an intersection coefficient of a logical page address range of the mapping item and an access address range corresponding to the target request, wherein the intersection coefficient is used for representing the distance between the logical page address range of the mapping item and the access address range corresponding to the target request;
And updating the access heat parameter of the mapping item according to the access times, the intersection coefficient and the preset attenuation coefficient corresponding to the mapping item.
3. The method of claim 2, wherein obtaining intersection coefficients of the logical page address range of the mapping entry and the access address range corresponding to the target request comprises:
When the logical page address range of the mapping item has no intersection with the access address range corresponding to the target request, the intersection coefficient is 0;
When the logical page address range of the mapping item has an intersection with the access address range corresponding to the target request, calculating an intersection coefficient according to the minimum address and the maximum address of the mapping item and the maximum access address and the minimum access address corresponding to the target request.
4. A method according to claim 3, wherein the formula for calculating the intersection coefficient is:
Wherein D is an intersection coefficient corresponding to the mapping item; the minimum address corresponding to the mapping item is obtained; /(I) The maximum address corresponding to the mapping item is obtained; /(I)A maximum access address for the target request; /(I)A minimum access address for the target request; /(I)And the capacity of the solid state disk is obtained.
5. The method according to any one of claims 2-4, wherein the calculation formula of the access heat parameter of any mapping item is:
Wherein n is the access times of the mapping item in the cache mapping table, and when any mapping item is loaded into the cache mapping table, n=1; For the access heat parameter when the access times of the mapping item in the cache mapping table are n, the method comprises the following steps of The access heat parameter is used for the mapping item when the access times of the mapping item in the cache mapping table is n; /(I)Is the attenuation coefficient; d is the intersection coefficient of the mapping term.
6. The method of claim 1, wherein performing a culling policy comprises:
determining a mapping item to be removed in the cache mapping table;
Acquiring the mapping items to be removed in the translation block area of the solid state disk, and comparing the mapping items to be removed in the translation block area with the mapping items to be removed in the cache mapping table;
and deleting the mapping item to be removed from the cache mapping table when the mapping item to be removed from the translation block area is consistent with the mapping item to be removed from the cache mapping table.
7. The method of claim 6, wherein determining the mapping entries to be culled in the cache mapping table comprises:
And in the cache mapping table, the mapping item with the minimum access heat parameter is used as the mapping item to be removed.
8. The method of claim 6, wherein after comparing the map entries to be culled in the translation block region with the map entries to be culled in the cache map, the method further comprises:
And when the mapping items to be removed in the translation block area are inconsistent with the mapping items to be removed in the cache mapping table, executing a translation block area updating strategy, and deleting the mapping items to be removed in the cache mapping table.
9. The method of claim 8, wherein the translation block region update policy comprises:
Determining a translation page where the mapping item to be removed is located in the translation block area according to a global translation directory set in the solid state disk, wherein the global translation directory comprises a mapping relation between a virtual translation page where any mapping item is located and the translation page where the mapping item is located;
Merging the mapping item to be removed in the cache mapping table and the translation page where the mapping item to be removed is located, and writing in a new translation page;
And replacing the mapping relation of the page numbers of the virtual conversion pages corresponding to the mapping items to be removed in the global conversion directory with the page numbers of the new translation pages.
10. The method of claim 1, wherein after updating the access heat parameter corresponding to each mapping entry in the cache mapping table, the method further comprises:
inquiring whether the cache mapping table contains a target mapping item corresponding to the target request;
and when the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is not full, adding the target mapping item corresponding to the target request into the cache mapping table.
11. The method of claim 1, wherein adding the target mapping entry corresponding to the target request in the cache mapping table comprises:
determining a translation page where a target mapping item corresponding to the target request is located in a translation block area of the solid state disk according to a global translation directory set in the solid state disk, wherein the global translation directory comprises a mapping relation between a virtual translation page where any mapping item is located and the translation page where the mapping item is located;
And acquiring the target mapping item corresponding to the target request from the translation page where the target mapping item is located, and adding the target mapping item into the cache mapping table.
12. The method according to claim 9 or 11, wherein the determining, according to the global conversion directory set in the solid state disk, a translation page where any mapping item is located in a translation block area of the solid state disk includes:
Determining the page number of the virtual conversion page where the mapping item is located according to the page number of the logical page corresponding to the mapping item;
According to the page number of the virtual conversion page where the mapping item is located, the page number of the translation page corresponding to the page number of the virtual conversion page where the mapping item is located is queried in the global conversion directory;
And taking the translation page corresponding to the page number of the translation page where the mapping item is located as the translation page where the mapping item is located in the translation block area of the solid state disk.
13. The method of claim 12, wherein determining the page number of the virtual translation page in which the mapping item is located based on the page number of the logical page to which the mapping item corresponds comprises:
page number of virtual conversion page= [ page number of the logical page mapping item size/page size ]
Wherein [ (i ] represents a rounding function).
14. The method of claim 1, wherein when the cache mapping table includes a target mapping entry corresponding to the target request, the method further comprises:
and determining whether to change the target mapping item corresponding to the target request in the cache mapping table according to the type of the target request.
15. The method of claim 14, wherein determining whether to change the target mapping entry corresponding to the target request in the cache mapping table according to the type of the target request comprises:
And when the type of the target request is a write request, updating a target mapping item corresponding to the target request in the cache mapping table after executing the target request.
16. The method of claim 14, wherein determining whether to change the target mapping entry corresponding to the target request in the cache mapping table according to the type of the target request comprises:
and when the type of the target request is a read request, not updating a target mapping item corresponding to the target request in the cache mapping table.
17. The utility model provides a solid state disk address mapping device which characterized in that is applied to solid state disk, the memory of solid state disk is loaded with the buffer mapping table, and the device includes:
The access heat parameter updating module is used for acquiring a target request and updating access heat parameters corresponding to each mapping item in the cache mapping table, wherein the mapping item is used for representing the mapping relation between the page number of any logic page and the page number of a physical page, and the access heat parameter corresponding to any mapping item is determined according to the access times of the mapping item and the distance between the logic page address range of the mapping item and the access address range corresponding to the target request;
The mapping item eliminating module is used for executing an eliminating strategy according to the access heat parameters corresponding to each mapping item when the cache mapping table does not contain the target mapping item corresponding to the target request and the cache mapping table is full;
And the mapping item adding module is used for adding the target mapping item corresponding to the target request into the cache mapping table.
18. The solid state disk is characterized in that the solid state disk is used for executing the solid state disk address mapping method according to any one of claims 1-16.
19. A computer device, comprising: at least one processor, and a memory storing a computer program executable on the processor, wherein the processor performs the solid state disk address mapping method of any of claims 1-16 when the program is executed.
20. A non-transitory readable storage medium, characterized in that the non-transitory readable storage medium stores a computer program, wherein the computer program, when executed by a processor, performs the solid state disk address mapping method of any one of claims 1-16.
21. A computer program product comprising computer programs/instructions which when executed by a processor implement the solid state disk address mapping method of any of claims 1-16.
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR101297442B1 (en) * | 2013-02-22 | 2013-08-16 | 서울과학기술대학교 산학협력단 | Nand flash memory including demand-based flash translation layer considering spatial locality |
| CN103678166A (en) * | 2013-08-16 | 2014-03-26 | 记忆科技(深圳)有限公司 | Method and system for using solid-state disk as cache of computer |
| CN103902473A (en) * | 2012-12-31 | 2014-07-02 | 华为技术有限公司 | Data processing method and data caching system |
| CN104268094A (en) * | 2014-09-23 | 2015-01-07 | 浪潮电子信息产业股份有限公司 | Optimized flash memory address mapping method |
| CN109739780A (en) * | 2018-11-20 | 2019-05-10 | 北京航空航天大学 | Dynamic secondary based on the mapping of page grade caches flash translation layer (FTL) address mapping method |
-
2024
- 2024-05-14 CN CN202410593446.3A patent/CN118170327A/en active Pending
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103902473A (en) * | 2012-12-31 | 2014-07-02 | 华为技术有限公司 | Data processing method and data caching system |
| KR101297442B1 (en) * | 2013-02-22 | 2013-08-16 | 서울과학기술대학교 산학협력단 | Nand flash memory including demand-based flash translation layer considering spatial locality |
| CN103678166A (en) * | 2013-08-16 | 2014-03-26 | 记忆科技(深圳)有限公司 | Method and system for using solid-state disk as cache of computer |
| CN104268094A (en) * | 2014-09-23 | 2015-01-07 | 浪潮电子信息产业股份有限公司 | Optimized flash memory address mapping method |
| CN109739780A (en) * | 2018-11-20 | 2019-05-10 | 北京航空航天大学 | Dynamic secondary based on the mapping of page grade caches flash translation layer (FTL) address mapping method |
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