CN118135261A - Graph matching method and system for ultra-large scale layout - Google Patents
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Abstract
The invention discloses a pattern matching method and a system of a super-large-scale layout, comprising the following steps: obtaining a layout pattern and a template matching pattern, wherein the template matching pattern comprises a plurality of polygons and a key area mark; surrounding a rectangular frame for each polygon structure of the layout graph; selecting a fixed polygon in the template matching pattern and combining the fixed polygon with the key region mark to form a coarse template matching pattern; obtaining a potential area according to the matching detection of the rough template matching pattern and the layout pattern; and establishing a KD (key distribution) search tree on the layout graph according to the positions of all the potential areas, associating polygons which surround the rectangular frames and intersect with the key area marks of the graph in the branch with the positions of the potential areas, screening the associated polygons, and then matching the polygons with the template matching graph point by point. By using the method, the problems of poor precision, false alarm missing report and the like of complex graph searching in the prior art are solved, high accuracy and low time consumption are realized, and a large amount of searching time cost is saved.
Description
Technical Field
The invention relates to the technical field of image processing, in particular to a pattern matching method and system for a super-large-scale layout.
Background
Defects in the chip manufacturing process are important factors affecting the chip yield, and can be generally classified into systematic defects and non-systematic defects according to the cause. Wherein systematic defects are typically introduced by photolithography, etching, chemical mechanical polishing, etc., and are closely related to the layout.
To locate these hotspot patterns in an integrated circuit layout and to circumvent such hotspot patterns in subsequent tiles, a pattern matching (PATTERN MATCHING) tool is required to locate patterns of a particular structure in increasingly larger-scale layouts. Because it ensures that the design can work normally in actual manufacturing, the conventional DRC (Design Rule Check) tool can only realize pattern search matching with simple structure, and cannot describe complex patterns; for complex graphics, DRC inspection may have false alarm and false miss situations, and the time cost required for searching graphics by existing DRC tools in the industry is high and the speed is slow.
Pattern matching is a widely used technique in the fields of computer science and engineering for finding a specific pattern or object in a pattern or image. This technology relates to a number of fields including computer vision, image processing, pattern recognition and artificial intelligence. In addition to the pattern matching technology, which is considered as the most accurate and rapid detection means in lithography hotspots, the pattern matching technology is widely used in various fields such as standard unit pattern inspection, automatic pattern repair and replacement, and accelerated OPC correction of repeated unit patterns.
In the field of image processing, a plurality of novel algorithms have been created to solve the image processing problem, but the existing image processing algorithms have a plurality of problems, especially related to the image and image matching task, such as large time cost, high computational complexity, complex image matching misjudgment and the like, required by matching images.
By combining with the actual pattern matching problem, the problems existing in the existing matching method are analyzed:
In the grid-dividing gradual matching method, a matching layout and a layout to be matched are finely divided into a plurality of grids, the number of the patterns on the grids is 1, otherwise, the patterns on the grids are 0, searching is performed by converting the patterns into a matrix form, meanwhile, in order to accelerate matching, the matching layout is divided into a plurality of windows or areas, searching is performed in each area by utilizing a sliding window method, and after the area which is possibly matched is found, finer grids are used for fine matching. Such a representation enables finding all matching results, but the matching method is computationally complex and expensive, occupying a lot of computational resources. If the graph has rotation and mirror image changes, the graph needs to be matched with the layout again.
In the partitioning processing, the matching layout is subjected to regional processing, each region comprises a plurality of regions to be matched, the regions to be matched are matched with partial regions on the matching layout, the primary matching is called rough matching, then the conforming rough matching regions and all regions on the layout are subjected to precise matching again, a certain computational complexity can be simplified through a twice matching method, and the computational cost is saved, but when the ultra-large-scale layout is faced, the operation steps of dividing the regions can increase the computational storage cost, the boundary processing problem among the regions is complex, the problem is difficult to solve, and the computational cost of matching is increased.
Disclosure of Invention
The invention aims to provide a pattern matching method and system for a super-large-scale layout aiming at the defects of the prior art.
According to a first aspect of the specification, the object of the invention is achieved by the following technical solutions: a pattern matching method of a super-large scale layout comprises the following steps:
S01, obtaining a layout pattern and a template matching pattern, wherein the layout pattern comprises a plurality of polygons, and the template matching pattern comprises a plurality of polygons and a key region mark;
s02, acquiring main characteristic information of each polygon in the layout graph, and constructing a surrounding rectangular frame for each polygon; selecting a fixed and invariable polygon in the template matching pattern, and combining the polygon with the key region mark to form a coarse template matching pattern;
s03, detecting the matching of the main feature information of the matching pattern of the rough template and the pattern of the layout, wherein the matched pattern is used as a potential area;
S04, building a KD (key distribution) search tree on the layout graph according to the positions of all the potential areas, taking each matching graph of the potential areas as a branch, and dividing the layout graph into a plurality of bounded area spaces according to the branches;
S05, searching for a polygon in the adjacent bounded region space of the KD search tree branch, and if the bounding rectangular frame of the polygon is intersected with the key region mark of the graph in the branch, associating the polygon with the potential region position;
S06, cutting all polygons associated with the potential area based on the boundary of the potential area, and eliminating the graphics outside the key area mark;
S07, comparing the template matching graph with the polygons of each potential area graph point by point, and outputting all the completely matched potential area position coordinates.
Further, the main characteristic information includes a length, a width, and the number of polygon vertices.
Further, in the template matching graph, a plurality of polygons are located in the key region mark, wherein the edge of each polygon is divided into a movable edge or a fixed edge, the moving range of the movable edge is in the key region mark, the movable edge does not overlap with other polygons, and the basic topological structure of the original graph is not changed after the edges move.
Further, the construction enclosure rectangular frame specifically includes: the largest bounding box that can enclose the graph is constructed for each polygon, and the largest bounding box of each polygon is unique and explicitly unchanged, and the enclosing rectangular boxes of multiple polygons are allowed to overlap but do not affect each other.
Furthermore, in the layout pattern matching detection according to the main characteristic information of the rough template matching pattern, the pattern after the polygon in the rough template matching pattern is rotated and mirrored is matched.
Further, the establishing a KD-search tree specifically comprises: each potential area is arranged on an independent branch of the tree, and all branches vertically and horizontally extend and then intersect to form a complete KD search tree, so that the layout graph is divided into a plurality of bounded area spaces.
Further, the judgment that the bounding rectangle of the polygon intersects with the key region mark of the graph in the branch is specifically as follows: substituting potential areas in the polygon, the bounding rectangle frame and the branches into the same coordinate system, and judging:
Wherein, The lower left corner vertex coordinates, (Lx, ly) and (Rx, ry) are the lower left corner coordinates and the upper right corner coordinates of the bounding rectangle, respectively,/>, for the potential region graphAnd/>The lower left corner coordinates and the upper right corner coordinates of the key area marks are respectively marked; if the two conditions are met, the surrounding rectangular frame representing the polygon is intersected with the potential area position, and the polygon is regarded as being associated with the potential area position; otherwise, the relationship is regarded as no relationship.
Further, the cutting all polygons associated with the potential region specifically includes: classifying the edges intersected with the regional boundary, and when the edges are not intersected with the regional boundary, reserving if both ends of the edges are positioned in the key regional marks; discarding if both ends of the edge are outside the key region mark; the edge and region boundary intersect to cut, leaving only the portion within the boundary.
According to a second aspect of the specification, the present invention also provides a pattern matching system for a very large scale layout, the system comprising: the system comprises a layout graphic processing module, a template matching graphic processing module, a KD searching tree module and a graphic matching module;
The layout graph processing module is used for acquiring main characteristic information of each polygon in the layout graph and constructing a surrounding rectangular frame for each polygon;
The template matching pattern processing module is used for selecting a fixed and invariable polygon in the template matching pattern and combining the polygon with the key region mark to form a coarse template matching pattern;
The KD searching tree module is used for establishing a KD searching tree on the layout graph according to the positions of all the potential areas, taking each matching graph of the potential areas as a branch, and dividing the layout graph into a plurality of bounded area spaces according to the branches; searching for a polygon in the adjacent bounded region space of the KD search tree branch, and if the bounding rectangular frame of the polygon intersects with the key region mark of the graph in the branch, associating the polygon with the potential region position;
The pattern matching module is used for detecting the matching of the patterns in the layout according to the main characteristic information of the coarse template matching patterns, and the matched patterns are used as potential areas; cutting all polygons associated with the potential area based on the boundary of the potential area, and eliminating the graphics outside the key area mark; and comparing the template matching graph with the polygons of each potential area graph point by point, and outputting all the completely matched potential area position coordinates.
According to a third aspect of the specification, the invention further provides a pattern matching device of the super-large-scale layout, which comprises a memory and one or more processors, wherein executable codes are stored in the memory, and the pattern matching method of the super-large-scale layout is realized when the executable codes are executed by the processors.
The invention has the beneficial effects that:
compared with the existing technologies such as pattern matching, the method and the device can realize lower calculation cost by using fewer calculation resources, and have high matching response speed.
The method for establishing the rough template matching graph can describe the common characteristics of various Manhattan polygons to the greatest extent, and reduces the calculation memory and calculation cost for characteristic reading and storage. The method provided by the invention considers complex matching patterns such as rotation, mirror image and the like at the beginning, can also completely respond and match, and does not need to re-match as in the prior art.
The KD lookup tree for establishing the coarse template matching patterns can realize the rapid reduction of the number of the matching patterns, greatly reduce the pattern detection calculation time, and is more suitable for a mask layout with ultra-large scale.
Drawings
FIG. 1 is a schematic flow chart of a pattern matching method for a very large scale layout provided by an embodiment of the invention;
FIG. 2 is a schematic diagram of a small layout according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a large-scale layout formed by a plurality of small layouts provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of a template matching pattern according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a rotated and mirrored template matching pattern provided by an embodiment of the present invention;
FIG. 6 is a schematic diagram of feature extraction of polygons in a layout pattern and a template matching pattern provided by an embodiment of the present invention;
FIG. 7 is a schematic diagram of a combined coarse template matching pattern according to an embodiment of the present invention;
FIG. 8 is a schematic diagram of a coarse template matching pattern in a layout pattern according to an embodiment of the present invention;
FIG. 9 is a simplified schematic diagram of a KD lookup tree built from a coarse template matching pattern provided in an embodiment of the present invention;
FIG. 10 is a schematic diagram of the location of a potential area after association provided by an embodiment of the present invention;
FIG. 11 is a schematic diagram of the results of classifying potential regions according to an embodiment of the present invention;
FIG. 12 is a schematic diagram of the results of a polygon classification provided by an embodiment of the present invention;
FIG. 13 is a schematic view of the results of classification cut provided by an embodiment of the present invention;
FIG. 14 is a schematic diagram of a result of a partial template matching pattern obtained by complete matching in a layout pattern provided by an embodiment of the present invention;
FIG. 15 is a schematic diagram of a pattern matching device for a very large scale layout according to an embodiment of the present invention.
Detailed Description
The embodiment of the invention provides a pattern matching method of a super-large-scale layout, which is used for making the purposes, technical schemes and advantages of the embodiment of the invention clearer and more definite, and is further described in detail below with reference to the accompanying drawings and the detailed description. The described embodiments of the invention are only some, but not all, of the embodiments of the invention. Other embodiments similar to those described herein are within the scope of the present invention.
Referring to the flowchart of fig. 1, this embodiment provides a pattern matching method for a very large scale layout, including:
And S01, obtaining a layout pattern and a template matching pattern, wherein the layout pattern comprises a plurality of polygons, and the template matching pattern comprises a plurality of polygons and a key area mark (rectangular frame).
Further, step S01 includes:
the layout pattern is composed of a plurality of Manhattan polygons (hereinafter referred to as polygons) and the number of the layout patterns is far more than that of template matching patterns. As shown in fig. 2, fig. 2 is an example of a small layout composed of 5 polygons, the vertex coordinates of each polygon are connected in a counterclockwise manner to describe the polygons, the vertex coordinates of each polygon are denoted as { (x 1,y1),(x2,y2),...,(xn,yn) }, and all the polygons are described in a rectangular coordinate system, where n represents the number of polygon vertices.
In this embodiment, a very Large scale Layout (Large Layout) with 200 ten thousand polygons is used, and as shown in fig. 3, the Layout is composed of a plurality of small layouts as described above, and is a design drawing of an actual integrated circuit mask Layout. In other embodiments, the layout pattern may have a greater number of polygons.
The template matching pattern is composed of several polygons and a key region mark (hereinafter simply referred to as a mark rectangle), which is composed of 6 polygons, the vertex coordinates of each polygon being connected counterclockwise, the vertex coordinates of each polygon being represented as { (i 1,j1),(i2,j2),...,(in,jn) }, where n represents the number of polygon vertices, all of which are described in a rectangular coordinate system, as shown in fig. 4, where (i 1,j1) is marked as the origin. The marked rectangular frame is connected counterclockwise from the lower left corner coordinate, and is denoted as { (l 1,k1),(l2,k2),(l3,k3),(l4,k4) }. The sides of the polygons in the marked rectangular frame are allowed to move, but each polygon has at most 1 allowed movable side, and the rest sides are fixed sides, so that each polygon has one variable side; or there are no variable edges, all fixed edges. The allowable moving range of the edges is in the marked rectangular frame, but the edges are not allowed to overlap with other polygons, and the basic topological structure of the original graph is not changed after the edges move, namely the number of the edges and the number of the top points of the polygons are not changed.
The allowable movement of two sides of two polygons is given below, as the hatched portion in the figure represents the allowable movement range of the variable side, where the allowable movement range is still calculated as a part of the polygon. Further, these polygons are surrounded by a peripheral marked rectangular frame, and the sides of all polygons fall within or coincide with the marked rectangular frame.
In this embodiment, the layout pattern includes a plurality of forward template matching patterns, and in addition to complete forward matching, the layout pattern may also include rotated and mirrored template matching patterns, because the circuit mask layout has the characteristics of high repetition and dense arrangement. Fig. 5 shows a simple illustration of one of the cases, in which the pattern is formed by rotating the positive template matching pattern 90 degrees to the right. In addition, other complex conditions such as rotation angles, mirror images and the like are not shown in detail, and 8 conditions are found after each 90-degree rotation, horizontal mirror image inversion and vertical mirror image inversion.
In this embodiment, the template matching pattern has rotation and mirror image conditions, and polygons in the template matching pattern have variable edges, which all need to be detected in the layout pattern to be regarded as obtaining a completely correct matching result. In other embodiments, the stencil-matching pattern may not be rotated, mirrored, and the sides of the polygon may be unchanged.
S02, processing the layout graph to obtain main characteristic information of each polygon; and processing the template matching pattern, selecting a fixed and invariable polygon, and combining the polygon with the key region mark to form a coarse template matching pattern.
In this embodiment, step S02 specifically includes: the polygons of the layout patterns show characteristics of complex shapes and unequal sizes, so that the main characteristics of all the polygons need to be extracted, and the digital coordinate information of the layout files is converted into available space coordinate information, so that the matching patterns of the matching templates can be conveniently matched later. First, a maximum bounding box that can enclose the graphic is constructed for each polygon, the maximum bounding box of each polygon being unique and explicitly unchanged, called an enclosing rectangular box, and the enclosing rectangular boxes of multiple polygons are allowed to overlap but do not affect each other.
The structure surrounding rectangular frame has the advantages that the corresponding relation between the template matching graph and the layout graph can be established, and the potential matching area of the template matching graph can be quickly found.
In the present embodiment, a polygon feature extraction diagram is provided, and as shown in FIG. 8, a bounding rectangular frame (black rectangular frame in the figure) is described by lower left corner coordinates LL (Lx, ly) and upper right corner coordinates UR (Rx, ry), the length and width of which are W, H, and the number of vertices of the polygon is 8, and the coordinates of all the points are also recorded {(x1,y1),(x2,y2),(x3,y3),...,(x8,y8)}.
The method for calculating the length and the width of the surrounding rectangular frame comprises the following steps:
fig. 3 and 4 are schematic diagrams of embodiments of the present invention. The matching method is described in detail below with reference to fig. 3 and 4.
Providing a Layout pattern Layout (shown in figure 3) and a template matching pattern (shown in figures 4 and 5), wherein the Layout pattern comprises a plurality of forward, rotating and mirror template matching patterns.
In this embodiment, a polygon with all sides in the marked rectangular frame and no variable sides is selected first, because the polygon features are stable and simple, there is no intersecting condition of the marked rectangular frame, there is no pattern segmentation or change condition, and the final matching result must include the complete polygon. In other embodiments, if there is a variable edge for each polygon, then a polygon is selected that has a variable edge or a portion of edges that coincide with the marked rectangular box.
As shown in FIG. 7, this embodiment selects a square whose sitting sign is { (i 1,j1),(i2,j2),(i3,j3),(i4,j4) }, which is combined with a marked rectangular frame to form a coarse template matching pattern.
And S03, detecting the matching of the layout pattern according to the length and width dimensions of the rough template matching pattern and the number of polygon vertexes, wherein all the matched patterns form a rough matching pattern library, and the positions are called potential areas.
In this embodiment, step S03 specifically includes:
According to the above selected length W, width H dimensions (w=h) and 4 top points of the square, the three features are detected and searched in the layout graph, the positions of polygons which all conform to the three features are 6, the schematic result diagram after searching in the layout is shown in fig. 8 finally, all detected graphics in the layout form a rough matching graph library, the 6 positions are called potential areas, and the square position coordinates obtained by detection at the 6 positions can be described as ,/> ,…,/>The coordinates of the marked rectangular frame corresponding thereto can be described as
All its coordinate sets are denoted P.
In this embodiment, the patterns after rotation and mirroring of the square are also searched, and the feature patterns to be searched actually are 8, but in this embodiment, the square is a highly symmetrical pattern, so only one feature pattern needs to be searched. In other embodiments, all variations of the non-highly symmetric pattern need to be considered.
And step S04, building a KD-search Tree (K-Dimension Tree) according to the positions of all the potential areas.
In this embodiment, step S04 includes: establishing a KD searching tree according to the square central coordinates of the 6 potential area positions obtained by the detection, wherein the 6 square central coordinates are described asWherein n represents 1,2,..6. As a result, as shown in FIG. 9, each potential region position is on a single branch of the tree, 6 branches of the tree are shared, each branch extends vertically and horizontally and then is intersected to form a complete KD search tree, the layout graph is divided into 7 bounded region spaces, each branch is only related to two bounded region spaces adjacent to the left side and the right side of the branch or adjacent to the right side and the left side and the right side of the branch, each branch is independent of each other and does not affect each other, for example, the branch at the 1 st potential region position at the top of FIG. 9 is only related to the two bounded region spaces at the left side and the right side of the branch. According to the above-described divided 7 bounded area spaces, all polygons in the layout pattern are divided into fixed bounded area spaces, and surrounding rectangular frames intersect branches while belonging to two adjacent bounded area spaces. Therefore, according to the constructed KD tree, the polygons in each bounded region space are only related to the nearby branches, and the range that each branch in the KD searching tree can allow searching is only in the range of two adjacent bounded region spaces, so that the searching range of the graph to be matched is simplified to the greatest extent.
And S05, utilizing a KD tree searching algorithm to correlate and classify the potential area position on the branch and the polygon intersected with the branch.
Further, step S05 includes:
In this embodiment, the above-mentioned established KD lookup tree divides the bounded area space by establishing branches, so as to complete the division of the relative space positions of the layout polygons, and reduce the range of each branch for searching the graphics to be matched according to the potential area positions.
Next, the potential region locations on the branch and the polygons intersecting the branch are first correlated and categorized, narrowing the search more recently. Taking the 1 st branch at the top of the KD search tree as an example, the two adjacent bounded area spaces of the branch contain a large number of polygons, but only the polygons near the two sides of the position of the potential area of the branch and the vicinity thereof can be graphics to be searched in a matching way, and the polygons with the space positions far relative to the position of the potential area on the branch are not in the searching range, so that the polygons in the two bounded area spaces need to be judged, and the polygons need to be intersected and associated with the position of the potential area of the branch. Since the bounding rectangle of the polygon has been established above, the problem of determining whether the polygon intersects with the potential region position is converted into the problem of determining whether the bounding rectangle of the polygon intersects with the potential region position, and the problem can be converted into the problem of determining whether the two rectangles intersect, which is determined according to the following criteria:
Wherein n represents 1,2, & gt, 6. The condition judgment is carried out on all polygons in two bounded area spaces, if the two conditions are met, the surrounding rectangular frame of the polygon is intersected with the potential area position, and the polygon is regarded as being associated with the potential area position; otherwise, the relationship is regarded as no relationship. As shown in fig. 10, a schematic diagram of the associated potential zone locations is provided.
Second, the associated polygons need to be categorized into the potential region that intersects with it, because not all subsequent associated polygons need to be cut, polygons outside the boundary of the potential region need to be culled, and the graphics that intersect with or are inside the boundary remain.
The basis of the classification is that any one of four coordinate values L [ x ], L [ y ], R [ x ], R [ y ] of a polygon surrounding a rectangular frame is in the range of P, and as shown in FIG. 11, a schematic diagram of the result after the classification is given, wherein the diagram is a reserved polygon.
In this embodiment, the method uses KD tree search algorithm to correlate polygons, so as to realize the sudden drop of the number of graphics to be detected and the sudden drop of the time for detecting the matched graphics, which is also the greatest advantage of the method of the present invention.
And S06, cutting all polygons associated with the potential area based on the boundary of the potential area, and eliminating the graphics outside the key area mark.
Further, step S06 includes:
In this embodiment, in the classified potential region, some polygons intersect with the region boundary, so that the pattern needs to be cut and then compared with the template matching pattern. Cutting the pattern is cutting the edges of the pattern, and converting the problem into cutting the edges is easier.
All edges intersecting the region boundary are classified, and accurate cutting of the edges according to the classification criteria is easier, and no miscut or miscut occurs. Fig. 12 shows a schematic view of all edge classifications, for a total of 4, the criteria for classification are as follows:
(1) The edges and region boundaries do not intersect, there are two cases:
Edges are from inside to inside and belong to class 1 edges;
the edges are from outside to outside and belong to class 3 edges;
(2) The edges intersect the region boundaries in two cases:
Edges are from inside to outside (outside of the region and boundary), belonging to class 2 edges;
edges are from outside (outside of the region and boundary) to inside, belonging to class 4;
In this embodiment, it is obvious according to the classification criterion that the class 1 edge and the class 3 edge do not have the intersecting condition, wherein the class 1 edge is completely inside the boundary and is completely reserved; class 3 edges are completely outside the boundary and do not belong to the template matching pattern, and are removed. If there is an intersection between class 2 and class 4 edges, then a cut is required, leaving only the portion within the boundary (including the boundary).
Finally, cutting the graph according to the graph classification rule, and fig. 13 shows the effect schematic diagram after the cutting of fig. 11. All polygonal parts outside the boundary in the figure have been removed, the figure inside the boundary is preserved, and the size and the spatial relative coordinate position are not changed.
And S07, comparing the template matching graph with the polygons of each potential area graph point by point, and outputting all the completely matched potential area position coordinates.
Further, step S07 includes:
Thus far, in the present embodiment, the detection of the positions of all the potential areas is completed, and the cutting of the polygons in the potential areas is completed, and in this step, only the coordinates of the polygons in each template matching pattern and the potential area pattern need to be compared point by point, specifically described as whether the corresponding differences of { (i 1,j1),(i2,j2),...,(in,jn) } and { (x 1,y1),(x2,y2),...,(xn,yn) } are completely equal, that is, if the comparison x1-i1 , y1-j1 , x2-i2, y2-j2,… , xn-in, yn-jn. is x1-i1 = y1-j1 = x2-i2 = y2-j2,… , xn-in = yn-jn,, the potential areas are regarded as template matching patterns, and the coordinates {(l1+x1,k1+y1),(l2+x1,k2+y1),(l3+x1,k3+y1),(l4+x1,k4+y1)}, of the marked rectangular frames are recorded, and the marked rectangular frames of the template matching patterns are generated relative to the origin coordinates of (i 1,j1), so that the positions where the layout matching is successful become the coordinates relative to (x 1,y1) plus the offset; otherwise, any difference value is not equal, and is regarded as unmatched, and the place is abandoned. As shown in FIG. 14, a schematic diagram of a part of template matching patterns obtained by complete matching in the layout patterns is provided, the left side of FIG. 14 is a forward matching pattern, and the right side is a matching pattern after mirror rotation by 180 degrees. After all matching is completed, the position coordinates of all template matching patterns are recorded, the set of which is denoted as P matched, and the number of all template matching patterns is denoted as N_P matched.
In other embodiments, not all of the layout patterns may be matched to find a template matching pattern under the rotation and mirroring conditions, particularly a non-highly repetitive, non-highly complex layout pattern.
Corresponding to the embodiment of the pattern matching method of the super-large-scale layout, the embodiment also provides a pattern matching system of the super-large-scale layout, which comprises: the system comprises a layout graphic processing module, a template matching graphic processing module, a KD searching tree module and a graphic matching module;
The layout graph processing module is used for acquiring main characteristic information of each polygon in the layout graph and constructing a surrounding rectangular frame for each polygon;
The template matching pattern processing module is used for selecting a fixed and invariable polygon in the template matching pattern and combining the polygon with the key region mark to form a coarse template matching pattern;
The KD searching tree module is used for establishing a KD searching tree on the layout graph according to the positions of all the potential areas, taking each matching graph of the potential areas as a branch, and dividing the layout graph into a plurality of bounded area spaces according to the branches; searching for a polygon in the adjacent bounded region space of the KD search tree branch, and if the bounding rectangular frame of the polygon intersects with the key region mark of the graph in the branch, associating the polygon with the potential region position;
The pattern matching module is used for detecting the matching of the patterns in the layout according to the main characteristic information of the coarse template matching patterns, and the matched patterns are used as potential areas; cutting all polygons associated with the potential area based on the boundary of the potential area, and eliminating the graphics outside the key area mark; and comparing the template matching graph with the polygons of each potential area graph point by point, and outputting all the completely matched potential area position coordinates.
Corresponding to the embodiment of the pattern matching method of the super-large-scale layout, the invention also provides an embodiment of the pattern matching device of the super-large-scale layout.
Referring to fig. 15, a pattern matching device for a very large scale layout according to an embodiment of the present invention includes a memory and one or more processors, where executable codes are stored in the memory, and when the processor executes the executable codes, the processor is configured to implement a pattern matching method for a very large scale layout in the foregoing embodiment.
The embodiment of the pattern matching device of the ultra-large scale layout can be applied to any equipment with data processing capability, and the equipment with the data processing capability can be equipment or a device such as a computer. The apparatus embodiments may be implemented by software, or may be implemented by hardware or a combination of hardware and software. Taking software implementation as an example, the device in a logic sense is formed by reading corresponding computer program instructions in a nonvolatile memory into a memory by a processor of any device with data processing capability. In terms of hardware, as shown in fig. 15, a hardware structure diagram of an apparatus with any data processing capability where a pattern matching device for a very large-scale layout provided by the present invention is located is shown in fig. 15, and in addition to a processor, a memory, a network interface, and a nonvolatile memory shown in fig. 15, any apparatus with any data processing capability where an embodiment is located generally includes other hardware according to an actual function of the apparatus with any data processing capability, which is not described herein again.
The implementation process of the functions and roles of each unit in the above device is specifically shown in the implementation process of the corresponding steps in the above method, and will not be described herein again.
For the device embodiments, reference is made to the description of the method embodiments for the relevant points, since they essentially correspond to the method embodiments. The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purposes of the present invention. Those of ordinary skill in the art will understand and implement the present invention without undue burden.
The embodiment of the invention also provides a computer readable storage medium, on which a program is stored, which when executed by a processor, implements a pattern matching method for a very large-scale layout in the above embodiment.
The computer readable storage medium may be an internal storage unit, such as a hard disk or a memory, of any of the data processing enabled devices described in any of the previous embodiments. The computer readable storage medium may also be an external storage device of any device having data processing capabilities, such as a plug-in hard disk, a smart memory card (SMART MEDIA CARD, SMC), an SD card, a flash memory card (FLASH CARD), etc. provided on the device. Further, the computer readable storage medium may include both internal storage units and external storage devices of any data processing device. The computer readable storage medium is used for storing the computer program and other programs and data required by the arbitrary data processing apparatus, and may also be used for temporarily storing data that has been output or is to be output.
Those skilled in the art will appreciate that the drawings are schematic representations of only one preferred embodiment, and that the above-described embodiment numbers are merely for illustration purposes and do not represent advantages or disadvantages of the embodiments.
The above-described embodiments are intended to illustrate the present invention, not to limit it, and any modifications and variations made thereto are within the spirit of the invention and the scope of the appended claims.
Claims (10)
1. The pattern matching method of the ultra-large scale layout is characterized by comprising the following steps of:
S01, obtaining a layout pattern and a template matching pattern, wherein the layout pattern comprises a plurality of polygons, and the template matching pattern comprises a plurality of polygons and a key region mark;
s02, acquiring main characteristic information of each polygon in the layout graph, and constructing a surrounding rectangular frame for each polygon; selecting a fixed and invariable polygon in the template matching pattern, and combining the polygon with the key region mark to form a coarse template matching pattern;
s03, detecting the matching of the main feature information of the matching pattern of the rough template and the pattern of the layout, wherein the matched pattern is used as a potential area;
S04, building a KD (key distribution) search tree on the layout graph according to the positions of all the potential areas, taking each matching graph of the potential areas as a branch, and dividing the layout graph into a plurality of bounded area spaces according to the branches;
S05, searching for a polygon in the adjacent bounded region space of the KD search tree branch, and if the bounding rectangular frame of the polygon is intersected with the key region mark of the graph in the branch, associating the polygon with the potential region position;
S06, cutting all polygons associated with the potential area based on the boundary of the potential area, and eliminating the graphics outside the key area mark;
S07, comparing the template matching graph with the polygons of each potential area graph point by point, and outputting all the completely matched potential area position coordinates.
2. The pattern matching method of a very large scale layout according to claim 1, wherein said main feature information includes a length, a width, and the number of polygon vertices.
3. The pattern matching method of a very large scale layout according to claim 1, wherein in the template matching pattern, a plurality of polygons are located in a key region mark, wherein the edge of each polygon is divided into a movable edge or a fixed edge, the movable range of the movable edge is within the key region mark, the movable edge does not overlap with other polygons, and the basic topology of the original pattern is not changed after the edges are moved.
4. The pattern matching method of a very large scale layout according to claim 1, wherein said constructing an bounding rectangle specifically comprises: the largest bounding box that can enclose the graph is constructed for each polygon, and the largest bounding box of each polygon is unique and explicitly unchanged, and the enclosing rectangular boxes of multiple polygons are allowed to overlap but do not affect each other.
5. The pattern matching method of a very large scale layout according to claim 1, wherein in the layout pattern matching detection according to the main feature information of the rough template matching pattern, the pattern after the polygon in the rough template matching pattern is rotated and mirrored is also required to be matched.
6. The pattern matching method of a very large scale layout according to claim 1, wherein the building of the KD-lookup tree is specifically: each potential area is arranged on an independent branch of the tree, and all branches vertically and horizontally extend and then intersect to form a complete KD search tree, so that the layout graph is divided into a plurality of bounded area spaces.
7. The pattern matching method of a very large scale layout according to claim 1, wherein the judgment of intersection of the bounding rectangular frame of the polygon and the key region mark of the pattern in the branch is specifically as follows: substituting potential areas in the polygon, the bounding rectangle frame and the branches into the same coordinate system, and judging:
；
Wherein, The lower left corner vertex coordinates, (Lx, ly) and (Rx, ry) are the lower left corner coordinates and the upper right corner coordinates of the bounding rectangle, respectively,/>, for the potential region graphAnd/>The lower left corner coordinates and the upper right corner coordinates of the key area marks are respectively marked; if the two conditions in the formula are met at the same time, the surrounding rectangular frame of the polygon is intersected with the potential area position, and the polygon is regarded as being associated with the potential area position; otherwise, the relationship is regarded as no relationship.
8. The pattern matching method of a very large scale layout according to claim 1, wherein said cutting all polygons associated with potential regions specifically comprises: classifying the edges intersected with the regional boundary, and when the edges are not intersected with the regional boundary, reserving if both ends of the edges are positioned in the key regional marks; discarding if both ends of the edge are outside the key region mark; the edge and region boundary intersect to cut, leaving only the portion within the boundary.
9. A pattern matching system for a very large scale layout, the system comprising: the system comprises a layout graphic processing module, a template matching graphic processing module, a KD searching tree module and a graphic matching module;
The layout graph processing module is used for acquiring main characteristic information of each polygon in the layout graph and constructing a surrounding rectangular frame for each polygon;
The template matching pattern processing module is used for selecting a fixed and invariable polygon in the template matching pattern and combining the polygon with the key region mark to form a coarse template matching pattern;
The KD searching tree module is used for establishing a KD searching tree on the layout graph according to the positions of all the potential areas, taking each matching graph of the potential areas as a branch, and dividing the layout graph into a plurality of bounded area spaces according to the branches; searching for a polygon in the adjacent bounded region space of the KD search tree branch, and if the bounding rectangular frame of the polygon intersects with the key region mark of the graph in the branch, associating the polygon with the potential region position;
The pattern matching module is used for detecting the matching of the patterns in the layout according to the main characteristic information of the coarse template matching patterns, and the matched patterns are used as potential areas; cutting all polygons associated with the potential area based on the boundary of the potential area, and eliminating the graphics outside the key area mark; and comparing the template matching graph with the polygons of each potential area graph point by point, and outputting all the completely matched potential area position coordinates.
10. A pattern matching device for a very large scale layout, comprising a memory and one or more processors, wherein executable code is stored in the memory, and wherein the processor implements a pattern matching method for a very large scale layout according to any one of claims 1-8 when executing the executable code.
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Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015040657A1 (en) * | 2013-09-20 | 2015-03-26 | 富士通株式会社 | Image processing device, image processing method, and image processing program |
| CN104572682A (en) * | 2013-10-17 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for area indexing of integrated circuit layout data |
| US20160117795A1 (en) * | 2014-10-27 | 2016-04-28 | Fu Tai Hua Industry (Shenzhen) Co., Ltd. | Point cloud data processing system and method thereof and computer readable storage medium |
| CN107481276A (en) * | 2016-06-08 | 2017-12-15 | 北京天智航医疗科技股份有限公司 | The automatic identifying method of mark point sequence in a kind of 3 d medical images |
| CN111754479A (en) * | 2020-06-22 | 2020-10-09 | 上海华力微电子有限公司 | Checking method for accurate matching of layout graphs |
| US10813715B1 (en) * | 2019-10-16 | 2020-10-27 | Nettelo Incorporated | Single image mobile device human body scanning and 3D model creation and analysis |
| WO2023134309A1 (en) * | 2022-01-14 | 2023-07-20 | 深圳晶源信息技术有限公司 | Mask layout correction method |
| CN117891143A (en) * | 2024-02-21 | 2024-04-16 | 广东工业大学 | Photoetching hot spot detection method based on 2D overlapping judgment |
-
2024
- 2024-05-06 CN CN202410547698.2A patent/CN118135261A/en active Pending
Patent Citations (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO2015040657A1 (en) * | 2013-09-20 | 2015-03-26 | 富士通株式会社 | Image processing device, image processing method, and image processing program |
| CN104572682A (en) * | 2013-10-17 | 2015-04-29 | 上海华虹宏力半导体制造有限公司 | Method for area indexing of integrated circuit layout data |
| US20160117795A1 (en) * | 2014-10-27 | 2016-04-28 | Fu Tai Hua Industry (Shenzhen) Co., Ltd. | Point cloud data processing system and method thereof and computer readable storage medium |
| CN107481276A (en) * | 2016-06-08 | 2017-12-15 | 北京天智航医疗科技股份有限公司 | The automatic identifying method of mark point sequence in a kind of 3 d medical images |
| US10813715B1 (en) * | 2019-10-16 | 2020-10-27 | Nettelo Incorporated | Single image mobile device human body scanning and 3D model creation and analysis |
| CN111754479A (en) * | 2020-06-22 | 2020-10-09 | 上海华力微电子有限公司 | Checking method for accurate matching of layout graphs |
| WO2023134309A1 (en) * | 2022-01-14 | 2023-07-20 | 深圳晶源信息技术有限公司 | Mask layout correction method |
| CN117891143A (en) * | 2024-02-21 | 2024-04-16 | 广东工业大学 | Photoetching hot spot detection method based on 2D overlapping judgment |
Non-Patent Citations (1)
| Title |
|---|
| 史峥;高晓莹;任杰;施怡雯;: "集成电路版图中的多边形匹配比较研究", 机电工程, no. 10, 20 October 2007 (2007-10-20) * |
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