CN118133770A - Design method of high-speed Ethernet signal test board for embedded system - Google Patents
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Abstract
The invention provides a design method of a high-speed Ethernet signal test board for an embedded system, which comprises the following steps: establishing an initial model of the test board according to the signal transmission requirement of the verified system; simplifying the passive test transmission link in the test board initial model, and simplifying the analog connector of the test board initial model by using the simplified passive test transmission link to obtain a once simplified test board model; designing an active test transmission link of the once simplified test board model to obtain a test board model; preparing a test board by using a test board model, optimizing signals of an anti-bonding pad and a back drill of the test board, and performing disc cutting treatment on a non-functional bonding pad of the test board to obtain a final test board; and performing active test and passive test on the final test board by using the high-speed Ethernet signal testing device. The design method of the invention provides reliable data support for system design, and better realizes the high-speed interconnection function of the embedded system.
Description
Technical Field
The invention belongs to the field of embedded computers, relates to an Ethernet signal test design technology, and in particular relates to a method for designing a high-speed Ethernet signal test board for an embedded system.
Background
In the field of embedded computers, with the proliferation of data to be processed, a high-performance data exchange and information processing system including multiple modules, that is, an embedded computer system is generally constructed by using a backplane connection, and each module in the embedded computer system is interconnected at a high speed through the backplane. However, as the rates on the ethernet signal single-pair differential lines have reached above 25Gbps, tight control of transmission channel loss and impedance continuity presents a significant challenge.
Meanwhile, because the embedded computer system has high-speed Ethernet links with various transmission conditions and comprises various nonstandard connectors, and different boards and wiring modes are combined, the simulation of the high-speed signals is not enough to provide enough data support for the design of the signal links in the system demonstration stage, and therefore the high-speed signal test board is required to be designed for verifying the embedded computer system so as to avoid influencing the high-speed signal transmission of the system due to the signal quality problem.
Therefore, how to design a high-speed ethernet signal test board in the system demonstration stage to provide reliable data support for the design of a high-speed signal transmission link becomes a problem to be solved.
Disclosure of Invention
In order to provide reliable data support for the design of a high-speed signal transmission link in the demonstration stage of an embedded computer system, the invention discloses a design method of a high-speed Ethernet signal test board for an embedded system.
The technical scheme for realizing the aim of the invention is as follows: a design method of a high-speed Ethernet signal test board for an embedded system comprises the following steps:
s1, establishing a test board initial model according to signal transmission requirements of a verified system, wherein the test board initial model comprises an analog connector and transmission links, and each transmission link comprises a connector series and a link length;
S2, simplifying the passive test transmission link in the initial test board model according to the connector series and the link length, and simplifying the analog connector of the initial test board model by using the simplified passive test transmission link to obtain a once-simplified test board model;
S3, designing the active test transmission link of the once simplified test board model according to the long transmission link in the transmission link to obtain a test board model;
s4, preparing a test board by using the test board model, performing signal optimization on an anti-bonding pad and a back drill of the test board by adopting a high-speed signal simulation technology, and performing disc cutting treatment on a non-functional bonding pad of the test board to obtain a final test board;
s5, performing active test and passive test on the final test board through the high-speed Ethernet signal testing device.
Further, in the step S1, the establishing the initial model of the test board according to the signal transmission requirement of the verified system includes:
s11, analyzing the verified system, obtaining each connector model, each simulation device and each test board by using the analysis, and establishing a test board general model;
s12, counting all transmission links according to the information processing requirement of the verified system, wherein the transmission links comprise passive test transmission links and active test transmission links;
S13, placing each passive test transmission link and each active test transmission link into the test board general model, and establishing to obtain the test board initial model.
Further, in the step S11, the test board universal model includes an analog connector, an analog daughter card, an analog carrier board and an analog backplane, wherein the analog daughter card and the analog carrier board form an embedded module, and a plurality of the embedded modules are interconnected in the analog backplane at a high speed through the transmission link.
Further, in the step S12, the type of the transmission link includes a first transmission link and a second transmission link, where the first transmission link is a link in the authenticated system for completing ethernet information exchange through an electrical signal, and the second transmission link is a link in the authenticated system for converting the electrical signal into an optical signal.
Further, in the step S2, the simplifying the passive test transmission link in the test board initial model according to the connector stage number and the link length, and using the simplified passive test transmission link to simplify the analog connector of the test board initial model to obtain a simplified test board model, including:
S21, according to the connector series and the link length, using a set series threshold value and a link length threshold value, and simplifying the passive test transmission link to obtain a simplified test board initial model;
S22, modifying the signal definition of the analog connector passed by each passive test transmission link in the simplified test board initial model, and simplifying the number of the analog connectors, the analog daughter cards, the analog carrier boards and the analog backboard of the simplified test board initial model to obtain the one-time simplified test board model.
Further, in the step S3, the step of designing the active test transmission link of the once simplified test board model according to the long transmission link in the transmission links to obtain a test board model includes:
S31, by adjusting the passive test signal definition of the analog connector in the one-time simplified test board model, the passive test signal definition is different from the definition of a signal emission source adopting an FPGA daughter card as the active test transmission link;
S32, setting photoelectric transceivers on a simulation carrier plate and a simulation backboard of the once simplified test board model for each long transmission link to obtain an initial active test link of each long transmission link, and carrying out self-loop test on each long transmission link by adopting a high-speed Ethernet signal;
s33, setting a driver circuit for the long transmission link according to a self-loop test result, and completing the design of the active test transmission link of the once-simplified test board model to obtain the test board model.
Further, in the step S32, the long transmission link includes a connector with a connector number greater than or equal to 2 and a transmission link with a link length greater than or equal to a set length.
Further, in the step S32, the performing the self-loop test on each long transmission link by using the high-speed ethernet signal includes:
s321, loading the I BERT logic on line in the FPGA daughter card;
S322, transmitting set quantity data in the long transmission link corresponding to the photoelectric transceiver, recording the error rate and generating an electronic eye pattern for self-loop test.
Compared with the prior art, the beneficial effects that above-mentioned at least one technical scheme that this description embodiment adopted can reach include at least: the invention designs a high-speed Ethernet signal test board for an embedded system by carrying out design on an active transmission link and a passive transmission link to obtain a test board model, preparing the test board by using the test board model, and carrying out signal optimization by adopting a high-speed signal simulation technology to obtain a final test board. In the method, on one hand, in the system demonstration stage, a high-speed Ethernet signal test board is designed according to the connector selection, plates, specific transmission link conditions and the like, and the specific design of the system is guided according to the test result, so that design errors related to high-speed signal transmission are avoided, and the high-speed signal transmission quality is effectively ensured; on the other hand, by adding a driver circuit and a signal quality optimization design in the signal test board, the effectiveness of signal quality optimization measures under specific conditions is demonstrated, the signal transmission quality of a long-chain high-speed Ethernet in an embedded system is improved, and a high-performance data exchange and information processing system is constructed.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings that are needed in the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present application, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of a method for designing a high-speed Ethernet signal test board for an embedded system according to an embodiment of the invention;
FIG. 2 is a simplified schematic diagram of a passive test transmission link according to an embodiment of the present invention;
FIG. 3 is a simplified schematic diagram of an active test transmission link according to an embodiment of the present invention;
Fig. 4 is a schematic diagram of a high-speed ethernet signal testing apparatus according to an embodiment of the present invention.
Detailed Description
Embodiments of the present application will be described in detail below with reference to the accompanying drawings.
Other advantages and effects of the present application will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present application with reference to specific examples. It will be apparent that the described embodiments are only some, but not all, embodiments of the application. The application may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present application. It should be noted that the following embodiments and features of the embodiments may be combined with each other without conflict. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The embodiment of the invention discloses a method for designing a high-speed Ethernet signal test board for an embedded system, which is shown in fig. 1 and comprises the following steps:
s1, establishing a test board initial model according to signal transmission requirements of a verified system, wherein the test board initial model comprises an analog connector and transmission links, and each transmission link comprises a connector series and a link length;
S2, simplifying the passive test transmission link in the initial test board model according to the connector series and the link length, and simplifying the analog connector of the initial test board model by using the simplified passive test transmission link to obtain a once-simplified test board model;
S3, designing the active test transmission link of the once simplified test board model according to the long transmission link in the transmission link to obtain a test board model;
s4, preparing a test board by using the test board model, performing signal optimization on an anti-bonding pad and a back drill of the test board by adopting a high-speed signal simulation technology, and performing disc cutting treatment on a non-functional bonding pad of the test board to obtain a final test board;
s5, performing active test and passive test on the final test board through the high-speed Ethernet signal testing device.
Further, in the step S1, the establishing the initial model of the test board according to the signal transmission requirement of the verified system includes:
S11, analyzing the verified system, obtaining each connector model, each simulation device and each test board by using the analysis, and establishing a test board general model. During implementation, the selection of the plates and the connectors is required, wherein the plates directly influence the loss of the transmission channel, the proper high-speed plates are usually selected according to the condition of the high-speed signal transmission link, the connector types directly influence the insertion loss of the high-speed electric signals through the primary connector, and the high-speed Ethernet signal test plate model can be preliminarily determined according to the plates and the connector types. Meanwhile, the size of the test board and the layout of the analog devices are determined by the device pre-layout and the high-speed signal transmission links in the system design, the layout of the analog devices is required to imitate the device pre-layout position for completing high-speed signal receiving and transmitting in the system design, and because a plurality of high-speed signal transmission links with different lengths exist, the space for signal winding is required to be reserved on the test board so as to cover the link tests with different lengths.
S12, counting all transmission links according to the information processing requirement of the verified system, wherein the transmission links comprise passive test transmission links and active test transmission links.
In specific implementation, the passive test transmission link comprises two typical test links, one is a first transmission link, which is from a high-speed Serdes chip to a high-speed Serdes chip, namely, a transmitting end and a receiving end of a high-speed signal are both high-speed Serdes chips, wherein the chip positions can be at a carrier plate position of an embedded module or at a sub-card position of the embedded module; the other is a second transmission link, which is a high-speed Serdes chip to an optoelectronic transceiver, that is, a high-speed signal generated by the high-speed Serdes chip is routed to the optoelectronic transceiver to be converted into an optical signal, and the loss requirement on the link is determined by the maximum loss that the optoelectronic transceiver can receive.
S13, placing each passive test transmission link and each active test transmission link into the test board general model, and establishing to obtain the test board initial model.
Further, in the step S11, the test board universal model includes an analog connector, an analog daughter card, an analog carrier board and an analog backplane, wherein the analog daughter card and the analog carrier board form an embedded module, and a plurality of the embedded modules are interconnected in the analog backplane at a high speed through the transmission link.
Further, in the step S12, the type of the transmission link includes a first transmission link and a second transmission link, where the first transmission link is a link in the authenticated system for completing ethernet information exchange through an electrical signal, and the second transmission link is a link in the authenticated system for converting the electrical signal into an optical signal.
Further, in the step S2, the simplifying the passive test transmission link in the test board initial model according to the connector stage number and the link length, and using the simplified passive test transmission link to simplify the analog connector of the test board initial model to obtain a simplified test board model, including:
S21, according to the connector series and the link length, using a set series threshold value and a link length threshold value, and simplifying the passive test transmission link to obtain a simplified test board initial model.
In a specific implementation, the test board is designed to passively test the transmission link according to a possible transmission link, as shown in fig. 2, since a soldering device is not required, only a high-speed SerDes chip or a corresponding pad of an optoelectronic transceiver is required to be used for testing, however, for a high-speed ethernet signal, a direct point test manner of a differential stylus is not suitable, and a pad of an analog device needs to be led out as a coaxial interface (i.e., SMA head) capable of being connected with a test instrument. Specifically, a pair of coaxial connectors are used for being connected with the bonding pads corresponding to the differential wires, and because the SMA heads are connected and extra PCB wires are added in a link, partial interference is added in performance parameters obtained through testing of the SMA heads, and aiming at the problems, the wires from all the bonding pads of the analog devices on the test board to the SMA heads are kept consistent, including wire length, wire width and bending angle, all the wires are guaranteed to be identical, then the standard wires of the section are completely mirrored, a pair of differential wires from the SMA heads without the bonding pads to the SMA heads are obtained, and the pair of differential wires can be used for completing de-embedding calibration in actual testing, so that more accurate testing results are obtained.
The vector network analyzer has one sine source with sweep frequency inside, and the S parameter file of the tested part for different frequency point signals may be obtained through low frequency to high frequency scanning and comparing the amplitude and phase relation of the receivers in the ports. For a pair of differential transmission lines, see table 1 below, the 4 ports have 16 single-ended S parameters, which fully describe the characteristics of the pair of differential lines in terms of insertion loss, return loss, common mode radiation, and common mode radiation resistance, for example, the SDD21 parameter reflects the insertion loss characteristic of the differential line, and the SDD11 parameter reflects the return loss characteristic. Differential input to differential output in the table shows differential signal behavior, differential input to common mode output shows external electromagnetic radiation, common mode input to differential output shows electromagnetic radiation resistance, and common mode input to common mode output shows common mode signal behavior.
Table 1: differential model 16 differential S parameters
S22, modifying the signal definition of the analog connector passed by each passive test transmission link in the simplified test board initial model, and simplifying the number of the analog connectors, the analog daughter cards, the analog carrier boards and the analog backboard of the simplified test board initial model to obtain the one-time simplified test board model.
In specific implementation, considering low-cost design, integrating various test requirements, only designing 3 PCBs, including a simulation backboard, a simulation substrate and a simulation sub-card, the specific integration scheme is as follows: a plurality of signal links are defined by using the high-density connector to cover the links to be tested, and a transmitting end and a receiving end are combined with the same test board by winding the links to be tested on the test board according to the condition of multi-module high-speed electric signal exchange in an actual use scene, so that an analog daughter card or an analog carrier board does not need to be additionally added.
Further, in the step S3, the step of designing the active test transmission link of the once simplified test board model according to the long transmission link in the transmission links to obtain a test board model includes:
S31, by adjusting the passive test signal definition of the analog connector in the one-time simplified test board model, the passive test signal definition is different from the definition of a signal emission source adopting an FPGA daughter card as the active test transmission link;
S32, setting photoelectric transceivers on a simulation carrier plate and a simulation backboard of the once simplified test board model for each long transmission link to obtain an initial active test link of each long transmission link, and carrying out self-loop test on each long transmission link by adopting a high-speed Ethernet signal;
s33, setting a driver circuit for the long transmission link according to a self-loop test result, and completing the design of the active test transmission link of the once-simplified test board model to obtain a test board model;
in practical implementation, unlike a standard channel model, in practical design, a high-speed signal may be generated by a daughter card on a module, that is, the high-speed signal may pass through a multi-stage connector, including a daughter card connector between the daughter card and a carrier board, and a back board connector between the carrier board and a back board, where the multi-stage connector brings more loss, so that the margin of simulation error is gradually reduced, meanwhile, because the module needs to have a longer actual transmission link on the back board, various factors all cause the actual wiring loss to approach the upper limit of total loss required by the standard, an active test link for longer link transmission needs to be designed, and as shown in fig. 3, the high-speed Serdes chip (FPGA) daughter card is used as a signal source for active test, and the self-loop test of the active test link is realized by self-loop connecting the ports corresponding to the photoelectric transceiver.
For a long transmission link, aiming at the serious signal loss condition possibly occurring in the long transmission link, a driver is selected to carry out high-speed transmission signal link compensation, and the specific test method is that the long transmission link is selected on the basis of the test link, a driver related circuit is added at the near-receiving end of the link, and the preliminary effect can be obtained through an FPGA electronic eye diagram and an error rate. The specific configuration of the driver on the long transmission link is shown in fig. 3, and the driver can implement the processing of receiving and transmitting multiple high-speed signals, and can configure the multiple high-speed signals through the SMBus. Therefore, the MCU is adopted to configure the device through the SMBus, meanwhile, an AC coupling capacitor is required to be added on a transmitting and receiving link of the driver, and the driver related circuit is used for realizing transmission compensation of long-distance high-speed signals, so that preliminary verification test can be realized on the high-speed signal compensation technology.
Further, in the step S32, the long transmission link includes a connector with a connector number greater than or equal to 2 and a transmission link with a link length greater than or equal to a set length.
Further, in the step S32, the performing the self-loop test on each long transmission link by using the high-speed ethernet signal includes:
s321, loading the I BERT logic on line in the FPGA daughter card;
S322, transmitting set quantity data in the long transmission link corresponding to the photoelectric transceiver, recording the error rate and generating an electronic eye pattern for self-loop test.
In the implementation of the step S5, the analog daughter card, the analog carrier board and the analog backboard are inserted according to the connector, a pair of signal transmission links are selected, and the vector network analyzer is connected to SMA heads at two ends of the differential signal to be tested, so as to obtain the S parameter file. And inserting a high-speed Serdes chip (FPGA) daughter card into the analog carrier board, and obtaining the error rate and the electronic eye diagram by a signal transmission link to be tested through a photoelectric transceiver self-loop.
The embodiment of the invention also provides a high-speed Ethernet signal testing device, which is shown in fig. 4, and comprises a testing board formed by an analog daughter card and an analog carrier board mixed analog backboard, a high-speed Serdes chip (FPGA) daughter card, a PC and a vector network analyzer. The specific use flow of the testing device is as follows: when passive test is carried out, the analog daughter card, the analog carrier plate and the analog backboard are spliced according to the connector, and the vector network analyzer is respectively connected with the SMA heads at the two ends of the link to be tested to obtain S parameters and analyze the signal quality of the S parameters; when active test is carried out, the passive daughter card is replaced by a high-speed Serdes chip (FPGA) daughter card, and the corresponding link to be tested is self-looped in a mode of online programming of I BERT logic, and a certain data volume is accumulated and transmitted to obtain the bit error rate and the electronic eye diagram.
The embodiment of the invention realizes the following technical effects: the invention designs a high-speed Ethernet signal test board for an embedded system by carrying out design on an active transmission link and a passive transmission link to obtain a test board model, preparing the test board by using the test board model, and carrying out signal optimization by adopting a high-speed signal simulation technology to obtain a final test board. In the method, on one hand, in the system demonstration stage, a high-speed Ethernet signal test board is designed according to the connector selection, plates, specific transmission link conditions and the like, and the specific design of the system is guided according to the test result, so that design errors related to high-speed signal transmission are avoided, and the high-speed signal transmission quality is effectively ensured; on the other hand, by adding a driver circuit and a signal quality optimization design in the signal test board, the effectiveness of signal quality optimization measures under specific conditions is demonstrated, the signal transmission quality of a long-chain high-speed Ethernet in an embedded system is improved, and a high-performance data exchange and information processing system is constructed.
It will be apparent to those skilled in the art that the foregoing is merely a preferred embodiment of the present invention and is not intended to limit the invention, and that various modifications and variations can be made to the embodiment of the present invention by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present invention should be included in the protection scope of the present invention.
Claims (8)
1. A design method of a high-speed Ethernet signal test board for an embedded system is characterized by comprising the following steps: comprising the following steps:
Establishing a test board initial model according to the signal transmission requirement of a verified system, wherein the test board initial model comprises an analog connector and transmission links, and each transmission link comprises a connector series and a link length;
simplifying the passive test transmission link in the test board initial model according to the connector series and the link length, and simplifying the analog connector of the test board initial model by using the simplified passive test transmission link to obtain a once simplified test board model;
According to the long transmission link in the transmission links, designing the active test transmission link of the once simplified test board model to obtain a test board model;
preparing a test board by using the test board model, performing signal optimization on an anti-bonding pad and a back drill of the test board by adopting a high-speed signal simulation technology, and performing disc cutting treatment on a nonfunctional bonding pad of the test board to obtain a final test board;
And performing active test and passive test on the final test board through a high-speed Ethernet signal testing device.
2. The embedded system-oriented high-speed ethernet signal test board design method according to claim 1, wherein said establishing a test board initial model according to signal transmission requirements of the verified system comprises:
analyzing the verified system, obtaining each connector model, each simulation device and each test board plate by using the analysis, and establishing a test board universal model;
counting all transmission links according to the information processing requirement of the verified system, wherein the transmission links comprise passive test transmission links and active test transmission links;
And placing each passive test transmission link and each active test transmission link into the test board universal model, and establishing and obtaining the test board initial model.
3. The embedded system-oriented high-speed ethernet signal test board design method of claim 2, wherein said test board generic model comprises an analog connector, an analog daughter card, an analog carrier board, and an analog backplane, wherein said analog daughter card and said analog carrier board form an embedded module, and a plurality of said embedded modules are interconnected at high speed in said analog backplane via said transmission link.
4. The embedded system-oriented high-speed ethernet signal test board design method according to claim 2, wherein the type of the transmission link includes a first transmission link and a second transmission link, the first transmission link is a link in the authenticated system for completing ethernet information exchange through an electrical signal, and the second transmission link is a link in the authenticated system for converting the electrical signal into an optical signal.
5. The embedded system-oriented high-speed ethernet signal test board design method according to claim 1, wherein said simplifying the passive test transmission link in the test board initial model according to the number of connector stages and the link length, and simplifying the analog connector of the test board initial model using the simplified passive test transmission link, to obtain a simplified test board model, comprises:
according to the connector series and the link length, using a set series threshold value and a link length threshold value, simplifying the passive test transmission link to obtain a simplified test board initial model;
And modifying the signal definition of the analog connector passed by each passive test transmission link in the simplified test board initial model, and simplifying the number of the analog connectors, the analog daughter cards, the analog carrier boards and the analog back boards of the simplified test board initial model to obtain the one-time simplified test board model.
6. The embedded system-oriented high-speed ethernet signal test board design method according to claim 1, wherein said designing the active test transmission link of the one-time simplified test board model according to the long transmission link in the transmission links to obtain the test board model comprises:
the definition of the passive test signal of the analog connector in the one-time simplified test board model is adjusted to enable the definition of the passive test signal to be different from the definition of a signal emission source adopting an FPGA daughter card as the active test transmission link;
Setting photoelectric transceivers on a simulation carrier plate and a simulation backboard of the once simplified test board model for each long transmission link to obtain an initial active test link of each long transmission link, and carrying out self-loop test on each long transmission link by adopting a high-speed Ethernet signal;
And setting a driver circuit for the long transmission link according to the self-loop test result, and completing the design of the active test transmission link of the once simplified test board model to obtain the test board model.
7. The embedded system-oriented high-speed ethernet signal test board design method according to claim 1 or 6, wherein said long transmission link comprises a connector with a connector level of no less than 2 and a transmission link with a link length of no less than a set length.
8. The embedded system-oriented high-speed ethernet signal test board design method according to claim 6, wherein said performing a self-loop test on each of said long transmission links using high-speed ethernet signals comprises:
Loading IBERT logic on line in the FPGA daughter card;
and transmitting set quantity data in the long transmission link corresponding to the photoelectric transceiver, recording the error rate and generating an electronic eye pattern to perform self-loop test.
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