CN118133736A - Chip, method, device and storage medium for detecting data transmission interface type - Google Patents

Chip, method, device and storage medium for detecting data transmission interface type Download PDF

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Publication number
CN118133736A
CN118133736A CN202410550845.1A CN202410550845A CN118133736A CN 118133736 A CN118133736 A CN 118133736A CN 202410550845 A CN202410550845 A CN 202410550845A CN 118133736 A CN118133736 A CN 118133736A
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China
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module
signal
data transmission
random value
transmission interface
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CN202410550845.1A
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苏凯凯
崔根强
陈琦
方伟
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Zhejiang Xinsheng Electronic Technology Co Ltd
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Zhejiang Xinsheng Electronic Technology Co Ltd
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Priority to CN202410550845.1A priority Critical patent/CN118133736A/en
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Abstract

The application relates to the technical field of chips, and provides a chip, a method, equipment and a storage medium for detecting the type of a data transmission interface, wherein the device comprises: the device comprises a random value generation module, a time determination module and a level detection module; the random value generation module is respectively and electrically connected with the time determination module and the level detection module, and the time determination module and the level detection module are mutually and electrically connected; the random value generation module is used for generating a random value; the time determining module is used for acquiring a random value and determining target detection time according to the random value; the level detection module is used for acquiring a random value, and if a target data signal is detected from the receiving channel in the target detection time, the type of the data transmission interface to be detected is used as the type of the target data transmission interface, and the type of the data transmission interface to be detected is any one of an MDI interface and an MDIX interface. The technical scheme of the application improves the reliability and flexibility of the PHY chip for transmitting the data signals.

Description

Chip, method, device and storage medium for detecting data transmission interface type
Technical Field
The present application relates to the field of chip technologies, and in particular, to a chip, a method, an apparatus, and a storage medium for detecting a type of a data transmission interface.
Background
The data transmission interface types of PHY chips are divided into two types, MDI (MEDIA DEPENDENT INTERFACE, medium dependent) interface and MDIX (MEDIA DEPENDENT INTERFACE cross over interface) interface. The MDI interface and the MDIX interface differ in that the transmit channel and the receive channel are located opposite. The MDI interface and the MDIX interface are used as interfaces of PHY chips, and it is required to achieve the characteristics of high transmission stability and high transmission efficiency.
In the related art, in order to enable the interface of the PHY chip to stably and efficiently transmit data, when two ethernet devices transmit data, a data port of a transmitting end needs to be connected to a data port of a receiving end to normally transmit data. If the transmitting end of one device is connected to the transmitting end of the other device, and the receiving end is connected to the receiving end, the situation that data cannot be transmitted can be caused. Therefore, when two devices are in butt joint, the two ends of the devices need to be ensured to select proper interfaces so as to normally transmit data.
However, when the signals transmitted by the two ethernet devices are too bad, the PHY chip may misunderstand that the electrical connection device does not transmit the data signal, and thus the PHY chip cannot reliably and flexibly transmit the data signal.
Disclosure of Invention
The embodiment of the application provides a chip, a method, equipment and a storage medium for detecting the type of a data transmission interface, which can accurately determine a target data transmission interface, thereby improving the reliability and the flexibility of a PHY chip for transmitting data signals. The technical scheme is as follows:
according to a first aspect of an embodiment of the present application, there is provided a chip for detecting a type of a data transmission interface, the chip including:
The device comprises a random value generation module, a time determination module and a level detection module; the random value generation module is respectively and electrically connected with the time determination module and the level detection module, and the time determination module and the level detection module are mutually and electrically connected;
The random value generation module is used for generating a random value;
the time determining module is used for acquiring a random value and determining target detection time according to the random value;
The level detection module is configured to obtain the random value, and if a target data signal is detected from the receiving channel within the target detection time, take a type of data transmission interface to be detected as a type of target data transmission interface, where the random value indicates the type of data transmission interface to be detected, and the type of data transmission interface to be detected is any one of an MDI interface and an MDIX interface.
In one possible implementation manner, the level detection module is further configured to detect a level of the data signal to be detected if the data signal to be detected is detected from the receiving channel to be detected within the target detection time, compare the level with a level threshold, and use the data signal to be detected as the target data signal if the level is greater than the level threshold.
In one possible implementation, the level detection module includes a counting unit;
The counting unit is used for recording the times of continuously detecting the target data signal from the receiving channel to be detected;
The level detection module is further configured to compare the number of times with a number of times threshold, and lock the type of the target data transmission interface if the number of times is equal to the number of times threshold.
In one possible implementation, the mode selection module is electrically connected to the time determination module and the level detection module, respectively;
The mode selection module is used for acquiring an automatic detection signal, entering an automatic detection mode based on the automatic detection signal, and starting the time determination module and the level detection module;
The mode selection module is further configured to obtain a closing automatic detection signal, close the automatic detection mode based on the closing automatic detection signal, close the time determination module and the level detection module, and enter a manual detection mode.
In one possible implementation manner, the device further comprises an interface selection module and a PMD module, wherein the interface selection module is electrically connected with the level detection module, the mode selection module and the PMD module respectively;
The level detection module is further configured to generate a first control signal according to the random value in the automatic detection mode, and send the first control signal to the interface selection module; or (b)
The level detection module is further configured to generate a lock signal and send the lock signal to the interface selection module if the number of times is equal to the number of times threshold in the automatic detection mode.
In one possible implementation, the random value includes an indicator bit;
The level detection module is further configured to obtain the indication bit, and generate the first control signal according to the indication bit.
In a possible implementation manner, the interface selection module is configured to send the first control signal to the PMD module in the automatic detection mode, where the first control signal is used to control the PMD module to select the type of the data transmission interface to be tested; or (b)
The interface selection module is used for sending the locking signal to the PMD module in the automatic detection mode, and the locking signal is used for controlling the PMD module to lock the target data transmission interface type; or (b)
The interface selection module is configured to obtain a second control signal in the manual detection mode, send the second control signal to the PMD module, where the second control signal is used to control the PMD module to select the target data transmission interface type, and the second control signal is generated by the chip.
In one possible implementation manner, the device further comprises an unlocking module, wherein the unlocking module is electrically connected with the level detection module;
The unlocking module is used for acquiring the locking signal, recording duration time when the target data signal is not detected from the target receiving channel after the locking signal is acquired, wherein the receiving end of the target receiving channel is of the type of the target data transmission interface, and when the duration time is greater than a duration time threshold value, the unlocking module generates an unlocking signal;
the interface selection module is further configured to obtain the unlock signal, send the unlock signal to the PMD module, and control the PMD module to unlock the target data transmission interface type.
In one possible implementation manner, the device further comprises a detection failure module, wherein the detection failure module is electrically connected with the level detection module and the random value generation module respectively;
The level detection module is further configured to generate a redetected signal if the data signal to be detected is not detected from the receiving channel to be detected in the target detection time, send the redetected signal to the random value generation module and the detection failure module, and instruct the random value generation module to generate an updated random value;
The detection failure module is used for counting the re-detection signal to obtain a count value, comparing the count value with a count value threshold, generating a detection failure signal if the count value is larger than the count value threshold, feeding back the detection failure signal to the chip, and indicating the chip to update the level threshold by the detection failure signal.
According to a second aspect of an embodiment of the present application, there is provided a method of detecting a type of a data transmission interface, the method comprising:
generating a random value;
acquiring a random value, and determining target detection time according to the random value;
If the target data signal is detected from the receiving channel in the target detection time, the type of the data transmission interface to be detected is used as the type of the target data transmission interface, the random value indicates the type of the data transmission interface to be detected, and the type of the data transmission interface to be detected is any one of an MDI interface and an MDIX interface.
In one possible implementation manner, during the target detection time, if the data signal to be detected is detected from the receiving channel to be detected, the method further includes:
And detecting the level of the data signal to be detected, comparing the level with a level threshold, and taking the data signal to be detected as a target data signal if the level is larger than the level threshold.
In one possible implementation, the method further includes:
Recording the number of times of continuously detecting the target data signal from the receiving channel to be detected;
And comparing the times with a times threshold, and locking the type of the target data transmission interface if the times are equal to the times threshold.
In one possible implementation, the method further includes:
acquiring an automatic detection signal, entering an automatic detection mode based on the automatic detection signal, and starting the time determining module and the level detecting module;
acquiring a closing automatic detection signal, closing the automatic detection mode based on the closing automatic detection signal, closing the time determining module and the level detection module, and entering a manual detection mode.
In one possible implementation, the method further includes:
in the automatic detection mode, generating a first control signal according to the random value, and sending the first control signal to the interface selection module; or (b)
In the automatic detection mode, if the number of times is equal to the number of times threshold, a locking signal is generated and sent to the interface selection module.
In one possible implementation, the random value includes an indicator bit;
the method further comprises the following steps:
The indication bit is acquired, and the first control signal is generated according to the indication bit.
In one possible implementation, the method further includes:
In the automatic detection mode, the first control signal is sent to the PMD module, and the first control signal is used for controlling the PMD module to select the type of the data transmission interface to be detected; or (b)
In the automatic detection mode, sending the locking signal to the PMD module, wherein the locking signal is used for controlling the PMD module to lock the target data transmission interface type; or (b)
In the manual detection mode, a second control signal is acquired and sent to the PMD module, the second control signal is used for controlling the PMD module to select the target data transmission interface type, and the second control signal is generated by the chip.
In one possible implementation, the method further includes:
After the locking signal is obtained, recording the duration time when the target data signal is not detected from a target receiving channel, wherein the receiving end of the target receiving channel is the type of the target data transmission interface, and when the duration time is greater than a duration time threshold value, the unlocking module generates an unlocking signal;
And acquiring the unlocking signal, and sending the unlocking signal to the PMD module, wherein the unlocking signal is used for controlling the PMD module to unlock the type of the target data transmission interface.
In one possible implementation, the method further includes:
In the target detection time, if the data signal to be detected is not detected from the receiving channel to be detected, a re-detection signal is generated, the re-detection signal is sent to the random value generation module and the detection failure module, and the re-detection signal indicates the random value generation module to generate an updated random value;
Counting the re-detection signal to obtain a count value, comparing the count value with a count value threshold, generating a detection failure signal if the count value is larger than the count value threshold, feeding back the detection failure signal to the chip, and indicating the chip to update the level threshold by the detection failure signal.
According to a third aspect of embodiments of the present application, there is provided a computer device comprising a processor and a memory for storing at least one program to be loaded by the processor and to perform the above-described method of detecting a data transmission interface type.
According to a fourth aspect of embodiments of the present application, there is provided a computer readable storage medium having stored therein at least one program loaded and executed by a processor to implement the above-described method of detecting a data transmission interface type.
In the embodiment of the application, the device for detecting the type of the data transmission interface is provided, a chip generates a random value, a time determining module determines target detection time according to the random value, the random value indicates the type of the data transmission interface to be detected, and if the level detecting module can detect a target data signal in the target detection time, the type of the data transmission interface to be detected is used as the type of the target data transmission interface. In the embodiment of the application, the random value and the target detection time are used in the process of determining the type of the target data transmission interface, so that the target data transmission interface can be accurately determined, and the reliability and the flexibility of the PHY chip for transmitting data signals are further improved.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present application, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic illustration of an implementation environment provided in accordance with an embodiment of the present application;
Fig. 2 is a schematic structural diagram of an apparatus for detecting a type of a data transmission interface according to an embodiment of the present application;
fig. 3 is a schematic flow chart of an apparatus for detecting a data transmission interface type in an automatic detection mode according to an embodiment of the present application;
fig. 4 is a schematic flow chart of an apparatus for detecting a type of a data transmission interface in a manual detection mode according to an embodiment of the present application;
Fig. 5 is a schematic structural diagram of a terminal according to an embodiment of the present application;
Fig. 6 is a schematic structural diagram of a server according to an embodiment of the present application.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the present application more apparent, the embodiments of the present application will be described in further detail with reference to the accompanying drawings.
Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The implementations described in the following exemplary examples do not represent all implementations consistent with the application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.
The terms "first," "second," and the like in this disclosure are used for distinguishing between similar elements or items having substantially the same function and function, and it should be understood that there is no logical or chronological dependency between the terms "first," "second," and "n," and that there is no limitation on the amount and order of execution. It will be further understood that, although the following description uses the terms first, second, etc. to describe various elements, these elements should not be limited by the terms.
These terms are only used to distinguish one element from another element. For example, a first action can be referred to as a second action, and similarly, a second action can also be referred to as a first action, without departing from the scope of the various examples. The first action and the second action may both be actions, and in some cases may be separate and distinct actions.
At least one means one or more, and for example, at least one action may be an integer number of actions equal to or greater than one, such as one action, two actions, and three actions. The plurality means two or more, and for example, the plurality of actions may be an integer number of actions equal to or greater than two, such as two actions and three actions.
Fig. 1 is a schematic diagram of an implementation environment provided according to an embodiment of the present application, which may include a first device 1 and a second device 2.
The first device 1 is provided with a first PHY chip 11, the second device 2 is provided with a second PHY chip 12, and the first PHY chip 11 is taken as an example for explanation, the first PHY chip 11 is provided with two types of data transmission interface types, namely an MDI interface and an MDIX interface, so that a receiving channel is formed between the first PHY chip 11 and the second PHY chip 12 through the data transmission interface type of the first PHY chip 11 and the data transmission interface type of the second PHY chip 12, and further data interaction between the first device 1 and the second device 2 is realized.
In some embodiments, taking the first PHY chip 11 as an example for explanation, the first PHY chip 11 is configured to select a type of data transmission interface to be tested, and then detect the type of data transmission interface to be tested to determine whether the type of data transmission interface to be tested of the first PHY chip 11 is matched with the type of data transmission interface to be tested of the second PHY chip 12, and if the type of data transmission interface to be tested of the first PHY chip 11 is matched with the type of data transmission interface to be tested of the second PHY chip 12, the type of data transmission interface to be tested of the first PHY chip 11 is used as the type of target data transmission interface of the first PHY chip 11. Otherwise, if the type of the data transmission interface to be tested of the first PHY chip 11 is not adapted to the type of the data transmission interface to be tested of the second PHY chip 12, the first PHY chip 11 selects another type of the data transmission interface to be tested until the type of the target data transmission interface is determined.
In some embodiments, the first device 1 and the second device 2 may be computers or switches.
The first device 1 and the second device 2 may interact with data via a wired network.
In some embodiments, the wired network uses standard communication techniques and/or protocols. The network is typically the Internet, but may be any network including, but not limited to, a local area network (Local Area Network, LAN), metropolitan area network (Metropolitan Area Network, MAN), wide area network (Wide Area Network, WAN), etc. In some embodiments, data exchanged over the network is represented using techniques and/or formats including HyperText Mark-up Language (HTML), extensible markup Language (Extensible Markup Language, XML), and the like. All or some of the links may also be encrypted using conventional encryption techniques such as secure sockets layer (Secure Socket Layer, SSL), transport layer security (Transport Layer Security, TLS), virtual private network (Virtual Private Network, VPN), internet protocol security (Internet Protocol Security, IPsec), etc. In other embodiments, custom and/or dedicated data communication techniques may also be used in place of or in addition to the data communication techniques described above.
Fig. 2 is a schematic structural diagram of an apparatus for detecting a type of a data transmission interface according to an embodiment of the present application, where the apparatus includes:
A random value generation module 113, a time determination module 111, and a level detection module 112; the random value generation module 113 is electrically connected to the time determination module 111 and the level detection module 112, respectively, and the time determination module 111 and the level detection module 112 are electrically connected to each other.
Compared with the structure of the device in the related technology, the device for detecting the type of the data transmission interface has the advantages of smaller area and lower power consumption, thereby reducing the use cost.
In some embodiments, the first PHY chip 11 of the first device is explained as an example.
In some embodiments, the random value generation module 113 may be a Linear Feedback Shift Register (LFSR).
In some embodiments, the random value generation module 113 is configured to generate a random value; the time determining module 111 is configured to obtain a random value, and determine a target detection time according to the random value; the level detection module 112 is configured to obtain the random value, and if a target data signal is detected from the receiving channel within the target detection time, take a type of data transmission interface to be detected as a type of target data transmission interface, where the random value indicates the type of data transmission interface to be detected, and the type of data transmission interface to be detected is any one of an MDI interface and an MDIX interface.
In some embodiments, after the first PHY chip 11 is powered up, the first PHY chip 11 generates a random value signal, sends the random value signal to the random value generation module 113, and the random value generation module 113 generates a random value from the random value signal.
In some embodiments, in order to make the type of the data transmission interface to be tested of the first PHY chip 11 and the type of the data transmission interface to be tested of the second PHY chip not adapted, the type of the data transmission interface to be tested of the second PHY chip may be kept unchanged, only the first PHY chip 11 switches the type of the data transmission interface to be tested, otherwise, if the type of the data transmission interface to be tested of the first PHY chip 11 and the type of the data transmission interface to be tested of the second PHY chip are simultaneously switched, the adaptation process of the type of the data transmission interface to be tested of the first PHY chip 11 and the type of the data transmission interface to be tested of the second PHY chip may enter into a vicious circle. Therefore, in the embodiment of the present application, after the random value is obtained, the time determining module 111 randomly selects one preset detection time from the preset detection time set as the target detection time, so as to avoid simultaneous switching between the type of the data interface to be detected of the first PHY chip 11 and the type of the data transmission interface to be detected of the second PHY chip. The preset detection time set comprises a plurality of preset detection times.
In some embodiments, the first PHY chip 11 is provided with an auto-negotiation function, and each preset detection time is longer than an interval time of transmitting the data signal by the auto-negotiation function. Because the preset detection time is less than the interval time, the level detection module 112 may misjudge.
Alternatively, when the interval time is greater than 16ms, each preset detection time is greater than 16.
Alternatively, the data signal may be a FLP (Fast Link Pulse) signal.
In some embodiments, the level detection module 112 is further configured to detect a level of the data signal to be detected if the data signal to be detected is detected from the receiving channel to be detected within the target detection time, compare the level with a level threshold, and regard the data signal to be detected as the target data signal if the level is greater than the level threshold.
In some embodiments, the level detection module 112 includes a counting unit; the counting unit is used for recording the number of times of continuously detecting the target data signal from the receiving channel to be detected. The level detection module 112 is further configured to compare the number of times with a number of times threshold, and lock the target data transmission interface type if the number of times is equal to the number of times threshold.
In some embodiments, in order to avoid misjudging the glitch signal as the target data signal, the glitch signal is an abnormal data signal, in the embodiments of the present application, after the level detection module 112 detects the target data signal for the first time, the counting unit updates the recorded number of times to 1, the level detection module 112 compares the number of times with a number of times threshold, and the number of times is smaller than the number of times threshold, and then the level detection module 112 continues to detect the data signal to be detected from the receiving channel to be detected according to the target detection time; after the level detection module 112 continuously detects the target data signal for the nth time, the calculation unit updates the recorded number of times to N, and the level detection module 112 compares the number of times with the number of times threshold value, where the number of times is equal to the number of times threshold value, and indicates that the type of the data transmission interface to be tested of the first PHY chip 11 is adapted to the type of the data transmission interface to be tested of the second PHY chip. N is an integer greater than or equal to 1.
Alternatively, the number of times threshold may be 5.
Optionally, after the number of times the counting unit records is equal to the number of times threshold, the counting unit is cleared, i.e. the number of times the counting unit records is reset to 0.
In some embodiments, the mode selection module 114 is electrically connected to the time determination module 111 and the level detection module 112, respectively.
The mode selection module 114 is configured to obtain an auto-detection signal, enter an auto-detection mode based on the auto-detection signal, and activate the time determination module and the level detection module 112.
The mode selection module 114 is further configured to obtain an off automatic detection signal, turn off the automatic detection mode based on the off automatic detection signal, turn off the time determination module and the level detection module 112, and enter a manual detection mode.
In some embodiments, the first PHY chip 11 generates an auto-detect signal or a shut-down auto-detect signal, which is sent to the mode selection module 114.
In some embodiments, an interface selection module 115 and a PMD (PHYSICAL MEDIA DEPENDENT, physical media dependent layer) module are also included, the interface selection module 115 being electrically connected to the level detection module 112, the mode selection module 114 and the PMD module 116, respectively.
In some embodiments, the level detection module 112 is further configured to generate a first control signal according to the random value in the automatic detection mode, and send the first control signal to the interface selection module 115.
In some embodiments, the level detection module 112 is further configured to generate a lock signal if the number of times is equal to the number of times threshold in the automatic detection mode, and send the lock signal to the interface selection module 115.
In some embodiments, the random value includes an indicator bit; the level detection module 112 is further configured to obtain the indication bit, and generate the first control signal according to the indication bit.
Optionally, the indication bit is the lowest bit of the random value, and when the lowest bit is 0, the first control signal generated according to the indication bit indicates the MDI interface. Or when the lowest bit is 1, the third control signal generated according to the indication bit indicates the MDIX interface.
In some embodiments, the interface selection module 115 is configured to send the first control signal to the PMD module 116 in the automatic detection mode, where the first control signal is configured to control the PMD module 116 to select the type of data transmission interface under test.
Optionally, after the PMD module 116 obtains the first control signal, the PMD module processes the first control signal to obtain a processing result, selects a type of data transmission interface to be tested according to the processing result, and constructs a receiving channel to be tested by using the type of data transmission interface to be tested and the type of data transmission interface to be tested of the second PHY chip.
It should be noted that, the process of the PMD module 116 for processing the first control signal may be obtained from the related art, and the embodiments of the present application will not be described in detail.
In some embodiments, the interface selection module 115 is further configured to send the lock signal to the PMD module 116 in the auto-detect mode, the lock signal being configured to control the PMD module 116 to lock the target data transmission interface type.
Optionally, the PMD module 116 cannot switch the target data transmission interface type in the locked state, so as to ensure the stability of the target receiving channel, and further ensure that the first PHY chip 11 can stably transmit data.
In some embodiments, the interface selection module 115 is further configured to obtain a second control signal in the manual detection mode, and send the second control signal to the PMD module 116, where the second control signal is used to control the PMD module 116 to select the target data transmission interface type, and the second control signal is generated by the chip.
Optionally, the second control signal is generated by the first PHY chip 11.
In some embodiments, the embodiments of the present application allow the first PHY chip 11 to freely switch between an automatic detection mode and a manual detection mode, and in the manual detection mode, any one of the MDI interface and the MDIX interface is manually selected by using the mode selection module 114, so as to avoid the situation that the first PHY chip 11 cannot work normally due to the abnormality of the automatic detection mode, thereby improving the reliability and flexibility of the transmission of the data signal by the first PHY chip 11.
In some embodiments, an unlocking module 118 is further included, the unlocking module 118 being electrically connected to the level detection module 112; the unlocking module 118 is configured to acquire the locking signal, record a duration of time when the target data signal is not detected from the target receiving channel after the locking signal is acquired, wherein the receiving end of the target receiving channel is the target data transmission interface type, and when the duration of time is greater than a duration threshold, the unlocking module 118 generates the unlocking signal, thereby improving reliability and flexibility of the data signal transmission of the first PHY chip 11.
In some embodiments, after the lock signal is acquired, the unlocking module 118 starts an unlocking mechanism, that is, records the duration of time when the target data signal is not detected from the target receiving channel, and determines that the target transmission interface type is in the idle or switching state when the duration of time is greater than the duration threshold, so as to avoid that the interface of the target transmission interface type is in the idle or switching state for a long time, thereby improving the reliability of the data signal transmission of the first PHY chip 11.
In some embodiments, the interface selection module 115 is further configured to obtain the unlock signal, and send the unlock signal to the PMD module 116, where the unlock signal is configured to control the PMD module 116 to unlock the target data transmission interface type.
In some embodiments, after the PMD module 116 obtains the unlock signal, the PMD module 116 parses the unlock signal to obtain a parsing result, and the PMD module 116 unlocks the target transport interface type according to the parsing result, so that the target transport interface type is in a null connection or a change connection state.
In some embodiments, after the PMD module 116 unlocks the target transmission interface type according to the parsing result, the PHY chip regenerates the random value signal, and sends the regenerated random value signal to the random value generation module 113, so that the random value generation module 113 regenerates the random value according to the re-acquired random value signal.
In some embodiments, a detection failure module 117 is further included, and the detection failure module 117 is electrically connected to the level detection module 112 and the random value generation module 113, respectively.
The level detection module 112 is further configured to generate a redetect signal if the data signal to be detected is not detected from the receiving channel to be detected within the target detection time, send the redetect signal to the random value generation module 113 and the detection failure module 117, and instruct the random value generation module 113 to generate an updated random value.
The detection failure module 117 is configured to count the re-detection signal to obtain a count value, compare the count value with a count value threshold, and if the count value is greater than the count value threshold, generate a detection failure signal, and feed back the detection failure signal to the chip, where the detection failure signal indicates that the chip updates the level threshold.
In some embodiments, taking a type of data interface to be tested as an example for illustration, when the level detection module 112 does not detect the data signal to be tested within the first target detection time, a re-detection signal is generated, and the re-detection signal is fed back to the first PHY chip 11, and the first PHY chip 11 sends the re-detection signal to the random value generation module 113, so that the random value generation module 113 generates an updated random value using the re-detection signal.
Alternatively, the time determination module 111 acquires the update random value to select the update target detection time according to the update random value. And the level detection time acquires the updated random value, and determines the type of the data interface to be updated according to the updated random value, namely the type of the data interface to be updated is switched to the type of the data interface to be updated.
In some embodiments, the level detection module 112 is illustrated as an example. Since the level detection module 112 may malfunction during use, after the level detection module 112 accumulates that the count value of the data signal to be detected cannot be detected is greater than the count value threshold, which indicates that the level detection module 112 cannot work normally, the level detection module 112 generates a detection failure signal and feeds back the detection failure signal to the first PHY chip 11, and the first PHY chip 11 updates the level threshold according to the detection failure signal. Alternatively, the count value threshold may be 50.
Alternatively, the first PHY chip 11 decreases the level threshold according to the detection failure signal, and then the level detection module 112 detects the data signal to be detected according to the decreased level threshold, that is, compares the decreased level threshold with the received data signal to be detected.
Alternatively, after the level detection module 112 accumulates M times that the data signal to be detected cannot be detected, M is an integer greater than or equal to 1 and less than the count value threshold. If the level detection module 112 detects the data signal to be detected in the m+1th detection process, the count value recorded by the detection failure module 117 is cleared, which indicates that the level detection module 112 can work normally.
In the embodiment of the application, the first PHY chip generates a random value, the time determining module determines the target detection time according to the random value, the random value indicates the type of the data transmission interface to be detected, and if the level detecting module can detect the target data signal in the target detection time, the type of the data transmission interface to be detected is used as the type of the target data transmission interface. In the embodiment of the application, the random value and the target detection time are used in the process of determining the type of the target data transmission interface, so that the target data transmission interface can be accurately determined, and the reliability and the flexibility of the PHY chip for transmitting data signals are further improved.
Fig. 3 is a flow chart of a method for detecting a data transmission interface type in an automatic detection mode according to an embodiment of the present application, as shown in fig. 3, and in an embodiment of the present application, an application to a first device having a first PHY chip is described as an example. The method comprises the following steps:
In step 301, an auto-detection signal is acquired, an auto-detection mode is entered based on the auto-detection signal, and the time determination module and the level detection module are activated.
In step 302, in the automatic detection mode, a random value is generated, where the random value includes an indication bit, the first control signal is generated according to the indication bit, and the first control signal is sent to the PMD module, where the first control signal is used to control the PMD module to select the type of the data transmission interface to be tested.
In step 303, a random value is obtained, and a target detection time is determined based on the random value.
In step 304, after the data signal to be detected is detected from the receiving channel to be detected in the target detection time, the level of the data signal to be detected is detected, the level is compared with a level threshold, and if the level is greater than the level threshold, the data signal to be detected is used as the target data signal.
In step 305, the number of times a target data signal is continuously detected from the receive channel under test is recorded.
In step 306, the number of times is compared with a number of times threshold, and if the number of times is equal to the number of times threshold, the type of data transmission interface to be tested is used as the type of target data transmission interface.
In step 307, a lock signal is generated and sent to the PMD module, the lock signal being used to control the PMD module to lock the target data transmission interface type. The random value indicates the type of the data transmission interface to be tested, and the type of the data transmission interface to be tested is any one of an MDI interface and an MDIX interface.
In step 308, the lock signal is acquired, and after the lock signal is acquired, the duration of time that the target data signal is not detected from the target receiving channel is recorded, the receiving end of the target receiving channel is the target data transmission interface type, and when the duration of time is greater than the duration threshold, the unlocking module generates an unlocking signal.
In step 309, the unlock signal is obtained and sent to the PMD module, where the unlock signal is used to control the PMD module to unlock the target data transmission interface type.
In some embodiments, steps 301 through 309 above are repeated after unlocking the target data transfer interface type.
In some embodiments, step 304 described above is one implementation. In addition, in the target detection time, if the data signal to be detected is not detected from the receiving channel to be detected, a re-detection signal is generated, the re-detection signal is sent to the random value generation module and the detection failure module, and the re-detection signal indicates the random value generation module to generate an updated random value; counting the re-detection signal to obtain a count value, comparing the count value with a count value threshold, if the count value is greater than the count value threshold, generating a detection failure signal, feeding back the detection failure signal to the chip, indicating the chip to update the level threshold by the detection failure signal, and repeating the steps 301 to 309.
It should be noted that: the method for detecting the type of the data transmission interface provided in the above embodiment belongs to the same concept as the device embodiment for detecting the type of the data transmission interface, and the specific implementation process is detailed in the method embodiment, which is not described herein again.
In the embodiment of the application, a random value is generated, the target detection time is determined according to the random value, the random value indicates the type of the data transmission interface to be detected, and if the target data signal can be detected in the target detection time, the type of the data transmission interface to be detected is used as the type of the target data transmission interface. In the embodiment of the application, the random value and the target detection time are used in the process of determining the type of the target data transmission interface, so that the target data transmission interface can be accurately determined, and the reliability and the flexibility of the PHY chip for transmitting data signals are further improved.
Fig. 4 is a flow chart of a method for detecting a data transmission interface type in a manual detection mode according to an embodiment of the present application, as shown in fig. 4, and in an embodiment of the present application, an application to a first device having a first PHY chip is described as an example. The method comprises the following steps:
In step 401, a shutdown auto-detect signal is acquired, the auto-detect mode is shutdown based on the shutdown auto-detect signal, and the time determination module and the level detection module are shutdown, entering a manual detect mode.
In step 402, a second control signal is obtained and sent to the PMD module.
In step 403, the PMD module selects the target data transmission interface type according to the second control signal, the second control signal being generated by the chip.
It should be noted that: the method for detecting the type of the data transmission interface provided in the above embodiment belongs to the same concept as the device embodiment for detecting the type of the data transmission interface, and the specific implementation process is detailed in the method embodiment, which is not described herein again.
According to the embodiment of the application, the chip is allowed to be freely switched in the automatic detection mode and the manual detection mode, and any one of the MDI interface and the MDIX interface is manually selected by using the mode selection module in the manual detection mode, so that the situation that the first PHY chip cannot work normally due to the abnormality of the automatic detection mode is avoided, and the reliability and the flexibility of the data signal transmission of the first PHY chip are improved.
Embodiments of the present application also provide a computer device comprising a processor, a memory and a computer program stored in the memory and configured to be executed by the processor, the processor implementing a method of detecting a data transmission interface type as above when the computer program is executed.
Taking a computer device as an example of a terminal, fig. 5 is a schematic structural diagram of a terminal according to an embodiment of the present application, referring to fig. 5, a terminal 500 may be: a smart phone, a tablet computer, an MP3 player (Moving Picture Experts Group Audio Layer III, motion picture expert compression standard audio plane 3), an MP4 (Moving Picture Experts Group Audio Layer IV, motion picture expert compression standard audio plane 4) player, a notebook computer, or a desktop computer. The terminal 500 may also be referred to by other names of user devices, portable terminals, laptop terminals, desktop terminals, etc.
In general, the terminal 500 includes: a processor 501 and a memory 502.
Processor 501 may include one or more processing cores, such as a 4-core processor, a 5-core processor, and the like. The processor 501 may be implemented in at least one hardware form of DSP (DIGITAL SIGNAL Processing), FPGA (Field-Programmable gate array), PLA (Programmable Logic Array ). The processor 501 may also include a main processor and a coprocessor, where the main processor is a processor for processing data in an awake state, and is also called a CPU (Central Processing Unit ); a coprocessor is a low-power processor for processing data in a standby state. In some embodiments, the processor 501 may be integrated with a GPU (Graphics Processing Unit, image processor) for rendering and drawing of content required to be displayed by the display screen. In some embodiments, the processor 501 may also include an AI (ARTIFICIAL INTELLIGENCE ) processor for processing computing operations related to machine learning.
Memory 502 may include one or more computer-readable storage media, which may be non-transitory. Memory 502 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In some embodiments, a non-transitory computer readable storage medium in memory 502 is used to store at least one program code for execution by processor 501 to implement a process performed by a terminal in a method of detecting a data transmission interface type provided by an embodiment of a method in the present application.
In some embodiments, the terminal 500 may further optionally include: a peripheral interface 503 and at least one peripheral. The processor 501, memory 502, and peripheral interface 503 may be connected by buses or signal lines. The individual peripheral devices may be connected to the peripheral device interface 503 by buses, signal lines or circuit boards. Specifically, the peripheral device includes: at least one of radio frequency circuitry 504, a display 505, a camera assembly 506, audio circuitry 507, and a power supply 508.
Peripheral interface 503 may be used to electrically connect at least one Input/Output (I/O) related peripheral to processor 501 and memory 502. In some embodiments, processor 501, memory 502, and peripheral interface 503 are integrated on the same chip or circuit board; in some other embodiments, either or both of processor 501, memory 502, and peripheral interface 503 may be implemented on separate chips or circuit boards, as embodiments of the application are not limited in this regard.
The Radio Frequency circuit 504 is configured to receive and transmit RF (Radio Frequency) signals, also known as electromagnetic signals. The radio frequency circuitry 504 communicates with a communication network and other communication devices via electromagnetic signals. The radio frequency circuit 504 converts an electrical signal into an electromagnetic signal for transmission, or converts a received electromagnetic signal into an electrical signal. In some embodiments, the radio frequency circuit 504 includes: antenna systems, RF transceivers, one or more amplifiers, tuners, oscillators, digital signal processors, codec chipsets, subscriber identity module cards, and so forth. The radio frequency circuitry 504 may communicate with other terminals via at least one wireless communication protocol. The wireless communication protocol includes, but is not limited to: metropolitan area networks, various generations of mobile communication networks (2G, 3G, 4G, and 5G), wireless local area networks, and/or WiFi (WIRELESS FIDELITY ) networks. In some embodiments, the radio frequency circuit 504 may further include NFC (NEAR FIELD Communication) related circuits, which is not limited by the present application.
The display 505 is used to display a UI (User Interface, user page). The UI may include graphics, text, icons, video, and any combination thereof. When the display 505 is a touch display, the display 505 also has the ability to collect touch signals at or above the surface of the display 505. The touch signal may be input as a control signal to the processor 501 for processing. At this time, the display 505 may also be used to provide virtual buttons and/or virtual keyboards, also referred to as soft buttons and/or soft keyboards. In some embodiments, the display 505 may be one, and disposed on the front panel of the terminal 500; in other embodiments, the display 505 may be at least two, respectively disposed on different surfaces of the terminal 500 or in a folded design; in other embodiments, the display 505 may be a flexible display disposed on a curved surface or a folded surface of the terminal 500. Even more, the display 505 may be arranged in a non-rectangular irregular pattern, i.e., a shaped screen. The display 505 may be made of LCD (Liquid CRYSTAL DISPLAY), OLED (Organic Light-Emitting Diode), or other materials.
The camera assembly 506 is used to capture images or video. In some embodiments, the camera assembly 506 includes a front camera and a rear camera. Typically, the front camera is disposed on the front panel of the terminal and the rear camera is disposed on the rear surface of the terminal. In some embodiments, the at least two rear cameras are any one of a main camera, a depth camera, a wide-angle camera and a tele camera, so as to realize that the main camera and the depth camera are fused to realize a background blurring function, and the main camera and the wide-angle camera are fused to realize a panoramic shooting and Virtual Reality (VR) shooting function or other fusion shooting functions. In some embodiments, camera assembly 506 may also include a flash. The flash lamp can be a single-color temperature flash lamp or a double-color temperature flash lamp. The dual-color temperature flash lamp refers to a combination of a warm light flash lamp and a cold light flash lamp, and can be used for light compensation under different color temperatures.
The audio circuitry 507 may include a microphone and a speaker. The microphone is used for collecting sound waves of users and environments, converting the sound waves into electric signals, and inputting the electric signals to the processor 501 for processing, or inputting the electric signals to the radio frequency circuit 504 for voice communication. For the purpose of stereo acquisition or noise reduction, a plurality of microphones may be respectively disposed at different portions of the terminal 500. The microphone may also be an array microphone or an omni-directional pickup microphone. The speaker is used to convert electrical signals from the processor 501 or the radio frequency circuit 504 into sound waves. The speaker may be a conventional thin film speaker or a piezoelectric ceramic speaker. When the speaker is a piezoelectric ceramic speaker, not only the electric signal can be converted into a sound wave audible to humans, but also the electric signal can be converted into a sound wave inaudible to humans for ranging and other purposes. In some embodiments, audio circuitry 507 may also include a headphone jack.
The power supply 508 is used to power the various components in the terminal 500. The power source 508 may be alternating current, direct current, disposable or rechargeable. When the power supply 508 includes a rechargeable battery, the rechargeable battery may support wired or wireless charging. The rechargeable battery may also be used to support fast charge technology.
In some embodiments, the terminal 500 further includes one or more sensors 509. The one or more sensors 509 include, but are not limited to: acceleration sensor 510, gyro sensor 511, pressure sensor 512, optical sensor 513, and proximity sensor 514.
The acceleration sensor 510 may detect the magnitudes of accelerations on three coordinate axes of a coordinate system established with the terminal 500. For example, the acceleration sensor 510 may be used to detect components of gravitational acceleration in three coordinate axes. The processor 501 may control the display screen 505 to display a user page in a landscape view or a portrait view according to a gravitational acceleration signal acquired by the acceleration sensor 510. The acceleration sensor 510 may also be used for the acquisition of motion data of a game or a user.
The gyro sensor 511 may detect the body direction and the rotation angle of the terminal 500, and the gyro sensor 511 may collect the three-dimensional motion of the user to the terminal 500 in cooperation with the acceleration sensor 510. The processor 501 may implement the following functions based on the data collected by the gyro sensor 511: motion sensing (e.g., changing UI according to a tilting operation by a user), image stabilization at shooting, game control, and inertial navigation.
The pressure sensor 512 may be disposed at a side frame of the terminal 500 and/or at a lower layer of the display 505. When the pressure sensor 512 is disposed at a side frame of the terminal 500, a grip signal of the terminal 500 by a user may be detected, and the processor 501 performs a left-right hand recognition or a shortcut operation according to the grip signal collected by the pressure sensor 512. When the pressure sensor 512 is disposed at the lower layer of the display screen 505, the processor 501 controls the operability control on the UI page according to the pressure operation of the user on the display screen 505. The operability controls include at least one of a button control, a scroll bar control, an icon control, and a menu control.
The optical sensor 513 is used to collect the ambient light intensity. In one embodiment, the processor 501 may control the display brightness of the display 505 based on the ambient light intensity collected by the optical sensor 513. Specifically, when the intensity of the ambient light is high, the display brightness of the display screen 505 is turned up; when the ambient light intensity is low, the display brightness of the display screen 505 is turned down. In another embodiment, the processor 501 may also dynamically adjust the shooting parameters of the camera module 506 according to the ambient light intensity collected by the optical sensor 513.
A proximity sensor 514, also referred to as a distance sensor, is typically provided on the front panel of the terminal 500. The proximity sensor 514 is used to collect the distance between the user and the front of the terminal 500. In one embodiment, when the proximity sensor 514 detects that the distance between the user and the front surface of the terminal 500 gradually decreases, the processor 501 controls the display 505 to switch from the bright screen state to the off screen state; when the proximity sensor 514 detects that the distance between the user and the front surface of the terminal 500 gradually increases, the processor 501 controls the display screen 505 to switch from the off-screen state to the on-screen state.
Those skilled in the art will appreciate that the structure shown in fig. 5 is not limiting and that more or fewer components than shown may be included or certain components may be combined or a different arrangement of components may be employed.
Taking a computer device as a server as an example, fig. 6 is a schematic structural diagram of a server according to an embodiment of the present application, where the server 600 may have a relatively large difference due to different configurations or performances, and may include one or more processors (Central Processing Units, CPUs) 601 and one or more memories 602, where at least one computer program is stored in the one or more memories 602, and the at least one computer program is loaded and executed by the one or more processors 601 to implement the above method for detecting a data transmission interface type. Of course, the server 600 may also have a wired or wireless network interface, a keyboard, an input/output interface, and other components for implementing the functions of the device, which are not described herein.
The embodiment of the application also provides a computer readable storage medium, which comprises a stored computer program, wherein the computer readable storage medium is controlled to execute the method for generating the image processing model by the device when the computer program runs. Alternatively, the computer readable storage medium may be a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a Compact-Disc Read-Only Memory (CD-ROM), a magnetic tape, a floppy disk, an optical data storage device, and the like.
It will be understood by those skilled in the art that all or part of the steps for implementing the above embodiments may be implemented by hardware, or may be implemented by a program for instructing relevant hardware, where the program may be stored in a computer readable storage medium, and the storage medium may be a read-only memory, a magnetic disk or an optical disk, etc.
The foregoing description of the preferred embodiments of the present application is not intended to limit the application, but rather, the application is to be construed as limited to the appended claims.

Claims (12)

1. A chip for detecting a type of data transmission interface, comprising:
The device comprises a random value generation module, a time determination module and a level detection module; the random value generation module is respectively and electrically connected with the time determination module and the level detection module, and the time determination module and the level detection module are mutually and electrically connected;
The random value generation module is used for generating a random value;
the time determining module is used for acquiring the random value and determining target detection time according to the random value;
The level detection module is configured to obtain the random value, and if a target data signal is detected from the receiving channel within the target detection time, take a type of data transmission interface to be detected as a type of target data transmission interface, where the random value indicates the type of data transmission interface to be detected, and the type of data transmission interface to be detected is any one of an MDI interface and an MDIX interface.
2. The chip of claim 1, wherein the level detection module is further configured to detect a level of the data signal to be detected if the data signal to be detected is detected from the receiving channel to be detected within the target detection time, compare the level with a level threshold, and use the data signal to be detected as a target data signal if the level is greater than the level threshold.
3. The chip of claim 1, wherein the level detection module comprises a counting unit;
the counting unit is used for recording the times of continuously detecting the target data signals from the receiving channel to be detected;
The level detection module is further configured to compare the number of times with a number of times threshold, and lock the type of the target data transmission interface if the number of times is equal to the number of times threshold.
4. The chip of claim 3, further comprising: the mode selection module is electrically connected with the time determination module and the level detection module respectively;
the mode selection module is used for acquiring an automatic detection signal, entering an automatic detection mode based on the automatic detection signal, and starting the time determination module and the level detection module;
The mode selection module is further configured to obtain a closing automatic detection signal, close the automatic detection mode based on the closing automatic detection signal, close the time determination module and the level detection module, and enter a manual detection mode.
5. The chip of claim 4, further comprising an interface selection module and a PMD module, the interface selection module electrically connected to the level detection module, the mode selection module, and the PMD module, respectively;
The level detection module is further configured to generate a first control signal according to the random value in the automatic detection mode, and send the first control signal to the interface selection module; or (b)
The level detection module is further configured to generate a lock signal and send the lock signal to the interface selection module if the number of times is equal to the number of times threshold in the automatic detection mode.
6. The chip of claim 5, wherein the random value comprises an indicator bit;
the level detection module is further configured to obtain the indication bit, and generate the first control signal according to the indication bit.
7. The chip of claim 6, wherein the interface selection module is configured to send the first control signal to the PMD module in the automatic detection mode, the first control signal being configured to control the PMD module to select the type of data transmission interface to be tested; or (b)
The interface selection module is used for sending the locking signal to the PMD module in the automatic detection mode, and the locking signal is used for controlling the PMD module to lock the target data transmission interface type; or (b)
The interface selection module is configured to obtain a second control signal in the manual detection mode, send the second control signal to the PMD module, where the second control signal is used to control the PMD module to select the target data transmission interface type, and the second control signal is generated by the chip.
8. The chip of claim 7, further comprising an unlocking module electrically connected to the level detection module;
the unlocking module is used for acquiring the locking signal, recording duration time when the target data signal is not detected from the target receiving channel after the locking signal is acquired, wherein the receiving end of the target receiving channel is of the type of the target data transmission interface, and when the duration time is greater than a duration time threshold value, the unlocking module generates an unlocking signal;
The interface selection module is further configured to obtain the unlock signal, send the unlock signal to the PMD module, and control the PMD module to unlock the target data transmission interface type.
9. The chip of claim 1, further comprising a detection failure module electrically connected to the level detection module and the random value generation module, respectively;
the level detection module is further configured to generate a redetect signal if the data signal to be detected is not detected from the receiving channel to be detected in the target detection time, and send the redetect signal to the random value generation module and the detection failure module, where the redetect signal instructs the random value generation module to generate an updated random value;
the detection failure module is used for counting the re-detection signals to obtain a count value, comparing the count value with a count value threshold, generating a detection failure signal if the count value is larger than the count value threshold, feeding back the detection failure signal to the chip, and indicating the chip to update the level threshold by the detection failure signal.
10. A method of detecting a type of data transmission interface, comprising:
generating a random value;
acquiring the random value, and determining target detection time according to the random value;
And if the target data signal is detected from the receiving channel in the target detection time, taking the type of the data transmission interface to be detected as the type of the target data transmission interface, wherein the random value indicates the type of the data transmission interface to be detected, and the type of the data transmission interface to be detected is any one of an MDI interface and an MDIX interface.
11. A computer device comprising a processor and a memory for storing at least one program, the at least one program being loaded by the processor and executing the method of detecting a data transmission interface type of claim 10.
12. A computer readable storage medium having stored therein at least one program loaded and executed by a processor to implement the method of detecting a data transmission interface type of claim 10.
CN202410550845.1A 2024-05-07 2024-05-07 Chip, method, device and storage medium for detecting data transmission interface type Pending CN118133736A (en)

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