CN118116966A

CN118116966A - Semiconductor device, manufacturing method of semiconductor device and electronic equipment

Info

Publication number: CN118116966A
Application number: CN202211515661.9A
Authority: CN
Inventors: 戴淑君; 陆天皓; 仲正
Original assignee: Huawei Technologies Co Ltd
Current assignee: Huawei Technologies Co Ltd
Priority date: 2022-11-30
Filing date: 2022-11-30
Publication date: 2024-05-31
Also published as: WO2024114629A1

Abstract

The embodiment of the application provides a semiconductor device, electronic equipment and a preparation method of the semiconductor device. Relates to the technical field of semiconductors. A semiconductor device capable of reducing thermal resistance is provided. The semiconductor device includes a substrate, a functional layer formed on the substrate, and a plurality of electrodes, source pads, drain pads, and gate pads formed on a side of the functional layer remote from the substrate; the grid electrode bonding pad and the drain electrode bonding pad are oppositely arranged and extend along a first direction; the plurality of electrodes includes a first group of electrodes and a second group of electrodes separated from each other, the first group of electrodes and the second group of electrodes being arranged in a space between the gate pad and the drain pad in a first direction; a source pad is disposed in a space between the first set of electrodes and the second set of electrodes. By inserting the source pad between the active regions formed by the two electrode groups, the highest temperature of each active region is reduced, and the thermal resistance is reduced.

Description

Semiconductor device, manufacturing method of semiconductor device and electronic equipment

Technical Field

The present application relates to the field of semiconductor technology, and in particular, to a semiconductor device, an electronic apparatus having the semiconductor device, and a method for manufacturing the semiconductor device.

Background

With the development of the fifth generation mobile communication technology (5th generation of wireless communications technologies,5G), the communication field has put demands on semiconductor devices for higher frequencies, higher output power and higher efficiency.

For example, compared with a Laterally Diffused Metal Oxide Semiconductor (LDMOS), a gallium nitride (GaN) -based device has higher saturation current and power density, and can effectively reduce the area of the device and realize a small-sized device, so that the device is widely used in radar, wireless communication, navigation, satellite communication, electronic countermeasure equipment and other systems.

However, since the GaN device epitaxial process costs are high, a single device is required to have as small an area as possible to reduce the device cost. The smaller area has larger power density, which inevitably brings about the problem of difficult heat dissipation. Then, the junction temperature of the device with higher thermal resistance is higher under the same power in the subsequent working process, so that the aging failure of the device can be accelerated.

Therefore, how to effectively reduce thermal resistance of a semiconductor device based on GaN material is a technical problem to be solved.

Disclosure of Invention

The application provides a semiconductor device, electronic equipment with the semiconductor device and a preparation method of the semiconductor device. By changing the layout of the source electrode pad, the grid electrode pad or the drain electrode pad on the device, the thermal resistance of the semiconductor device is reduced, and the device performance is improved.

In order to achieve the above purpose, the embodiment of the present application adopts the following technical scheme:

In one aspect, the present application provides a semiconductor device. For example, the semiconductor device may be a gallium nitride (GaN) -based high electron mobility transistor (high electron mobility transistor, HEMT).

The semiconductor device includes: a substrate, a functional layer formed on the substrate, and a plurality of electrodes, source pads, drain pads, and gate pads formed on a side of the functional layer remote from the substrate; the plurality of electrodes comprise a plurality of sources, a plurality of drains and a plurality of grids, wherein the plurality of sources are electrically connected with the source bonding pads, the plurality of drains are electrically connected with the drain bonding pads, and the plurality of grids are electrically connected with the grid bonding pads; the grid electrode bonding pad and the drain electrode bonding pad are oppositely arranged and extend along a first direction; the plurality of electrodes includes a first group of electrodes and a second group of electrodes separated from each other, the first group of electrodes and the second group of electrodes being arranged in a space between the gate pad and the drain pad in a first direction; a source pad is disposed in a space between the first set of electrodes and the second set of electrodes.

In the semiconductor device provided by the application, the arrangement direction of the plurality of electrodes in the first group of electrodes and the second group of electrodes of the semiconductor device is consistent with the extension direction of the drain electrode pad and the gate electrode pad. By dividing the plurality of electrodes into a first group of electrodes and a second group of electrodes that are separated from each other, and disposing the source pad in the space between the first group of electrodes and the second group of electrodes, it is equivalent to dividing the heat generating body (where the electrodes are located) into two separate heat generating bodies (i.e., the first group of electrodes and the second group of electrodes) by the source pad. In this way, compared with the situation that a plurality of electrodes are not separated but are continuously arranged, the application can weaken heat concentration, and utilize the passive area where the source electrode bonding pad is positioned to dissipate heat so as to reduce the thermal resistance of the device and improve the heat dissipation effect.

In one possible implementation, the arrangement direction of the plurality of electrodes in the first set of electrodes and the arrangement direction of the plurality of electrodes in the second set of electrodes are both parallel to the first direction; or the arrangement direction of the plurality of electrodes in the first group of electrodes and the arrangement direction of the plurality of electrodes in the second group of electrodes intersect the first direction, for example, the arrangement direction of the plurality of electrodes in the first group of electrodes and the arrangement direction of the plurality of electrodes in the second group of electrodes are perpendicular to the first direction.

In one possible implementation, the source pad includes a first source pad and a second source pad; the first source pad and the second source pad are each located in a space between the first set of electrodes and the second set of electrodes.

Compared with the arrangement of the first source electrode pad and the second source electrode pad in the passive area outside the active area where the plurality of electrodes are located, the heat dissipation effect of the device can be improved, and the size of the device can not be increased.

In one possible implementation, the arrangement direction of the first source pad and the second source pad is parallel to the first direction.

By arranging the first source electrode pad and the second source electrode pad along the direction parallel to the gate electrode pad, the distance between the first group of electrodes and the second group of electrodes can be increased, the area of the passive region between the first group of electrodes and the second group of electrodes is increased, and the heat dissipation effect is further improved.

In one possible implementation, the arrangement direction of the first source pad and the second source pad is perpendicular to the first direction.

Compared with the method that the first source electrode pad and the second source electrode pad are arranged in the passive area outside the active areas where the plurality of electrodes are arranged, the size of the device can be reduced on the premise that the heat dissipation effect is equivalent.

In one possible implementation, the source pad includes a first source pad and a second source pad; the plurality of electrodes further includes a third group of electrodes, the first group of electrodes, the second group of electrodes, and the third group of electrodes being arranged in a space between the gate pad and the drain pad along the first direction, the second group of electrodes being located between the first group of electrodes and the third group of electrodes; the first source pad is located in a space between the first set of electrodes and the second set of electrodes, and the second source pad is located in a space between the second set of electrodes and the third set of electrodes.

When the plurality of electrodes are divided to include not only the first group electrode and the second group electrode but also the third group electrode, the first source pad may be disposed between the first group electrode and the second group electrode, and the second source pad may be disposed between the second group electrode and the third group electrode, thereby dividing the plurality of electrodes into at least three independent heat generating bodies.

In one possible implementation, the arrangement directions of the plurality of electrodes in the first group of electrodes, the second group of electrodes and the third group of electrodes are all parallel to the first direction; a first set of electrodes and a third set of electrodes, adjacent to an edge of the semiconductor device relative to the second set of electrodes; the number of electrodes in the first set of electrodes is greater than the number of electrodes in the second set of electrodes; the number of electrodes in the third set of electrodes is greater than the number of electrodes in the second set of electrodes.

The number of the electrodes of the electrode group close to the edge of the device is designed to be smaller than that of the electrode group close to the center of the device, so that a passive area at the edge of the device can be fully utilized for heat dissipation, thermal resistance is further reduced, and heat dissipation effect is improved.

In one possible implementation, the gate pad includes a first gate pad segment and a second gate pad segment, the first gate pad segment having a width dimension that is greater than a width dimension of the second gate pad segment in a direction perpendicular to the first direction; the drain pad includes a first drain pad segment and a second drain pad segment, a width dimension of the first drain pad segment being greater than a width dimension of the second drain pad segment in a direction perpendicular to the first direction.

In this manner, the gate pad includes a wider portion and a narrower portion, and the drain pad includes a wider portion and a narrower portion, for example, the first group of electrodes may be disposed between the wider portion of the gate pad and the narrower portion of the drain pad, and the second group of electrodes may be disposed between the narrower portion of the gate pad and the wider portion of the drain pad, so that the high temperature region of the first group of electrodes may be offset from the high temperature region of the second group of electrodes to weaken the phenomenon of heat concentration, thereby reducing thermal resistance and enhancing heat dissipation.

In one possible implementation, the first drain pad segment is opposite the second gate pad segment, and the first set of electrodes is located in a space between the first drain pad segment and the second gate pad segment; the second drain electrode pad segment is opposite to the first gate electrode pad segment, and the second group of electrodes are positioned in a space between the second drain electrode pad segment and the first gate electrode pad segment; the arrangement direction of the plurality of electrodes in the first group of electrodes and the arrangement direction of the plurality of electrodes in the second group of electrodes are parallel to the first direction.

The device can be reduced in size in a direction perpendicular to the first direction so that the device meets the miniaturization design requirements.

In one possible implementation, the first drain pad segment is opposite the first gate pad segment, and the first set of electrodes is located in a space between the first drain pad segment and the first gate pad segment; the second drain electrode pad segment is opposite to the second gate electrode pad segment, and the second group of electrodes are positioned in a space between the second drain electrode pad segment and the second gate electrode pad segment; the arrangement direction of the plurality of electrodes in the first group of electrodes and the arrangement direction of the plurality of electrodes in the second group of electrodes intersect the first direction.

In the semiconductor device provided by the application, the arrangement direction of the plurality of electrodes in the first group of electrodes and the second group of electrodes of the semiconductor device is intersected with the extending direction of the drain electrode bonding pad and the grid electrode bonding pad, such as vertical. The gate pad includes a wide portion and a narrow portion, and the drain pad includes a wide portion and a narrow portion, and the first group of electrodes is disposed between the wide portion of the gate pad and the wide portion of the drain pad, and the second group of electrodes is disposed between the narrow portion of the gate pad and the narrow portion of the drain pad.

Compared with the gate bonding pads with uniform width and the drain bonding pads with uniform width, the application can lead the number of the electrodes of the first group of electrodes to be smaller than the number of the electrodes of the second group of electrodes, thereby increasing the interval between two adjacent electrodes in the first group of electrodes to reduce the thermal resistance; in addition, the width dimensions of the gate pad and the drain pad opposite to the second group of electrodes become smaller, so that the number of the second group of electrodes is increased, the distance between two adjacent electrodes can be increased, the thermal resistance is reduced, and the heat dissipation effect is improved.

In one possible implementation, the number of electrodes in the first set of electrodes is less than the number of electrodes in the second set of electrodes.

In one possible implementation, the width dimension of the first gate pad segment is L1, and the width dimension of the second gate pad segment is L2, 5.ltoreq.L1/L2.ltoreq.8; and/or the width dimension of the first drain electrode pad segment is L3, and the width dimension of the second drain electrode pad segment is L4, and L3/L4 is less than or equal to 5 and less than or equal to 8. For example, 5.ltoreq.L1/L2.ltoreq.6, 5.ltoreq.L3/L4.ltoreq.6.

In one possible implementation, the side of the first drain pad segment remote from the first set of electrodes is flush with the side of the second gate pad segment remote from the second set of electrodes; the side of the second gate pad segment remote from the first set of electrodes is flush with the side of the first gate pad segment remote from the second set of electrodes.

In one possible implementation, the first gate pad segment and the second gate pad segment are of unitary construction; the first drain pad segment and the second drain pad segment are in an integral structure.

The integrated first gate pad section and the second gate pad section and the integrated first drain pad section and second drain pad section are adopted, so that the process is convenient to realize.

In still another aspect, the present application provides a method of manufacturing a semiconductor device, the method comprising:

forming a functional layer on one side of a substrate;

forming a plurality of electrodes, source pads, gate pads and drain pads on a side of the functional layer away from the substrate;

In forming the plurality of electrodes, the source pad, the gate pad, and the drain pad, comprising:

drain electrode pads and gate electrode pads which extend along the first direction and are oppositely arranged are manufactured;

in the space between the gate pad and the drain pad, a first group of electrodes and a second group of electrodes are prepared to be separated from each other, and the first group of electrodes and the second group of electrodes are arranged along a first direction;

A source pad is disposed in a space between the first set of electrodes and the second set of electrodes.

In the semiconductor device manufactured by the method, the source electrode pad is adjusted to be between the first group of electrodes and the second group of electrodes which are separated, which is equivalent to dividing a heating body (the position where the electrodes are located) into two independent heating bodies (namely, the first group of electrodes and the second group of electrodes) by using the source electrode pad. In this way, compared with the situation that a plurality of electrodes are not separated but are continuously arranged, the application can weaken heat concentration, and utilize the passive area where the source electrode bonding pad is positioned to dissipate heat so as to reduce the thermal resistance of the device and improve the heat dissipation effect.

In one possible implementation, when forming the gate pad and the drain pad, the method includes: the method comprises the steps of manufacturing a first grid electrode bonding pad section and a second grid electrode bonding pad section which are connected, wherein the width dimension of the first grid electrode bonding pad section is larger than that of the second grid electrode bonding pad section along the direction perpendicular to the first direction; and manufacturing a first drain electrode pad section and a second drain electrode pad section which are connected, wherein the width dimension of the first drain electrode pad section is larger than that of the second drain electrode pad section along the direction perpendicular to the first direction.

In one possible implementation, when the first gate pad section, the second gate pad section, the first drain pad section, and the second drain pad section are manufactured, further comprising: providing a second gate pad section at a position opposite to the first drain pad section, and providing a first gate pad section at a position opposite to the second drain pad section; in forming the first set of electrodes and the second set of electrodes, comprising: forming a first set of electrodes in a space between the first drain pad segment and the second gate pad segment; forming a second set of electrodes in a space between the second drain pad segment and the first gate pad segment; the arrangement direction of the plurality of electrodes in the first group of electrodes and the arrangement direction of the plurality of electrodes in the second group of electrodes are parallel to the first direction.

In this way, the first group of electrodes is disposed between the portion with the wider width of the gate pad and the portion with the narrower width of the drain pad, and the second group of electrodes is disposed between the portion with the narrower width of the gate pad and the portion with the wider width of the drain pad, so that the high temperature region of the first group of electrodes is staggered with the high temperature region of the second group of electrodes, the phenomenon of heat concentration is weakened, and further, the thermal resistance is reduced, and the heat dissipation effect is improved.

In one possible implementation, when the first gate pad section, the second gate pad section, the first drain pad section, and the second drain pad section are manufactured, further comprising: a first gate pad section is provided at a position opposite to the first drain pad section, and a second gate pad section is provided at a position opposite to the second drain pad section; in forming the first set of electrodes and the second set of electrodes, comprising: forming a first set of electrodes in a space between the first drain pad segment and the first gate pad segment; a second group of electrodes is formed in a space between the second drain pad section and the second gate pad section, and an arrangement direction of the plurality of electrodes in the first group of electrodes and an arrangement direction of the plurality of electrodes in the second group of electrodes all intersect the first direction.

Compared with the gate bonding pad with uniform width and the drain bonding pad with uniform width, the semiconductor device manufactured by the application can enable the number of the electrodes of the first group of electrodes to be smaller than the number of the electrodes of the second group of electrodes, so that the distance between two adjacent electrodes in the first group of electrodes can be increased; in addition, the width dimensions of the gate pad and the drain pad opposite to the second group of electrodes become smaller, so that the number of the second group of electrodes is increased, the distance between two adjacent electrodes can be increased, the thermal resistance is reduced, and the heat dissipation effect is improved.

In yet another aspect, the present application provides a semiconductor device. The semiconductor device includes: a substrate, a functional layer formed on the substrate, and a plurality of electrodes, source pads, drain pads, and gate pads formed on a side of the functional layer remote from the substrate; the plurality of electrodes comprise a plurality of sources, a plurality of drains and a plurality of grids, wherein the plurality of sources are electrically connected with the source bonding pads, the plurality of drains are electrically connected with the drain bonding pads, and the plurality of grids are electrically connected with the grid bonding pads; the grid electrode bonding pad and the drain electrode bonding pad are oppositely arranged and extend along a first direction; the plurality of electrodes includes a first group of electrodes and a second group of electrodes separated from each other, the first group of electrodes and the second group of electrodes being arranged in a space between the gate pad and the drain pad in a first direction; the gate pad comprises a first gate pad section and a second gate pad section, and the width dimension of the first gate pad section is larger than that of the second gate pad section along the direction perpendicular to the first direction; the drain pad includes a first drain pad segment and a second drain pad segment, a width dimension of the first drain pad segment being greater than a width dimension of the second drain pad segment in a direction perpendicular to the first direction.

In the semiconductor device provided by the application, the gate bonding pad comprises a wider part and a narrower part, and the drain bonding pad comprises a wider part and a narrower part, compared with the gate bonding pad with uniform width and the drain bonding pad with uniform width, the number of the electrodes of the first group of electrodes is smaller than that of the electrodes of the second group of electrodes, so that the distance between two adjacent electrodes in the first group of electrodes can be increased to reduce the thermal resistance; in addition, the width dimensions of the gate pad and the drain pad opposite to the second group of electrodes become smaller, so that the number of the second group of electrodes is increased, the distance between two adjacent electrodes can be increased, the thermal resistance is reduced, and the heat dissipation effect is improved.

In one possible implementation, the first drain pad segment is opposite the first gate pad segment, and the first set of electrodes is located in a space between the first drain pad segment and the second gate pad segment; the second drain pad segment is opposite to the second gate pad segment, and the second set of electrodes is located in a space between the second drain pad segment and the first gate pad segment.

In one possible implementation, the arrangement direction of the plurality of electrodes in the first set of electrodes and the arrangement direction of the plurality of electrodes in the second set of electrodes each intersect the first direction; the number of electrodes in the first set of electrodes is smaller than the number of electrodes in the second set of electrodes.

In one possible implementation, the spacing between adjacent two electrodes in the first set of electrodes is equal to the spacing between adjacent two electrodes in the second set of electrodes.

In one possible implementation, the second set of electrodes is proximate to an edge of the semiconductor device relative to the first set of electrodes.

The heat dissipation is performed by placing a large number of the second set of electrodes close to the device edge to fully utilize the inactive area of the device edge.

In one possible implementation, the plurality of electrodes further includes a third set of electrodes, the third set of electrodes and the second set of electrodes being arranged in a first direction within a space between the second drain pad segment and the first gate pad segment; the number of electrodes in the third set of electrodes is greater than the number of electrodes in the first set of electrodes.

That is, the electrode groups with a large number are arranged close to the edges of the devices, so that the heat dissipation effect is improved.

In one possible implementation, the plurality of electrodes includes N sets of phase separated electrodes; the number of electrodes in the electrode group located at the edge of the semiconductor device is greater than the number of electrodes in the electrode group located at the center of the semiconductor device among the N phase-separated electrode groups.

For example, when the plurality of electrodes includes 7 separate electrode groups, the number of electrodes of the first group and the seventh group at both ends is greater than the number of electrodes of the fourth group at the center. That is, the electrode group with a smaller number of electrodes is arranged at the center of the device, so that the heat concentration degree at the center of the device is weakened.

For another example, when the plurality of electrodes includes 8 separate electrode groups, the number of electrodes of the first group and the eighth group at both ends is greater than the number of electrodes of the fourth group and the fifth group at the center. That is, the electrode group with a smaller number of electrodes is arranged at the center of the device, so that the heat concentration degree at the center of the device is weakened.

Since the widths of the portions of the gate pad and the drain pad are reduced, the size of the entire device can be reduced.

In still another aspect, the present application also provides a method for manufacturing a semiconductor device, the method comprising:

forming a functional layer on one side of a substrate;

forming a plurality of electrodes and gate pads on one side of the functional layer away from the substrate, and gate pads and drain pads which extend in a first direction and are oppositely arranged;

in forming the drain pad and the gate pad, comprising:

the method comprises the steps of manufacturing a first grid electrode bonding pad section and a second grid electrode bonding pad section which are connected, wherein the width dimension of the first grid electrode bonding pad section is larger than that of the second grid electrode bonding pad section along the direction perpendicular to the first direction;

and manufacturing a first drain electrode pad section and a second drain electrode pad section which are connected, wherein the width dimension of the first drain electrode pad section is larger than that of the second drain electrode pad section along the direction perpendicular to the first direction.

In the semiconductor device manufactured by the manufacturing method, the gate pad comprises a wider portion and a narrower portion, and the drain pad comprises a wider portion and a narrower portion, compared with the gate pad with uniform width and the drain pad with uniform width, the electrode number of the first group of electrodes is smaller than that of the second group of electrodes, so that the interval between two adjacent electrodes in the first group of electrodes can be increased to reduce thermal resistance; in addition, the width dimensions of the gate pad and the drain pad opposite to the second group of electrodes become smaller, so that the number of the second group of electrodes is increased, the distance between two adjacent electrodes can be increased, the thermal resistance is reduced, and the heat dissipation effect is improved.

In one possible implementation, when the first gate pad section, the second gate pad section, the first drain pad section, and the second drain pad section are manufactured, further comprising: a first gate pad section is provided at a position opposite to the first drain pad section, and a second gate pad section is provided at a position opposite to the second drain pad section; in forming a plurality of electrodes, comprising: disposing a first set of electrodes in a space between the first drain pad section and the first gate pad section; a second set of electrodes is disposed in a space between the second drain pad segment and the second gate pad segment.

In one possible implementation, when forming the first set of electrodes and the second set of electrodes, the method includes: the arrangement direction of the plurality of electrodes in the first group of electrodes and the arrangement direction of the plurality of electrodes in the second group of electrodes intersect the first direction.

In still another aspect, the present application further provides an electronic device, including a controller and the semiconductor device in any one of the above-mentioned implementations or the semiconductor device manufactured in any one of the above-mentioned implementations, where the controller is connected to the drain pad through the first connection line; the controller is connected with the grid electrode bonding pad through a second connecting wire.

The electronic equipment provided by the embodiment of the application comprises the semiconductor device, so that the electronic equipment provided by the embodiment of the application and the semiconductor device of the technical scheme can solve the same technical problems and achieve the same expected effect.

In one possible implementation, the gate pad includes a first gate pad section and a second gate pad section connected, the first gate pad section having a width dimension greater than a width dimension of the second gate pad section in a direction perpendicular to the first direction; the drain electrode pad comprises a first drain electrode pad section and a second drain electrode pad section which are connected, and the width dimension of the first drain electrode pad section is larger than that of the second drain electrode pad section along the direction perpendicular to the first direction; the controller is connected with the first grid electrode pad section through a first connecting wire; the controller is connected with the first drain electrode pad section through a second connecting wire.

Drawings

Fig. 1 is a schematic diagram of a part of a base station;

FIG. 2 is an exploded view of a part of the structure of a mobile phone;

fig. 3 is a schematic diagram of a part of the structure of some electronic devices such as a base station or a mobile phone;

fig. 4 is a schematic structural view of a semiconductor device;

fig. 5 is a schematic structural view of another semiconductor device;

Fig. 6 is a schematic structural view of yet another semiconductor device;

fig. 7 is a top view of a semiconductor device;

FIG. 8 is a cross-sectional view A-A of FIG. 7;

FIG. 9 is a thermal profile of FIG. 7;

fig. 10 is a top view of a semiconductor device according to an embodiment of the present application;

FIG. 11 is a section B-B of FIG. 10;

FIG. 12 is a thermal profile of FIG. 10;

fig. 13 is a top view of a semiconductor device according to an embodiment of the present application;

FIG. 14 is a section C-C of FIG. 13;

Fig. 15 is a top view of a semiconductor device according to an embodiment of the present application;

fig. 16 is a top view of a semiconductor device according to an embodiment of the present application;

fig. 17 is a top view of a semiconductor device according to an embodiment of the present application;

FIG. 18 is a thermal profile of FIG. 17;

Fig. 19 is a top view of a semiconductor device according to an embodiment of the present application

Fig. 20 is a top view of a semiconductor device;

FIG. 21 is a thermal profile of FIG. 20;

fig. 22 is a top view of a semiconductor device according to an embodiment of the present application;

FIG. 23 is a section D-D of FIG. 22;

Fig. 24 is a top view of a semiconductor device according to an embodiment of the present application;

fig. 25 is a top view of a semiconductor device according to an embodiment of the present application;

Fig. 26 is a top view of a semiconductor device according to an embodiment of the present application;

fig. 27 is a top view of a semiconductor device according to an embodiment of the present application;

fig. 28 is a top view of a semiconductor device according to an embodiment of the present application

FIG. 29 is a thermal profile of FIG. 28;

Fig. 30 is a top view of a semiconductor device according to an embodiment of the present application;

Fig. 31 is a top view of a semiconductor device according to an embodiment of the present application.

Reference numerals:

11-a middle frame; 110-frame; 111-carrier plates;

12-a rear shell;

13-a display screen;

100-a circuit board;

A 101-semiconductor device; 102-a first electrical connection structure; 103-packaging the substrate;

200-a second electrical connection structure;

1-a substrate;

3-a functional layer;

31-a nucleation layer;

32-a channel layer;

33-a barrier layer;

34-a stress buffer layer;

35-isolating layer;

36-cap layer

41-Source;

42-grid;

43-drain electrode;

51-source pads; 511-a first source pad; 512-second source pads;

52-gate pads; 521-a first gate pad segment; 522-a second gate pad segment;

53-drain pad; 531-a first drain pad segment; 532-a second drain pad segment;

6-conducting channels;

7-a metal layer;

81-a first connection line; 82-second connection line.

Detailed Description

Embodiments of the present application provide an electronic device that may include a communication device (e.g., a base station, a cell phone), a wireless charging device, a medical device, a radar, a navigation device, a Radio Frequency (RF) plasma lighting device, an RF induction and microwave heating device, and so forth. The embodiment of the application does not limit the specific form of the electronic device.

In the above electronic devices, basically, the electronic devices include semiconductor devices, for example, a Power Amplifier (PA), where the PA mainly amplifies a radio frequency signal, and fig. 1 shows a simple schematic structure of a base station, which includes a control unit, where the control unit includes a radio transceiver, an antenna, a related signal processing circuit, and the like, and the control unit mainly includes: cell controllers, voice channel controllers, signaling channel controllers, and multi-way interfaces for expansion. The control unit of the base station generally controls several base transceiver stations, and is responsible for all mobile communication interface management, mainly allocation, release and management of radio channels, etc., by remote commands of the transceiver stations and the mobile stations.

With continued reference to fig. 1, the base station further includes a transmission unit connected to the core network, and control signaling, voice call or data service information on the core network side is sent to the control unit of the base station through the transmission unit, and the control unit processes the services.

Referring to fig. 1, the base station further includes a baseband unit and a Radio Frequency (RF) unit, where the baseband unit mainly performs functions of baseband modulation and demodulation, radio resource allocation, call processing, power control, soft handoff, and the like. The RF unit mainly completes conversion between an air radio frequency channel and a baseband digital channel, amplifies signals by a Power Amplifier (PA), sends the signals to an antenna through a radio frequency feeder line for transmission, and terminal equipment such as a mobile phone (mobile phone), a tablet personal computer (pad) and the like receives radio waves transmitted by the antenna through a wireless channel, and demodulates signals belonging to the user.

With continued reference to fig. 1, the base station further includes a power supply unit, which may be used to supply power to the transmission unit, the baseband unit, the control unit, and other structures.

Fig. 2 shows a block diagram of another electronic device, which may be a terminal device, such as a mobile phone, a tablet computer, a smart bracelet, or a personal computer (personal computer, PC), for example, a mobile phone, which may include a middle frame 11, a rear case 12, and a display 13. The middle frame 11 includes a carrying plate 111 for carrying the display 13, and a frame 110 surrounding the carrying plate 111 for a circle, and the carrying plate 111 carries a semiconductor device such as an AC/DC converter.

With the development of the fourth generation mobile communication technology (4th generation of wireless communications technologies,4G) to the fifth generation mobile communication technology (5th generation of wireless communications technologies,5G), the functional requirements of the above semiconductor device are also increasing, for example, higher frequency, higher voltage, higher output power and efficiency, etc.

Among the semiconductor materials that can be selected, gallium nitride (GaN) is a key material for fabricating semiconductor devices due to its characteristics of high thermal conductivity, high breakdown field strength, high saturated electron mobility, etc. For example, a high electron mobility transistor (high electron mobility transistor, HEMT) based on gallium nitride (GaN) is fabricated from an epitaxial single crystal film of GaN grown on a single crystal substrate. Monocrystalline substrates typically employ materials such as Sapphire (Sapphire), silicon carbide (SiC), or silicon (Si) single crystals, for example, when the substrate employs a silicon single crystal material, the resulting HEMT may be referred to as a gallium nitride on silicon (GaN-on-Si) HEMT device.

As shown in fig. 3, the semiconductor device 101 in the above-described apparatus is disposed on a substrate 103, for example, on a package substrate, and the semiconductor device 101 is disposed on the substrate 103 through a first electrical connection structure (for example, a metal layer) 102 so that the semiconductor device 101 can be signal-interconnected with other electronic devices on the substrate 103.

The substrate 103 is further disposed on the circuit board 100 through a second electrical connection structure 200, for example, the circuit board 1 may be a printed circuit board (printed circuit board, PCB), where the second electrical connection structure 200 may be a ball grid array (ball GRID ARRAY, BGA) or other electrical connection structure.

The semiconductor device 101 shown in fig. 3 may include a structure as shown in fig. 4, and in conjunction with fig. 4, fig. 4 is a cross-sectional view of a semiconductor device 101 according to an embodiment of the present application, the semiconductor device 101 includes: a substrate 1, a nucleation layer 31 formed on the substrate 1, a channel layer 32 formed on the nucleation layer 31, and a barrier layer 33 formed on the channel layer 32. That is, the film structures of the nucleation layer 31, the channel layer 32, and the barrier layer 33 are stacked in this order on the substrate 1 along the L direction shown in fig. 4.

With continued reference to fig. 4, in the semiconductor device 101, the nucleation layer 31, the channel layer 32, and the barrier layer 33 may each comprise a group IIIA nitride, i.e., may be made of any group IIIA nitride material. For example, the group IIIA nitride material may include one or a combination of at least two of Boron Nitride (BN), aluminum nitride (AlN), gallium nitride (GaN), indium nitride (InN), thallium nitride (TIN), and aluminum gallium nitride (AlGaN), or may include any alloy formed from group IIIA elements and group VA elements, such as indium gallium nitride (InGaN), aluminum indium gallium nitride (AlInGaN), gallium arsenic phosphorus nitride (GaAsPbN), aluminum indium gallium arsenic phosphorus nitride (AlInGaAsPbN), and the like.

By way of example, nucleation layer 31 may comprise an aluminum nitride (AlN) material. An aluminum nitride (AlN) material may be understood to refer to aluminum nitride (AlN) and any alloys thereof, such as aluminum gallium nitride (AlGaN), aluminum indium nitride (AlInN), aluminum indium gallium nitride (AlInGaN), aluminum indium gallium arsenide phosphide (AlInGaAsPbN), and the like. Among these aluminum nitride (AlN) alloys, aluminum has a high concentration and may contain at least one of gallium and indium in a small amount, or gallium and indium are not included, that is, the alloy concentration is relatively small with respect to the aluminum concentration.

Fig. 5 is a structural diagram of another semiconductor device 101 according to an embodiment of the present application, and the semiconductor device 101 shown in fig. 5 includes not only the substrate 1, the nucleation layer 31, the channel layer 32, and the barrier layer 33, but also other functional layer structures, compared with the semiconductor device 101 shown in fig. 4. For example, with continued reference to fig. 5, the semiconductor device 101 may further include a stress buffer layer 34, an isolation layer 35, and a cap layer 36, wherein the stress buffer layer 34 is stacked between the nucleation layer 31 and the channel layer 32, the isolation layer 35 is stacked between the channel layer 32 and the barrier layer 33, and the cap layer 36 is stacked on the barrier layer 33.

Fig. 4 and 5 are only exemplary of some of the film structures included in semiconductor device 101, and of course, more film structures may be added or some of the film structures may be removed based on these embodiments. The present application is not particularly limited to these functional layers integrated on the substrate 1.

With continued reference to fig. 4 and 5, the semiconductor device 101 further includes a Source (Source) 41, a Gate (Gate) 42, and a Drain (Drain) 43. A Source (Source) 41, a Gate (Gate) 42, and a Drain (Drain) 43 are formed on the sides of these functional layers 3 remote from the substrate 1.

In fig. 4 and 5, it is exemplarily shown that the semiconductor device 101 includes one source electrode 41, one gate electrode 42, and one drain electrode 43.

In other possible structures, as shown in fig. 6, fig. 6 illustrates that the semiconductor device 101 includes a plurality of electrodes, for example, a first electrode pair T1, a second electrode pair T2, a third electrode pair T3, a fourth electrode pair T4, a fifth electrode pair T5, and a sixth electrode pair T6, each of which includes a source 41, a drain 43, and a gate 42 between the source 41 and the drain 43.

In order to reduce the number of electrodes, as shown in fig. 6, adjacent first and second electrode pairs T1 and T2 may share a drain electrode 43, adjacent second and third electrode pairs T2 and T3 may share a source electrode 41, adjacent third and fourth electrode pairs T3 and T4 may share a drain electrode 43, adjacent fourth and fifth electrode pairs T4 and T5 may share a source electrode 41, and adjacent fifth and sixth electrode pairs T5 and T6 may share a drain electrode 43.

Fig. 7 is a plan view of the semiconductor device 101 according to the present application, and fig. 8 is a cross-sectional view taken along the A-A direction of fig. 7. Referring to fig. 7 and 8, a semiconductor device 101 includes a substrate 1, a functional layer 3 provided on the substrate 1, and a plurality of electrodes formed on a side of the functional layer 3 remote from the substrate 1, and a source pad (source pad) 51, a gate pad (gate pad) 52, and a drain pad (drain pad) 53 are provided on the surface of the semiconductor device 101.

Wherein the plurality of gates 42 may be connected to the gate pad 52 through a connection line, and the plurality of drains 43 may be electrically connected to the drain pad 53 through a connection line.

In some scenarios, the gate pad 52 and the drain pad 53 need to be electrically connected to peripheral circuits, respectively, for example, as in fig. 3, a controller may be provided on the circuit board 100, and the controller may be electrically connected to the gate pad 52 and the drain pad 53, respectively, through leads, so that the controller controls the semiconductor device 101.

In other cases, the source 41 may be grounded, for example, as shown in fig. 8, which shows an implementation structure of grounding the source 41, a metal layer 7 may be disposed on a side of the substrate 1 away from the functional layer 3, and the source 41 may be connected to the metal layer 7 through a conductive via 6 penetrating the functional layer 3 and the substrate 1. By way of example, the conductive via 6 may be a hole structure filled with a conductive material (e.g. copper).

As shown in fig. 7, the source pad 51 on the surface of the semiconductor device 101 may be connected to the source 41 in the vicinity thereof by a connection line, so that the electrical connection of the source pad 51 to the metal layer 7 is achieved.

Fig. 8 shows only one implementation of the grounding of the source 41, for example, as shown in fig. 7, all the sources 41 may be connected to the source pad 51 by connecting wires, and the source pad 51 is connected to the metal layer 7 by the conductive path 6 penetrating the functional layer 3 and the substrate 1, thereby realizing the grounding of the source 41.

One way of routing the connection lines is illustrated in fig. 7, but other routing ways may be used to route the connection lines.

In some examples, in order to satisfy the electrical connection of the gate pad 52 and the drain pad 53 with the peripheral circuit, the gate pad 52 and the drain pad 53 may be respectively designed in a stripe structure, for example, see fig. 7, the gate pad 52 and the drain pad 53 in a stripe structure are disposed in parallel at opposite sides of the device surface, and a plurality of electrodes are disposed in a space between the gate pad 52 and the drain pad 53.

With continued reference to fig. 7 and 8, the source pad 51 for the pin test may include a first source pad 511 and a second source pad 512 that are separated, and the first source pad 511 and the second source pad 512 are symmetrically disposed on the surface of the device, so that the stress of the two source pads 51 on the device is relatively symmetrical, and the stress concentration or the stress asymmetry may be prevented from affecting the performance of the device.

In the structure shown in fig. 7 and 8, the arrangement of the plurality of electrodes is relatively concentrated, and the active region where the plurality of electrodes are located (the active region is exemplarily shown in fig. 7 at a rough position) is close to the central region of the semiconductor device 101, and occupies only about 40% of the entire device area, and the inactive region surrounds the periphery of the active region and occupies more than 60% of the device area.

In the embodiment of the present application, the area occupied by the plurality of electrodes may be referred to as an active area due to the large amount of heat dissipation, and the area of the semiconductor device 101 other than the active area may be referred to as an inactive area, for example, the gate pad 52 and the drain pad 53, and the source pad 51 are in the inactive area in fig. 7.

As shown in fig. 9, fig. 9 shows the heat distribution of the diffusion of the active region in the structures shown in fig. 7 and 8, and four black dotted lines illustrate the heat distribution, and the thicker the black dotted line, the higher the representative temperature. As can be seen from the four black dashed lines with different thicknesses in fig. 9, heat is basically concentrated in the active region, and the closer to the edge of the active region, the closer to the passive region, the lower the temperature is, so that the passive region with a larger area cannot effectively participate in heat dissipation of the active region, resulting in higher junction temperature of the active region, thereby easily deteriorating the performance of the device.

Based on this, the embodiments of the present application provide some structures that can be implemented to reasonably use the space on the chip to reduce the thermal resistance of the device, as described in detail below.

Fig. 10 is a top view of a semiconductor device 101 according to an embodiment of the present application, and fig. 11 is a cross-sectional view taken along the direction B-B of fig. 10. The structures shown in fig. 10 and 11, as well as the structures shown in fig. 7 and 8 described above, are the same: the gate pads 52 and the drain pads 53 each having a stripe shape are aligned in the extending direction, for example, in the X direction shown in fig. 10, and the plurality of electrodes are aligned in the extending direction, which is also aligned in the X direction, with the gate pads 52 and the drain pads 53. A plurality of electrodes are disposed in parallel between the gate pad 52 and the drain pad 53.

The structure shown in fig. 10 and 11 is different from the structure shown in fig. 7 and 8 described above in that: in fig. 10 and 11, the plurality of electrodes are divided into a first group electrode Q1 and a second group electrode Q2, and each of the first group electrode Q1 and the second group electrode Q2 includes a plurality of electrodes, for example, in fig. 10, each of the first group electrode Q1 and the second group electrode Q2 includes 9 electrodes, of which four gates 42 are each.

In addition, the different points include: the first group electrode Q1 and the second group electrode Q2 have a space therebetween, and the source pad 51 is disposed in the space between the first group electrode Q1 and the second group electrode Q2.

As shown in fig. 12, the heat distribution of diffusion of the first group electrode Q1 and the second group electrode Q2 is shown in fig. 12, and four black dotted lines in each group electrode are shown as heat distribution diagrams, and the thicker the black dotted lines, the higher the representative temperature, the heat distribution diagram shown in fig. 12, and the heat distribution diagram shown in fig. 9, the more known: since the plurality of electrodes are divided into two groups by the source pad 51, that is, the device is divided into two separate heating elements by the source pad 51, that is, the active region is divided by the passive region, the heat is also dispersed, the passive region where the source pad 51 is located is utilized to dissipate heat, and the heat diffused by the two heating elements can diffuse toward the edge of the device, so that the passive region at the edge can be fully utilized to dissipate heat, and the junction temperature of the device can be reduced.

Fig. 13 is a top view of still another semiconductor device 101 according to an embodiment of the application, and fig. 14 is a cross-sectional view taken along the C-C direction of fig. 13. The structures shown in fig. 13 and 14 are similar to the structures shown in fig. 10 and 11 described above, in which the plurality of electrodes are divided into a plurality of groups, in the structures shown in fig. 10 and 11, the plurality of electrodes are divided into a first group electrode Q1 and a second group electrode Q2, whereas in the structures shown in fig. 13 and 14, the plurality of electrodes are divided into a first group electrode Q1 and a second group electrode Q2, and a third group electrode Q3, with a space between the first group electrode Q1 and the second group electrode Q2, a first source pad 511 being provided in the space between the first group electrode Q1 and the second group electrode Q2, and a space between the second group electrode Q2 and the third group electrode Q3, and a second source pad 512 being provided in the space between the second group electrode Q2 and the third group electrode Q3.

Fig. 15 is a top view of yet another semiconductor device 101 according to an embodiment of the application. The embodiment shown in fig. 15 differs from that shown in fig. 13 in that: in fig. 13, the number of the gates 402 is the same in the divided first, second and third groups of electrodes Q1, Q2 and Q3, and two gates are used. However, in fig. 15, the number of the gates 402 is greater in the first group electrode Q1 and the third group electrode Q3 located at both ends than in the second group electrode Q2 located in the middle, for example, two gates 402 are located in the first group electrode Q1 and the third group electrode Q3, and one gate is located in the second group electrode Q2.

The method comprises the following steps: when the plurality of electrodes are divided into at least two groups, the number of gates of each group may be the same or different. If the number of gates in each group is different, the number of gates in the end electrode group may be greater than the number of gates in the middle electrode group.

With continued reference to fig. 13 and 15, when the plurality of electrodes are divided into a plurality of groups of electrodes having a pitch therebetween, the source pad 51 may be disposed within the pitch between adjacent two electrode groups. The number of gates of the adjacent two sets of electrodes may be equal as shown in fig. 13 or unequal as shown in fig. 15.

When the different structures shown in fig. 10 to 15 are adopted, compared with fig. 7, the highest temperature can be reduced by 2% to 10% under the same power, the highest temperature of the device is obviously reduced, and the heat dissipation effect of the active region is improved.

In addition, in the different embodiments described above, the examples show that in each set of electrodes, the ends of the adjacent two electrodes are flush, and in other examples, the ends of the adjacent two electrodes may not be flush, but rather protrude one with respect to the other.

In addition, in the above-described different embodiments, in each set of electrodes illustrated, a plurality of electrodes may enclose a rectangular structure, but may enclose other shapes, such as a circle or an ellipse.

In the different embodiments described above, the width of each electrode in each set of electrodes is equal or unequal. The length of the plurality of electrodes in each group of electrodes may be equal or unequal.

Fig. 16 is a top view of yet another semiconductor device according to an embodiment of the present application. Fig. 16 is similar to fig. 13 described above, in which the plurality of electrodes are divided into a first group electrode Q1 and a second group electrode Q2 which are separated, the first source pad 511 and the second source pad 512 are each disposed in a space between the first group electrode Q1 and the second group electrode Q2, and in fig. 16, the arrangement direction of the first source pad 511 and the second source pad 512 intersects with the arrangement direction of the plurality of electrodes, for example, the plurality of electrodes are arranged in the X direction, and the first source pad 511 and the second source pad 512 are arranged in the Y direction, that is, perpendicular or nearly perpendicular to each other. In fig. 13, the arrangement direction of the first source pad 511 and the second source pad 512 coincides with the arrangement direction of the plurality of electrodes, and are all arranged in the X direction.

With the embodiment shown in fig. 16, the dimension d between two adjacent gates 42 in fig. 16 can be increased while ensuring that the dimension of the entire chip in the X direction is unchanged, and thus, the heat dissipation effect can be improved.

Or under the condition of ensuring that the dimension D between two adjacent electrodes is unchanged, the dimension D of the whole device along the X direction can be reduced, so that the device meets the miniaturization design requirement.

In combination with the different examples illustrated in fig. 11, 14, 15 and 16, the structures of the drain pad 513 and the gate pad 512 are not changed compared with the example in fig. 7, and only the positions of the first source pad 511 and the second source pad 512 need to be adjusted, which is easy to implement in the manufacturing process and does not present challenges to the process.

The embodiment of the application also provides a method for preparing the semiconductor device, which comprises the following steps:

And S11, forming a functional layer on one side of the substrate.

S12: a plurality of electrodes, source pads, gate pads, and drain pads are formed on a side of the functional layer remote from the substrate.

In performing S12, that is, when forming the plurality of electrodes, the source pad, the gate pad, and the drain pad, it includes:

In this way, the semiconductor device 101 of any one of the above-described embodiments of fig. 10 to 15 can be manufactured. How to reduce the thermal resistance of the semiconductor device manufactured by this method has been explained above and will not be described here.

Fig. 17 is a top view of yet another semiconductor device according to an embodiment of the present application. In fig. 17, as in the embodiment of fig. 13 described above, the plurality of electrodes are divided into three groups, namely, a first group electrode Q1, a second group electrode Q2, and a third group electrode Q3, with a first source pad 511 disposed between the first group electrode Q1 and the second group electrode Q2, and a second source pad 512 disposed between the second group electrode Q2 and the third group electrode Q3.

Fig. 17 differs from the above-described fig. 13 in that: the gate pad 52 includes a first gate pad segment 521 and a second gate pad segment 522, the first gate pad segment 521 having a width L1 greater than a width L2 of the second gate pad 522; and, the drain pad 53 includes a first drain pad section 531 and a second drain pad section 532, and a width L3 of the first drain pad section 531 is greater than a width L4 of the second drain pad 532.

The width of the drain pad and the width of the gate pad refer to the dimension in the direction perpendicular to the extending direction of the drain pad, for example, the drain pad extends in the X direction, and the width of the drain pad is the dimension in the Y direction.

As further shown in fig. 17, the first gate pad 531 having a wider width is opposite to the second drain pad 522 having a narrower width, and the first group electrode Q1 is located therein, and the second gate pad 532 having a narrower width is opposite to the first drain pad 521 having a wider width. The second group of electrodes Q2 is located therein, the first gate pad 531 having a wider width is opposite to the second drain pad 522 having a narrower width, and the third group of electrodes Q3 is located therein.

The surface of the first gate pad 531 facing away from the first group electrode Q1 is flush with the surface of the second gate pad 532 facing away from the second group electrode Q2. The surface of the second drain pad 522 remote from the first group electrode Q1 is flush with the surface of the first drain pad 521 remote from the second group electrode Q2.

In some examples, the length dimensions of the plurality of electrodes are uniform, as in fig. 17 the dimensions of each electrode in the Y-direction are the same. In this way, the center lines M1, M2 and M3 of the first, second and third groups of electrodes Q1, Q2, Q3 are not on the same straight line, but are offset from each other, and further, as shown in fig. 18, the active regions of the first, second and third groups of electrodes Q1, Q2, Q3 are offset from each other, the high temperature region of the first group of electrodes Q1 (as shown by the black dotted line in fig. 18) is adjacent to the second gate pad segment 522 with a narrower width at the lower side thereof, the high temperature region of the second group of electrodes Q2 is adjacent to the second drain pad segment 532 with a narrower width at the upper side thereof, and the high temperature region of the third group of electrodes Q3 is adjacent to the second gate pad segment 522 with a narrower width at the lower side thereof, that is, so that the adjacent two active regions are offset from each other, the degree of aggregation of the adjacent two high temperature regions is weakened, and thus the heat dissipation effect can be further improved.

With continued reference to fig. 17 and 18, since the width of the portions of the drain pad 53 and the gate pad 52 is narrowed, the device can be reduced in size in the width direction of these pads, as in the reduced S size of fig. 18.

In the structures shown in fig. 17 and 18, the number of electrodes in each group is the same. In other examples, the number of electrodes of the second group of electrodes Q2 located in the middle may be smaller than the number of electrodes of the first group of electrodes Q1 and the third group of electrodes Q3 located at both ends. In this way, the passive regions of the edge can be made to spread heat effectively.

When the drain pad 53 and the gate pad 52 have a partially wide and partially narrow structure, as in fig. 18, when the drain pad 53 needs to be electrically connected to the controller, the drain pad 53 may be electrically connected to the controller using the first connection line 81 connected to the first drain pad segment 531 having a wider width. Similarly, when the gate pad 52 needs to be electrically connected to the controller, the gate pad 52 may be electrically connected to the controller using the second connection line 82 connected to the first gate pad segment 521 having a wider width.

Fig. 19 is a top view of yet another semiconductor device provided in an embodiment of the present application. The difference between the structure shown in fig. 19 and the structure shown in fig. 17 is that: in fig. 7, a first source pad 511 is disposed in a space between the first group electrode Q1 and the second group electrode Q2, and a second source pad 512 is disposed in a space between the second group electrode Q2 and the third group electrode Q3. In fig. 19, the first source pad 511 and the second source pad 512 are disposed outside the area surrounded by the first group electrode Q1 and the second group electrode Q2, and the third group electrode Q3, that is, the first source pad 511 and the second source pad 512 are disposed near the edge of the device.

As shown in fig. 17 and 19, in the structure that can be implemented, the first drain pad segment 531 and the second drain pad segment 532 are in a unitary structure, and the first gate pad segment 521 and the second gate pad segment 522 are in a unitary structure. That is, in the manufacturing process, a metal layer extending in the X direction may be formed on the device surface, and then the metal layer may be patterned to form the gate pad 52 and the drain pad 53 having different widths.

In the semiconductor device 101 shown in fig. 7 to 19 described above, one arrangement manner of the plurality of electrodes is given in which the arrangement direction of the plurality of electrodes coincides with the extending direction of the gate pad 52 and the drain pad 53, and as shown in fig. 19, the plurality of electrodes are arranged in the X direction, and the extending direction of the gate pad 52 and the drain pad 53 is also in the X direction.

Fig. 20 shows another arrangement of the plurality of electrodes, in which the plurality of electrodes are divided into a plurality of groups, and the arrangement direction of the plurality of electrodes in each group intersects with the extending directions of the gate pad 52 and the drain pad 53, for example, in fig. 20, the extending directions of the gate pad 52 and the drain pad 53 are X-directions, and the arrangement direction of the plurality of electrodes in each group is Y-directions.

Further, as shown in fig. 20, the arrangement direction of the plurality of electrode groups coincides with the extending direction of the gate pad 52 and the drain pad 53. As shown in fig. 20, five sets of electrode groups are illustrated, which are arranged along the X direction, and the extending directions of the gate pad 52 and the drain pad 53 are also the X direction.

With continued reference to fig. 20, the source, drain and gate electrodes in each set of electrodes are not explicitly shown in fig. 20, but rather the gate electrodes are simply shown with black lines, not shown with respect to the source and drain electrodes. The following views are similar, and for clarity of illustration of other structures, neither source nor drain are shown. In the product structure, however, as described above with respect to fig. 4-6, each gate includes a source and a drain on both sides.

Fig. 21 shows the thermal profile of fig. 20, since in this embodiment, a plurality of electrodes are disposed in a concentrated manner, the active regions where the plurality of electrodes are located (fig. 21 exemplarily shows the approximate positions of the active regions) are concentrated, and four black dotted lines showing the thermal profile in each group of electrodes are concentrated in the active regions, and the closer to the edge of the active device, even closer to the passive region, the lower the temperature, so that the passive region with a larger area cannot effectively participate in the heat dissipation of the active region, and further, the junction temperature of the active region is higher, which tends to deteriorate the performance of the device.

With respect to the electrode layout manners of fig. 20 and 21, some structures that can be implemented to reduce thermal resistance are also provided in the embodiments of the present application, which are described below.

Fig. 22 is a top view of a semiconductor device 101 according to an embodiment of the application, and fig. 23 is a cross-sectional view taken along the direction D-D of fig. 22. The structure shown in fig. 22 and 23 is different from the above-described fig. 20 and 21 in that: the gate pad 52 includes a first gate pad segment 521 and a second gate pad segment 522, the first gate pad segment 521 having a width L1 greater than a width L2 of the second gate pad 522; and, the drain pad 53 includes a first drain pad section 531 and a second drain pad section 532, and a width L3 of the first drain pad section 531 is greater than a width L4 of the second drain pad 532.

Also, as shown in fig. 22, the wider first gate pad segment 521 is opposite to the wider first drain pad segment 531 with the first group electrode Q1 located therein; the narrower width second gate pad 532 is opposite the narrower width second drain pad 522 with the second set of electrodes Q2 located therein; the wider first gate pad segment 521 is opposite to the wider first drain pad segment 531 with the third group of electrodes Q3 located therein; the narrower width second gate pad 532 is opposite the narrower width second drain pad 522 with the fourth set of electrodes Q4 located therein; the wider first gate pad segment 521 is opposite to the wider first drain pad segment 531 with the fifth group electrode Q5 located therein.

In some constructions, as in fig. 22, the surface of the first gate pad 531 remote from the first set of electrodes Q1 is flush with the surface of the second gate pad 532 remote from the second set of electrodes Q2. The surface of the second drain pad 522 remote from the first group electrode Q1 is flush with the surface of the first drain pad 521 remote from the second group electrode Q2.

Referring to fig. 20 and 22, each of the electrode groups in the gate pad 52 and the drain pad 53 of fig. 20 includes 10 gates, that is, two adjacent electrode groups include 20 gates, such as the first group electrode Q1 and the second group electrode Q2 each include 10 gates, and when the structure shown in fig. 22 is adopted, it is exemplified that 8 gates may be disposed in the first group electrode Q1 between the first gate pad section 521 and the first drain pad section 531, and 12 gates may be disposed in the second group electrode Q2 between the second gate pad section 522 and the second drain pad 532, that is, the total sum of the gates of the first group electrode Q1 and the second group electrode Q2 is maintained.

Then, when the width L1 of the first gate pad segment 521 in fig. 22 is the same as the width of the gate pad 52 in fig. 20, and the width L3 of the first drain pad segment 531 is the same as the width of the drain pad 53 in fig. 20, the interval t1 between two adjacent gates of the first group electrode Q1 may be increased when the scheme of fig. 22 of the embodiment of the present application is adopted, and thus, the heat dissipation effect of the first group electrode Q1 may be improved. The third group of electrodes Q3 and the fifth group of electrodes Q5, similar to the first group of electrodes Q1, may increase the space between two adjacent gates to reduce thermal resistance and improve heat dissipation.

With continued reference to fig. 22, when the width of the second gate pad segment 522 is reduced from L1 to L2 and the width of the second drain pad 532 is reduced from L3 to L4, for example, when the width is reduced from l1=100 nm to l2=20 nm and l3=100 nm to l4=20 nm, the distance between the second gate pad segment 522 and the second drain pad 532 is increased by 80×2=160 nm, and after the reduced 2 gates in the first group electrode Q1 are increased to the second group electrode Q2, since the distance between the adjacent two gates is substantially 40nm to 50nm, even if the reduced 2 gates in the first group electrode Q1 are increased to the second group electrode Q2, the thermal resistance of the second group electrode Q2 can be reduced and the heat dissipation effect can be improved.

In some examples, the width L1 of the first gate pad segment 521 and the width L2 of the second gate pad segment 522 may satisfy: L1/L2 is more than or equal to 5 and less than or equal to 8. For example, 5.ltoreq.L1/L2.ltoreq.7, 5.ltoreq.L1/L2.ltoreq.6. For example, 100 μm.ltoreq.L1.ltoreq.120μm,5 μm.ltoreq.L2.ltoreq.20μm.

In some examples, the width L3 of the first drain pad segment 531 may satisfy 5.ltoreq.L3/L4.ltoreq.8 with the width L4 of the second drain pad segment 532. For example, 5.ltoreq.L3/L4.ltoreq.7, 5.ltoreq.L3/L4.ltoreq.6. For example, 100 μm.ltoreq.L3.ltoreq.120μm,5 μm.ltoreq.L4.ltoreq.20μm.

In some examples, the width L1 of the first gate pad segment 521 may be equal to the width L3 of the first drain pad segment 531, or the width L1 of the first gate pad segment 521 may not be equal to the width L3 of the first drain pad segment 531.

In some examples, the width L2 of the second gate pad segment 522 may or may not be equal to the width L4 of the second drain pad segment 532, or the width L4 of the second drain pad segment 532.

Fig. 24 is a top view of yet another semiconductor device 101 according to an embodiment of the application. This embodiment differs from the example of fig. 22 described above in that: in the gate pad 52 of fig. 22, the first gate pad segments 521 and the second gate pad segments 522 are alternately arranged along the extending direction of the gate pad 52, that is, the second gate pad segments 522 are between two adjacent first gate pad segments 521, the first gate pad segments 521 are between two adjacent second gate pad segments 522, and the first gate pad segments 521 having a wider width are located at both ends. In addition, in the drain pad 53 of fig. 22, the first drain pad segments 531 and the second drain pad segments 532 are alternately arranged along the extending direction of the drain pad 53, that is, the second drain pad segments 532 are located between two adjacent first drain pad segments 531, the first drain pad segments 531 are located between two adjacent second drain pad segments 532, and the first drain pad segments 531 having a wider width are located at both ends.

In fig. 24, among the gate pads 52, the second gate pad segment 522 having a narrower width is located at both ends, and the first gate pad segment 521 having a wider width is left. Of the drain pads 53, at both ends are second drain pad segments 532 having a narrower width, and the remainder are first drain pad segments 531 having a wider width.

In fig. 24, compared with fig. 22, the number of electrodes in the electrode groups at both ends is larger, so that the passive region at the edge of the device can be fully utilized to dissipate heat, and the number of electrodes in the electrode group in the middle is smaller, so that the heat accumulation degree in the central region of the device is weakened, and the thermal resistance of the whole device is reduced.

Fig. 25 is a top view of yet another semiconductor device 101 according to an embodiment of the application. In the embodiment shown in fig. 25, in the gate pad 52, located at both ends is a second gate pad segment 522 having a narrower width. In the drain pad 53, located at both ends are second drain pad segments 532 having a narrower width.

With continued reference to fig. 25, in the gate pad 52, the first gate pad segment 521 and the second gate pad segment 522 are alternately arranged along the extending direction of the gate pad 52. In the drain pad 53, the first drain pad segment 531 and the second drain pad segment 532 are alternately arranged along the extending direction of the drain pad 53.

In fig. 25, at least two sets of electrodes are arranged between the opposite second gate pad segment 522 and second drain pad segment 532 at both ends, for example, two sets are shown in fig. 25. A set of electrode sets is disposed between the intermediate, opposing second gate pad segment 522 and second drain pad segment 532 to attenuate the extent to which heat is concentrated in the central region of the device, thereby reducing the thermal resistance of the overall device.

This can be understood as follows: when N phase-separated electrode groups are included, the number of electrodes in the electrode groups at both ends is greater than the number of electrodes in the electrode group at the center among the N phase-separated electrode groups. For example, when 5 electrode groups are included, the number of electrodes in the first group of electrodes and the fifth group of electrodes at both ends is greater than that in the third group of electrodes at the middle; for another example, when 6 electrode groups are included, the number of electrodes in the first and sixth groups of electrodes at both ends is greater than the number of electrodes in the third and fourth groups of electrodes at the middle.

Fig. 26 is a top view of yet another semiconductor device 101 according to an embodiment of the application. The differences between the example structure of fig. 26 and the example structure of fig. 22 include: in fig. 22, the first source pad 511 and the second source pad 512 are disposed outside the area surrounded by the plurality of electrodes; in fig. 26, the first and second source pads 511 and 512 are adjusted to be located between adjacent two electrode groups, for example, in fig. 26, the first and second source pads 511 and 512 are located between the third and fourth group electrodes Q3 and Q4. The arrangement direction of the first source pad 511 and the second source pad 512 coincides with the extension direction of the drain electrode 53 and the gate electrode 52, i.e., the two source pads are arranged in the X direction, for example.

Fig. 27 is a top view of yet another semiconductor device 101 according to an embodiment of the application. In fig. 27, the first source pad 511 and the second source pad 512 are respectively located at different positions, for example, the first source pad 511 is located between the second group electrode Q2 and the third group electrode Q3, and the second source pad 512 is located between the third group electrode Q3 and the fourth group electrode Q4.

In the different embodiments illustrated in fig. 26 and 27, the first source pad 511 and the second source pad 512 are as close as possible to the middle active region, avoiding excessive temperatures in the central region of the device.

Fig. 28 is a top view of yet another semiconductor device 101 according to an embodiment of the application. In fig. 22, a first gate pad segment 521 having a wider width is opposed to a first drain pad segment 531 having a wider width, in which a plurality of electrodes are arranged, as compared with the above-described example of fig. 22; the second gate pad 532 having a narrower width is opposite to the second drain pad 522 having a narrower width, and a plurality of electrodes are arranged therein; in fig. 28, the first gate pad segment 521 with a wider width is opposite to the second drain pad segment 532 with a narrower width, and the second gate pad segment 522 with a narrower width is opposite to the first drain pad segment 531 with a wider width.

Fig. 29 shows the thermal profile of the plurality of electrode sets of fig. 28, with the black dashed lines indicating the approximate locations of the active region for heat dissipation. Since in this embodiment, the first gate pad segment 521 with a wider width is opposite to the second drain pad segment 532 with a narrower width, and the second gate pad segment 522 with a narrower width is opposite to the first drain pad segment 531 with a wider width, the thermal profiles of the two adjacent electrode groups are staggered, so that the regions with higher temperature can be staggered, and the heat dissipation effect of the device is improved.

In the embodiment of fig. 28, compared with the example of fig. 21 described above, the device can also be reduced in size in the S direction so that the device satisfies the miniaturization design, with a considerable heat dissipation effect being ensured.

Fig. 30 is a top view of yet another semiconductor device 101 shown in an embodiment of the application. The differences from the example of fig. 29 include: in fig. 29, the first source pad 511 and the second source pad 512 are each disposed in an area other than the active area in which the plurality of electrode groups are located, whereas in fig. 30, the first source pad 511 and the second source pad 512 are interposed between adjacent two active areas.

As shown in fig. 22 to 30, in the above-described structure, the first drain pad segment 531 and the second drain pad segment 532 having different widths are integrally formed, and the first gate pad segment 521 and the second gate pad segment 522 having different widths are integrally formed.

When the drain pad 53 and the gate pad 52 have a partially wide and partially narrow structure, as in fig. 31, when the drain pad 53 needs to be electrically connected to the controller, the drain pad 53 may be electrically connected to the controller using the first connection line 81 connected to the first drain pad segment 531 having a wider width. Similarly, when the gate pad 52 needs to be electrically connected to the controller, the gate pad 52 may be electrically connected to the controller using the second connection line 82 connected to the first gate pad segment 521 having a wider width. Interconnecting the semiconductor device with a controller.

When the different structures from fig. 22 to fig. 31 are adopted, compared with fig. 20, the highest temperature can be reduced by 3% to 15% under the same power, the highest temperature of the device is obviously reduced, and the heat dissipation effect of the active region is improved.

and S21, forming a functional layer on one side of the substrate.

S22: a plurality of electrodes and gate pads are formed on a side of the functional layer away from the substrate, and gate pads and drain pads are each extended in a first direction and are oppositely arranged.

In performing S22, i.e., in forming the drain pad and the gate pad, it includes:

Thus, the semiconductor device 101 of any one of the above-described embodiments of fig. 22 to 31 can be manufactured. The explanation of how the thermal resistance of the semiconductor device manufactured by this method is reduced is also given above and will not be repeated here.

In the description of the present specification, a particular feature, structure, material, or characteristic may be combined in any suitable manner in one or more embodiments or examples.

The foregoing is merely illustrative of the present application, and the present application is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A semiconductor device, comprising:

A substrate;

A functional layer formed on one side of the substrate;

A plurality of electrodes, source pads, drain pads and gate pads, all formed on a side of the functional layer remote from the substrate;

the grid electrode bonding pad and the drain electrode bonding pad are oppositely arranged and extend along a first direction;

The plurality of electrodes includes a first group of electrodes and a second group of electrodes separated from each other, the first group of electrodes and the second group of electrodes being arranged in a space between the gate pad and the drain pad along the first direction;

The source pads are disposed in a space between the first set of electrodes and the second set of electrodes.

2. The semiconductor device according to claim 1, wherein,

The arrangement direction of the plurality of electrodes in the first group of electrodes and the arrangement direction of the plurality of electrodes in the second group of electrodes are parallel to the first direction; or alternatively

The arrangement direction of the plurality of electrodes in the first group of electrodes and the arrangement direction of the plurality of electrodes in the second group of electrodes are intersected with the first direction.

3. The semiconductor device of claim 1 or 2, wherein the source pad comprises a first source pad and a second source pad;

the first source pad and the second source pad are both located in a space between the first set of electrodes and the second set of electrodes.

4. The semiconductor device according to claim 3, wherein an arrangement direction of the first source pad and the second source pad is parallel to the first direction.

5. The semiconductor device of claim 1 or 2, wherein the source pad comprises a first source pad and a second source pad;

the plurality of electrodes further includes a third group of electrodes, the first group of electrodes, the second group of electrodes, and the third group of electrodes being arranged in the first direction within a space between the gate pad and the drain pad, the second group of electrodes being located between the first group of electrodes and the third group of electrodes;

The first source pad is located in a space between the first set of electrodes and the second set of electrodes, and the second source pad is located in a space between the second set of electrodes and the third set of electrodes.

6. The semiconductor device according to claim 5, wherein an arrangement direction of a plurality of electrodes in the first group of electrodes, the second group of electrodes, and the third group of electrodes is parallel to the first direction;

the first set of electrodes and the third set of electrodes being adjacent to an edge of the semiconductor device relative to the second set of electrodes;

the number of electrodes in the first set of electrodes is greater than the number of electrodes in the second set of electrodes;

the number of electrodes in the third set of electrodes is greater than the number of electrodes in the second set of electrodes.

7. A semiconductor device according to any one of claims 1 to 5, wherein,

The grid electrode pad comprises a first grid electrode pad section and a second grid electrode pad section which are connected, and the width dimension of the first grid electrode pad section is larger than that of the second grid electrode pad section along the direction perpendicular to the first direction;

The drain pad includes a first drain pad segment and a second drain pad segment connected, and a width dimension of the first drain pad segment is greater than a width dimension of the second drain pad segment along a direction perpendicular to the first direction.

8. The semiconductor device according to claim 7, wherein,

The first drain pad segment is opposite to the second gate pad segment, and the first group of electrodes is located in a space between the first drain pad segment and the second gate pad segment;

the second drain pad segment is opposite to the first gate pad segment, and the second group of electrodes is located in a space between the second drain pad segment and the first gate pad segment;

The arrangement direction of the plurality of electrodes in the first group of electrodes and the arrangement direction of the plurality of electrodes in the second group of electrodes are parallel to the first direction.

9. The semiconductor device according to claim 7, wherein,

The first drain pad segment is opposite to the first gate pad segment, and the first group of electrodes is located in a space between the first drain pad segment and the first gate pad segment;

The second drain pad segment is opposite to the second gate pad segment, and the second group of electrodes is located in a space between the second drain pad segment and the second gate pad segment;

10. The semiconductor device of claim 9, wherein the semiconductor device comprises a semiconductor substrate,

The number of electrodes in the first set of electrodes is less than the number of electrodes in the second set of electrodes.

11. A semiconductor device according to any one of claims 7 to 10, wherein,

The width dimension of the first grid electrode pad section is L1, and the width dimension of the second grid electrode pad section is L2, wherein L1/L2 is more than or equal to 5 and less than or equal to 8; and/or the number of the groups of groups,

The width dimension of the first drain electrode pad section is L3, and the width dimension of the second drain electrode pad section is L4, wherein L3/L4 is more than or equal to 5 and less than or equal to 8.

12. The semiconductor device of any of claims 7-11, wherein a side of the first drain pad segment remote from the first set of electrodes is flush with a side of the second gate pad segment remote from the second set of electrodes;

The side of the second gate pad segment remote from the first set of electrodes is flush with the side of the first gate pad segment remote from the second set of electrodes.

13. A semiconductor device according to any one of claims 7 to 12, wherein,

The first grid electrode bonding pad section and the second grid electrode bonding pad section are of an integrated structure;

the first drain pad segment and the second drain pad segment are in an integral structure.

14. A method of manufacturing a semiconductor device, comprising:

forming a functional layer on one side of a substrate;

the drain electrode bonding pad and the grid electrode bonding pad which extend along the first direction and are oppositely arranged are manufactured;

in the space between the gate pad and the drain pad, a first group of electrodes and a second group of electrodes are prepared to be separated from each other, and the first group of electrodes and the second group of electrodes are arranged along the first direction;

15. The method for manufacturing a semiconductor device according to claim 14, wherein when forming the gate pad and the drain pad, comprising:

And manufacturing a first drain electrode bonding pad section and a second drain electrode bonding pad section which are connected, wherein the width dimension of the first drain electrode bonding pad section is larger than that of the second drain electrode bonding pad section along the direction perpendicular to the first direction.

16. The method for manufacturing a semiconductor device according to claim 15, wherein when manufacturing the first gate pad section, the second gate pad section, the first drain pad section, and the second drain pad section, further comprising:

Providing the second gate pad section at a position opposite to the first drain pad section, and providing the first gate pad section at a position opposite to the second drain pad section;

in forming the first set of electrodes and the second set of electrodes, comprising:

forming the first set of electrodes in a space between the first drain pad segment and the second gate pad segment;

forming the second set of electrodes in a space between the second drain pad segment and the first gate pad segment;

17. The method for manufacturing a semiconductor device according to claim 15, wherein when manufacturing the first gate pad section, the second gate pad section, the first drain pad section, and the second drain pad section, further comprising:

providing the first gate pad section at a position opposite to the first drain pad section, and providing the second gate pad section at a position opposite to the second drain pad section;

Forming the first set of electrodes in a space between the first drain pad segment and the first gate pad segment;

The second group of electrodes is formed in a space between the second drain pad section and the second gate pad section, and the arrangement direction of the plurality of electrodes in the first group of electrodes and the arrangement direction of the plurality of electrodes in the second group of electrodes all intersect with the first direction.

18. A semiconductor device, comprising:

A substrate;

A functional layer formed on one side of the substrate;

19. The semiconductor device of claim 18, wherein,

The first drain pad segment is opposite to the first gate pad segment, and the first group of electrodes is located in a space between the first drain pad segment and the second gate pad segment;

The second drain pad segment is opposite to the second gate pad segment, and the second set of electrodes is located in a space between the second drain pad segment and the first gate pad segment.

20. The semiconductor device according to claim 19, wherein an arrangement direction of the plurality of electrodes in the first group of electrodes and an arrangement direction of the plurality of electrodes in the second group of electrodes each intersect the first direction;

21. The semiconductor device of claim 20, wherein the second set of electrodes is proximate an edge of the semiconductor device relative to the first set of electrodes.

22. The semiconductor device of claim 21, wherein the plurality of electrodes further comprises a third set of electrodes, the third set of electrodes and the second set of electrodes being arranged in the first direction within a space between the second drain pad segment and the first gate pad segment;

the number of electrodes in the third set of electrodes is greater than the number of electrodes in the first set of electrodes.

23. The semiconductor device of claim 18, wherein,

24. A semiconductor device according to any one of claims 18 to 23,

25. The semiconductor device of any of claims 18-24, wherein a side of the first drain pad segment remote from the first set of electrodes is flush with a side of the second gate pad segment remote from the second set of electrodes;

26. The semiconductor device according to any one of claims 18 to 25, wherein,

27. A method of manufacturing a semiconductor device, comprising:

forming a functional layer on one side of a substrate;

in forming the drain pad and the gate pad, comprising:

28. The method of manufacturing a semiconductor device according to claim 27, wherein when the first gate pad section, the second gate pad section, the first drain pad section, and the second drain pad section are manufactured, further comprising:

in forming the plurality of electrodes, comprising:

Disposing a first set of electrodes in a space between the first drain pad segment and the first gate pad segment;

A second set of electrodes is disposed in a space between the second drain pad segment and the second gate pad segment.

29. The method for manufacturing a semiconductor device according to claim 28, wherein when forming the first group of electrodes and the second group of electrodes, comprising:

30. An electronic device, comprising:

A controller;

A semiconductor device according to any one of claims 1 to 13, 18 to 26, or a method of manufacturing a semiconductor device according to any one of claims 14 to 17, 27 to 29;

the controller is connected with the drain electrode pad through a first connecting wire;

the controller is connected with the grid electrode bonding pad through a second connecting wire.

31. The electronic device of claim 30, wherein the electronic device comprises a memory device,

The drain electrode pad comprises a first drain electrode pad section and a second drain electrode pad section which are connected, and the width dimension of the first drain electrode pad section is larger than that of the second drain electrode pad section along the direction perpendicular to the first direction;

The controller is connected with the first grid electrode pad section through the first connecting wire;

The controller is connected with the first drain electrode pad section through the second connecting wire.