CN118113632A - Flash memory storage chip - Google Patents

Abstract

The application discloses a flash memory storage chip, which comprises a storage module, wherein the storage module comprises a data storage unit and a page buffer; the conversion module comprises a storage control unit and a data receiving unit, and is connected with the storage module to control the data access of the storage module; the data receiving unit is used for receiving the instruction and the stored data information, and the storage control unit is used for writing data into the first cache area and the second cache area of the page buffer based on the instruction; generating data in a third buffer area of the page buffer; the data generated by the third buffer area is obtained by carrying out logic operation on the data of the first buffer area and the data of the second buffer area, and the data of the first buffer area, the second buffer area and the third buffer area determine first data information; and writing the first data information cached by the page buffer into the data storage unit. By the mode, the reliability of the data stored by the storage device is improved by depending on the logic operation capability inside the storage chip.

Description

Flash memory storage chip

Technical Field

The present application relates to the field of memory, and in particular, to a flash memory chip.

Background

Today, the storage devices are increasingly used, and the storage technology of the storage devices is continuously advancing. Taking the current widely used memory of TLC/QLC as an example, TLC can store three bits of data information in one data storage unit, and QLC can store four bits of information data in one data storage unit. In order to distinguish various data information in one data storage unit, it is necessary to divide the corresponding threshold voltage section to distinguish it. TLC requires eight threshold voltage intervals to be divided, while QLC requires sixteen threshold voltage intervals to be divided. However, since the threshold voltage intervals inside the data storage unit are limited, the more the threshold voltage intervals are divided, the smaller the interval intervals are, and the small interval intervals mean that when the threshold voltage of the data storage unit shifts left and right due to various factors, the data storage unit passes through the threshold voltage value thereof, and data errors occur when reading is performed according to the threshold voltage value of the original interval, so that the reliability of the stored data is reduced.

Disclosure of Invention

The application mainly aims to provide a flash memory chip which can solve the technical problem of low data storage reliability of the flash memory chip.

In order to solve the technical problems, the first technical scheme adopted by the application is as follows: the flash memory storage chip comprises a storage module, wherein the storage module comprises a data storage unit and a page buffer; the conversion module comprises a storage control unit and a data receiving unit, and is connected with the storage module to control the data access of the storage module; the data receiving unit is used for receiving the instruction and the stored data information, and the storage control unit is used for writing data into the first cache area and the second cache area of the page buffer based on the instruction; generating data in a third buffer area of the page buffer; the data generated by the third buffer area is obtained by carrying out logic operation on the data of the first buffer area and the data of the second buffer area, and the data of the first buffer area, the second buffer area and the third buffer area determine first data information; and writing the first data information cached by the page buffer into the data storage unit.

The beneficial effects of the application are as follows: on the basis of determining the data of the first and second buffer areas, the data of the third buffer area is not determined by input, but the data of the third buffer area is obtained by carrying out logic operation on the data of the first and second buffer areas, and because the buffer data has 0 or 1, each buffer area stores the buffer data of one bit data information, eight data information can be obtained by determining the data of the first, second and third buffer areas by using the critical voltage value in the prior art. Because the occurrence of data information is reduced, on the basis of the same maximum voltage interval, a larger threshold voltage interval can be divided for four data information, the fault tolerance degree of the data information on the threshold voltage offset of the memory cell is increased, and the reliability of the stored data is improved. The logic operation can be realized by means of the logic operation capability inside the memory chip, and the computing resource of an external CPU is not required to be occupied, so that the computing power of the system can be saved, and the operation of completing the memory mode conversion from the memory chip can be realized.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a schematic diagram of post-write threshold voltages of TLC NAND FLASH memories;

FIG. 2 is a schematic diagram of the voltages stored in the TLC data storage unit shifted left and right;

FIG. 3 is a schematic diagram of a first embodiment of a flash memory chip according to the present application;

FIG. 4 is a flow chart of a first embodiment of a control flow of a memory control unit in the data flash memory chip of the present application;

FIG. 5 is a flow chart of a second embodiment of a control flow of a memory control unit in the data flash memory chip of the present application;

FIG. 6 is a schematic diagram of a logic operation according to the present application;

FIG. 7 is a further schematic diagram of the logic operation of the present application;

FIG. 8 is a flow chart of a third embodiment of a control flow of a memory control unit in the data flash memory chip of the present application;

FIG. 9 is a further schematic diagram of the logic operation of the present application;

FIG. 10 is a flow chart of a fourth embodiment of a control flow of a memory control unit in the data flash memory chip of the present application;

FIG. 11 is a flowchart of a fifth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application;

FIG. 12 is a flowchart of a sixth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application;

FIG. 13 is a schematic diagram of the read voltage interval after determining a logic operation according to the present application;

FIG. 14 is a schematic diagram of a read voltage interval after a logic operation is determined according to the present application;

FIG. 15 is a flowchart of a seventh embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application;

FIG. 16 is a flowchart of an eighth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application;

FIG. 17 is a flow chart of a ninth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application;

FIG. 18 is a flowchart of a tenth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application;

FIG. 19 is a flowchart of an eleventh embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application;

FIG. 20 is a flowchart of a twelfth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application;

FIG. 21 is a flowchart of a thirteenth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application;

FIG. 22 is a flowchart of a fourteenth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application;

FIG. 23 is a flowchart showing a control flow of a memory control unit in a data flash memory chip according to a fifteenth embodiment of the present application.

Detailed Description

The following description of the embodiments of the present application will be made clearly and fully with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.

The terms "first," "second," and the like in this disclosure are used for distinguishing between different objects and not for describing a particular sequential order. Furthermore, the terms "comprise" and "have," as well as any variations thereof, are intended to cover a non-exclusive inclusion. For example, a process, method, system, article, or apparatus that comprises a list of steps or elements is not limited to only those listed steps or elements but may include other steps or elements not listed or inherent to such process, method, article, or apparatus.

Reference herein to "an embodiment" means that a particular feature, structure, or characteristic described in connection with the embodiment may be included in at least one embodiment of the application. The appearances of such phrases in various places in the specification are not necessarily all referring to the same embodiment, nor are separate or alternative embodiments mutually exclusive of other embodiments. Those of skill in the art will explicitly and implicitly appreciate that the embodiments described herein may be combined with other embodiments.

In order to improve the reliability of data storage of a flash memory chip, it is necessary to reduce the number of bits of data information that can be stored in one data storage unit, thereby increasing the threshold voltage interval of data storage and reducing the influence of read data after voltage offset.

Referring to fig. 1, fig. 1 is a schematic diagram of threshold voltages after writing of TLC NAND FLASH memories.

Currently, in practical applications, TLC NAND FLASH memories and QLC NAND FLASH memories are used more. One data storage unit of TLC in the two kinds of memories can store 3 bits of information, one data storage unit of QLC can store 4 bits of information, and one data storage unit of MLC can only store 2 bits of information, so that compared with MLC, the production cost of the two is lower. However, the maximum voltage intervals of the data storage units are all the same, and storing more information in the same maximum voltage interval means that the voltage interval is divided into more cells, so that the stored voltages are identified according to the interval threshold value to read data. For TLC, as shown in the figure, one data storage unit can store 3 bits of information, then 8 voltage states are required, 8 intervals are required, and different READ LEVEL are used to distinguish them.

The TLC stores information with 3 bits. When storing, the data of each bit is stored in different page buffers, after the data of all bits are stored in the buffer, the data are written into the memory cell together, and finally the distribution of the threshold voltage written into the flash page is shown in fig. 1.

The distribution of the voltages of each state may shift left and right and broaden due to the influence of various interference factors after data writing, so that READ LEVEL cannot distinguish the 8 voltage states well during reading. As shown in fig. 2, fig. 2 is a schematic diagram of a shift of threshold voltage in TLC data memory cells. If a certain number of erroneous bits is exceeded, the data will fail to read, resulting in a loss of data. If the fewer the stored voltage states, the more separated the states, the easier it is to distinguish between the states when reading according to READ LEVEL, the less likely it is for data to be erroneous, and the more reliable it is for data storage.

In some application scenarios, the reliability requirement on the data is very high, but the requirement on the storage capacity is not so strict, and the reliability of the TLC/QLC does not meet the actual requirement of the user, so the application proposes the following embodiments to improve the data reliability of the TLC/QLC product to meet the use requirement.

Referring to fig. 3, fig. 3 is a schematic structural diagram of a first embodiment of a flash memory chip according to the present application.

The flash memory chip includes a memory module 10 and a conversion module 20. The conversion module 20 is connected to the memory module 10 to control data access of the memory module 10.

The memory module 10 includes a data storage unit 11 and a page buffer 12. The conversion module 20 includes a storage control unit 21 and a data receiving unit 22.

The data receiving unit 22 is used for receiving instructions and stored data information. The data receiving unit 22 is connected to the storage control unit 21. The memory control unit 21 writes data in the first buffer area and the second buffer area of the page buffer 12 based on the instruction, and generates data in the third buffer area of the page buffer 12 by utilizing the logical operation capability of the page buffer. The data generated by the third buffer area is obtained by carrying out logic operation on the data of the first buffer area and the data of the second buffer area. The data of the first buffer area, the second buffer area and the third buffer area jointly determine first data information. The storage control unit 21 writes the first data information obtained by the page buffer 12 to the data storage unit 11.

The instruction received by the data receiving unit 22 may be a storage mode conversion instruction of the flash memory chip, so that the storage control unit 21 controls the storage unit based on the instruction.

Referring to fig. 4, fig. 4 is a flowchart illustrating a control flow of a memory control unit in a data flash memory chip according to a first embodiment of the present application. Which comprises the following steps:

S11: and writing data in the first buffer area and the second buffer area of the page buffer.

The data of the first buffer area and the second buffer area are data input by an external user.

S12: data is generated in a third buffer area of the page buffer.

In the prior art, the data of the third buffer is also input by an external user. However, in the present invention, in order to ensure the reliability of data storage, the user only stores the user data of the first buffer area and the second buffer area in the storage unit, and does not provide the data of the third buffer area. The data of the third buffer area is generated by a storage control unit according to certain logic operation according to the data of the first buffer area and the second buffer area in the storage chip.

In the memory chip, the above logical operation process is implemented by the instruction information by the conversion module using logical operation functions in the page buffer, such as or operation, and operation, nor operation, nand operation, nor operation, exclusive or operation, and the like. The first data information is further determined from the data of the first buffer, the second buffer and the third buffer. The first data information is determined by the data written in the corresponding first buffer area, second buffer area and third buffer area under the same voltage interval.

S13: and writing the first data information cached by the page buffer into the data storage unit.

After the data writing in the page buffer is completed, the finally obtained first data information is written in the data storage unit to complete the data storage.

The logic operation in the embodiment can respond to the writing instruction by means of the storage control unit in the storage chip, and the logic operation is completed in the buffer area in the storage unit by utilizing the logic operation function of the buffer area, so that the computing resource of an external CPU is not occupied, the computing power of the system can be saved, and the operation of completing the storage mode conversion from the storage chip can be realized.

In this embodiment, based on determining the data of the first and second buffer areas, the data of the third buffer area is obtained by performing a logic operation on the data of the first and second buffer areas, and since there are 0 or 1 types of buffer data, each buffer area stores buffer data of one bit data information, eight types of data information can be obtained by determining the data of the first, second and third buffer areas according to the prior art. Because the occurrence of data information is reduced, on the basis of the same maximum voltage interval, a larger threshold voltage interval can be divided for four data information, the fault tolerance degree of the data information on the threshold voltage offset of the memory cell is increased, and the reliability of the stored data is improved.

Referring to fig. 5, fig. 5 is a flowchart illustrating a control flow of a memory control unit in a data flash memory chip according to a second embodiment of the present application. Which comprises the following steps:

s21: and carrying out first logic operation on the data of the first buffer area and the data of the second buffer area to obtain intermediate data.

According to the data written into the first buffer area and the second buffer area, first logic operation is carried out. The logical operation may be an exclusive nor operation.

S22: writing the intermediate data and the data of the first buffer area into a third buffer area by performing data obtained by the second logic operation; or writing the intermediate data and the data of the second buffer area into the third buffer area by the data obtained by performing the second logic operation.

And carrying out a second logic operation on the obtained intermediate data and the data of the first buffer area to obtain the data written into the third buffer area. The logical operation may be an or operation. The second logic operation may be performed on the obtained intermediate data and the data in the second buffer area, and the obtained data may be written into the third buffer area.

In one embodiment, referring to fig. 6, fig. 6 is a schematic diagram of the logic operation of the present application. If the data written into the first buffer LP (lower page) is 10000111 and the data written into the second buffer MP (middle page) is 11001100, then the data is subjected to an exclusive nor operation to obtain 10110100, and then the data is subjected to an exclusive nor operation with the data in the first buffer to obtain the data 10110111 in the third buffer UP (upper page). The stored threshold voltages are changed from the original maximum eight states to the final four states, 111, 001, 010, 101, respectively, of the original eight states. The resulting four voltage states have voltage intervals that are far apart, so that a new data read voltage can be set for them. The new read voltage distinguishes four voltage states, so that interval intervals of the new four voltage intervals are increased compared with the interval intervals of the new four voltage intervals, and therefore tolerance of the new four voltage intervals to left and right offset of the voltage is higher, reliability of data is enhanced, and probability of data errors is lower.

In this embodiment, the first buffer stores low-bit data, the second buffer stores middle-bit data, and the third buffer ultimately stores highest-bit data.

Similarly, referring to fig. 7, fig. 7 is a schematic diagram of a logic operation according to the present application. If the intermediate data and the data in the second buffer area are subjected to OR operation, the obtained data in the third buffer area is 11111100. The data voltages stored therein are finally in four states, 111, 011, 001, 100, respectively, of the original eight. The voltage interval of 001 is far away from the other three voltage intervals, and the other three intervals are still near, so after the new data reading voltage is set, the interval of the new voltage interval corresponding to 001 is increased, the tolerance to the left-right offset of the voltage is higher, the reliability of the data is enhanced, the probability of data error is lower, the interval intervals of the other three voltage intervals may not be greatly different, and the data reliability does not greatly float.

Therefore, for the operation process of performing the logic operation, it is required to consider that the original voltage intervals of the four finally obtained voltage states are relatively uniformly distributed in the whole maximum voltage interval, so that the interval intervals of the four new voltage states can be increased to a certain extent, rather than only the individual intervals thereof can be obviously increased, and thus the reliability of all the stored data can be improved, rather than the individual data thereof.

Referring to fig. 8, fig. 8 is a flowchart illustrating a control flow of a memory control unit in a data flash memory chip according to a third embodiment of the present application. Which comprises the following steps:

S31: and acquiring the data of the first cache region and the data of the second cache region.

S32: and writing the data obtained by performing a third logic operation on the data of the first buffer area and the data of the second buffer area into a third buffer area.

And acquiring data of the first buffer area and the second buffer area, directly performing a third logic operation on the data, and writing the acquired data into the third buffer area. The third logical operation may be an exclusive nor operation.

In an embodiment, the data written into the first buffer is 10000111, and the data written into the second buffer is 11100001, and then the data is subjected to an exclusive nor operation to obtain 10011001 as the data of the third buffer. The data voltages stored therein are finally in four states, 111, 001, 010, 101, respectively, among the original eight states. The resulting four voltage states have voltage intervals that are far apart, so that a new data read voltage can be set for them. The new read voltage distinguishes four voltage states, so that interval intervals of the new four voltage intervals are increased compared with the interval intervals of the new four voltage intervals, and therefore tolerance of the new four voltage intervals to left and right offset of the voltage is higher, reliability of data is enhanced, and probability of data errors is lower.

Referring to fig. 9, fig. 9 is a schematic diagram illustrating a logic operation process according to the present application.

Taking fig. 9 as an example, the first buffer data is written LP (lower page), the second buffer data is written UP (upper page), and the generation of the third buffer data is realized by utilizing the logic operation capability inside the memory chip. The data of the third buffer MP (middle page) is generated by (LP) XNOR (UP). After MP data are generated, the data of the MP data are written into the storage unit, so that four states in the original eight states can be eliminated, only four states are reserved, MLC storage is realized, and the reliability of the data is improved.

In this embodiment, the first buffer stores low-bit data, the second buffer stores high-bit data, and the third buffer stores intermediate-bit data.

Referring to fig. 10, fig. 10 is a flowchart illustrating a control flow of a memory control unit in a data flash memory chip according to a fourth embodiment of the present application. Which comprises the following steps:

s41: after the first buffer area writes data, the data of the first buffer area is copied to the third buffer area.

In the TLC page buffer, there is a three-layer page buffer structure, and each page buffer is correspondingly used for buffering one bit of data. In the process of performing the logic operation, when the bit data of the lowest bit is stored in the first buffer corresponding to lower page buffer, the data of the first buffer is copied and written into the third buffer.

S42: after the second buffer area writes data, the data of the third buffer area and the data of the second buffer area are subjected to first logic operation to obtain intermediate data, and the intermediate data is written into the third buffer area.

And when the second buffer area stores the bit data of the second bit, carrying out logic operation on the data of the first buffer area stored in the third buffer area and the data of the second buffer area at the moment. The logical operation may be an exclusive nor operation. And obtaining intermediate data after operation, and updating the data of the first buffer area written in the third buffer area by using the intermediate data.

S43: and writing the data obtained by performing the second logic operation on the data of the third buffer area and the data of the first buffer area into the third buffer area.

After the intermediate data is written into the third buffer area, the intermediate data and the buffer data in the first buffer area are subjected to logic operation again. The logical operation may be an or operation. The obtained data is the final data written into the third buffer area, and the updated intermediate data is written into the third buffer area.

After the data are written into the buffer, they are written together into the data storage unit.

This embodiment is a further extension of the second embodiment of the control flow of the storage unit, which exemplifies a specific flow how to operate on the cache data.

The logic operation is realized by the logic operation function of the buffer area by the storage control unit in the storage chip in response to the writing instruction, and the buffer area inside the storage unit does not occupy the computing resource of an external CPU, so that the computing power of the system can be saved, and the operation of completing the storage mode conversion from the storage chip can be realized.

For the third embodiment of the control flow of the memory unit of the present application, after writing data in the first buffer area and the second buffer area, the data in the third buffer area is obtained by performing a logic operation using the data in the first buffer area and the second buffer area, and then the data is written in the third buffer area.

Referring to fig. 11, fig. 11 is a flowchart illustrating a control flow of a memory control unit in a data flash memory chip according to a fifth embodiment of the present application. Which comprises the following steps:

s51: and determining a corresponding interval voltage signal according to the first data information cached by the page buffer.

After the data of the first buffer area and the second buffer area are subjected to logic operation to obtain the data of the third buffer area, four voltage state data, namely the data information stored in the buffer at present, can be obtained correspondingly.

In the above embodiment, the data in the first buffer area and the data in the second buffer area are subjected to exclusive nor operation to obtain intermediate data, and then the intermediate data and the data in the first buffer area are subjected to exclusive nor operation to obtain the data in the third buffer area, so that the obtained four voltage state data are 111, 100, 010 and 101. As shown in fig. 1, the voltage sections corresponding to the four kinds of voltage state data are a first section, a third section, a fifth section, and an eighth section from left to right.

S52: and writing the first data information into the data storage unit according to the corresponding interval voltage signal.

After the cached data information is determined, the interval voltage signal corresponding to the data information can be obtained, and the data is written into the data storage unit according to the corresponding voltage interval signal. When the data 111, 100, 010 and 101 are written, the voltage information corresponding to the first, third, fifth and eighth sections is written into the memory cell.

Referring to fig. 12, fig. 12 is a flowchart illustrating a sixth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application. Which comprises the following steps:

S61: 8 voltage intervals corresponding to the 3-bit data are determined.

In the memory mode of TLC, one data storage unit is capable of storing 3 bits corresponding to eight status data, which each occupy a voltage interval to be distinguished according to the threshold voltage of the voltage interval during reading. The 8 voltage intervals are determined by 7 threshold voltage values. In the above embodiment, the 7 threshold voltages are READ LEVEL1-7.

S62: 4 voltage intervals determined by the first buffer, the second buffer and the third buffer are determined.

Referring to fig. 13, fig. 13 is a schematic diagram of a read voltage interval after logic operation determination according to the present application. After the logic operation, only four of the eight state data are retained. For example, after the logic operation of the second embodiment, only 111, 100, 010, 101 are reserved, which corresponds to the first, third, fifth, and eighth voltage intervals. In order to increase the reliability of the data, a new read voltage needs to be determined for it, and a new voltage interval needs to be divided for it to distinguish the remaining four voltage states. The 4 voltage intervals are determined by 3 threshold voltage values.

By employing one of the 7 threshold voltage values and the corresponding offset, 3 threshold voltage values are respectively represented. After determining the voltage intervals corresponding to the four reserved state data, the respective critical voltages of the four reserved state data are determined correspondingly. In the above embodiment, the first, third, fifth and eighth voltage intervals correspond to READ LEVEL, 2,3,4,5 and 7 threshold voltages. In order to effectively improve the reliability of each state data, the new critical voltage of 111, 100 is determined as the middle voltage of the first third voltage interval, that is, the middle voltage of READ LEVEL1, 2, which is obtained by adding half of the difference between READ LEVEL1 and 2 on the basis of READ LEVEL1 or subtracting half of the difference between READ LEVEL1 and 2 on the basis of READ LEVEL 2. Similarly, the new threshold voltages of 100 and 010 are determined to be the middle voltage of the third and fifth voltage sections, that is, the middle voltages READ LEVEL and 4, and the offset value is increased on the basis of READ LEVEL or decreased on the basis of READ LEVEL 4. The new threshold voltages of 010 and 101 are determined to be the middle of the fifth eighth voltage interval, that is, the middle voltages of READ LEVEL and 7, and the offset value is increased on the basis of READ LEVEL or decreased on the basis of READ LEVEL. The new threshold voltage is not necessarily the middle between the two basic threshold voltages, and can be adjusted according to the actual situation. Simply determining the new threshold voltage at the very middle of the two base voltages can maximize the reliability of each data.

Fig. 14 is a schematic diagram of a read voltage interval after logic operation determination according to the present application. After the logic operation of the third embodiment, 111, 100, 010, and 001 are reserved, which correspond to the first, third, fifth, and seventh voltage intervals. In order to increase the reliability of the data, a new read voltage needs to be determined for it, and a new voltage interval needs to be divided for it to distinguish the remaining four voltage states. The 4 voltage intervals are determined by 3 threshold voltage values.

By employing one of the 7 threshold voltage values and the corresponding offset, 3 threshold voltage values are respectively represented. After determining the voltage intervals corresponding to the four reserved state data, the respective critical voltages of the four reserved state data are determined correspondingly. In the above embodiment, the first, third, fifth and seventh voltage intervals correspond to READ LEVEL, 2,3,4,5 and 6 threshold voltages. In order to effectively improve the reliability of each state data, the new critical voltage of 111, 100 is determined as the middle voltage of the first third voltage interval, that is, the middle voltage of READ LEVEL1, 2, which is obtained by adding half of the difference between READ LEVEL1 and 2 on the basis of READ LEVEL1 or subtracting half of the difference between READ LEVEL1 and 2 on the basis of READ LEVEL 2. Similarly, the new threshold voltages of 100 and 010 are determined to be the middle voltage of the third and fifth voltage sections, that is, the middle voltages READ LEVEL and 4, and the offset value is increased on the basis of READ LEVEL or decreased on the basis of READ LEVEL 4. The new threshold voltages of 010 and 001 are determined to be the middle voltage of the fifth eighth voltage interval, that is, the middle voltages of READ LEVEL and 6, and the offset value is increased on the basis of READ LEVEL or decreased on the basis of READ LEVEL. The new threshold voltage is not necessarily the middle between the two basic threshold voltages, and can be adjusted according to the actual situation. Simply determining the new threshold voltage at the very middle of the two base voltages can maximize the reliability of each data.

Referring to fig. 15, fig. 15 is a flowchart of a seventh embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application. Which comprises the following steps:

S71: the voltage information in the data storage unit is compared with 4 voltage intervals to read the first data information stored in the data storage unit.

After the data in the buffer area is stored in the data storage unit, when the data is read, the new threshold voltage value determined according to the above embodiment is read.

Referring to fig. 16, fig. 16 is a flowchart illustrating an eighth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application. Which comprises the following steps:

s81: data is generated in a fourth buffer area of the page buffer.

The data generated by the fourth buffer area is obtained by carrying out logic operation on any two of the data of the first buffer area, the data of the second buffer area and the data of the third buffer area, and the data of the first buffer area, the second buffer area, the third buffer area and the fourth buffer area determine second data information. On the basis of the above embodiment, after writing the data of the first buffer area and the second buffer area, the data of the third buffer area is obtained by performing a logic operation on the data of the first buffer area and the second buffer area. Still further, the data of the fourth buffer area is obtained by performing logic operation again on the data of any two of the first buffer area, the second buffer area and the third buffer area.

Among the data storage units of the QLC, each data storage unit may store 4 bits of data information. It has sixteen voltage intervals corresponding to sixteen medium voltage states, distinguished by fifteen threshold voltage values. The page buffer has a four-layer structure, and each page buffer corresponds to one bit of data. Writing is performed sequentially from the bit of the lowest order during writing.

The process of performing the logic operation to obtain the data of the third buffer area can refer to the description of the above embodiment, for example, after writing the data of the first buffer area, copying the data of the first buffer area into the third buffer area, and after writing the data of the second buffer area, performing the logic operation on the data of the third buffer area and the data of the second buffer area. The operation may be an exclusive nor operation. And obtaining intermediate data after operation, and updating the data of the first buffer area written in the third buffer area by using the intermediate data. After the intermediate data is written into the third buffer area, the intermediate data and the buffer data in the first buffer area are subjected to logic operation again. The logical operation may be an or operation. The obtained data is the final data written into the third buffer area, and the updated intermediate data is written into the third buffer area.

After the process of obtaining the fourth buffer area through logic operation, four voltage state data are correspondingly reserved, and the four voltage state data correspond to four of sixteen original voltage data. In order to enhance the reliability of the four voltage state data, a larger new voltage interval needs to be determined for the four voltage states. In order to improve the reliability of all the four voltage states to a certain extent, not just the individual data, it is necessary to make the voltage intervals corresponding to the four voltage state data originally obtained in the end more uniformly distributed in the whole maximum voltage interval, so that the new voltage interval can be obviously increased compared with the previous voltage interval. The specific operation logic may refer to the ideas provided in the above embodiments, and will not be described herein.

The logic operation is realized by the logic operation function of the buffer area by the storage control unit in the storage chip in response to the writing instruction, and the buffer area inside the storage unit does not occupy the computing resource of an external CPU, so that the computing power of the system can be saved, and the operation of completing the storage mode conversion from the storage chip can be realized.

In the practical application process, the first buffer area, the second buffer area, the third buffer area and the fourth buffer area can be any one of all the set buffer areas. The first, second, third and fourth buffer areas are not limited in position, and only indicate that the positions of the buffer areas are different.

S82: and writing the second data information cached by the page buffer into the data storage unit.

And after the data writing in the buffer is completed, writing the cached second data information into the data storage unit. The second data information is determined by the data written in the corresponding first buffer area, the second buffer area, the third buffer area and the fourth buffer area under the same voltage interval. And writing the data into the data storage unit to finish the storage of the data.

Referring to fig. 17, fig. 17 is a flowchart of a ninth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application. Which comprises the following steps:

S91: and determining a corresponding interval voltage signal according to the second data information cached by the page buffer.

After the data of the first buffer area and the second buffer area are subjected to logic operation to obtain the data of the third buffer area, and logic operation is performed again to obtain the data of the fourth buffer area, four voltage state data can be obtained correspondingly, and the four voltage state data are the data information currently stored in the buffer.

After determining the four voltage state data, the original voltage interval and the threshold voltage value of the voltage interval can be further determined. The determining step may refer to the above embodiment, and will not be described herein.

S92: and writing the second data information into the data storage unit according to the corresponding interval voltage signal.

And determining a voltage interval and a critical voltage value according to the determined cache data. Writing data into the data storage unit based on the section voltage. The voltage written into the data storage unit by the corresponding data information is in the corresponding voltage interval. Reference should be made specifically to the above embodiments, and details are not repeated here.

Referring to fig. 18, fig. 18 is a flowchart illustrating a control flow of a memory control unit in a data flash memory chip according to a tenth embodiment of the present application. Which comprises the following steps:

S101: 16 voltage intervals corresponding to 4-bit data are determined.

In the storage mode of QLC, one data storage unit is capable of storing 4 bits corresponding to sixteen state data, each occupying a voltage section so as to be distinguished according to adjacent voltages of the voltage section when read. The 16 voltage intervals are determined by 15 threshold voltage values. 15 critical voltage values are READ LEVEL1-15.

S102: and determining 4 voltage intervals determined by the first buffer area, the second buffer area, the third buffer area and the fourth buffer area.

After the logic operation, sixteen state data will only retain four of them. For example, it is assumed that the voltage sections corresponding to the four kinds of voltage state data that remain after the logical operation are the first section, the fifth section, the tenth section, and the sixteenth section. In order to increase the reliability of the data, a new read voltage needs to be determined for it, and a new voltage interval needs to be divided for it to distinguish the remaining four voltage states. The 4 voltage intervals are determined by 3 threshold voltage values.

By employing one of the 15 threshold voltage values and the corresponding offset, 3 threshold voltage values are respectively represented. After determining the voltage intervals corresponding to the four reserved state data, the respective critical voltages of the four reserved state data are determined correspondingly. It is assumed that the first, fifth, tenth, and sixteenth voltage intervals are reserved, and the first, fifth, tenth, and sixteenth voltage intervals correspond to READ LEVEL, 4,5, 9, 10, and 15 threshold voltages. In order to effectively improve the reliability of each state data, the first new threshold voltage is determined as the middle voltage between the first voltage interval and the fifth voltage interval, that is, the middle voltage of READ LEVEL, 4, which is obtained by adding half of the difference between READ LEVEL1 and 4 on the basis of READ LEVEL1 or subtracting half of the difference between READ LEVEL and 4 on the basis of READ LEVEL. Similarly, determining the second new threshold voltage as the middle of the fifth and tenth voltage intervals, i.e., the middle voltages READ LEVEL, 9, may be achieved by increasing the offset value on the basis of READ LEVEL or decreasing the offset value on the basis of READ LEVEL 9. The third new threshold voltage is determined to be the middle between the tenth and sixteenth voltage intervals, i.e., the middle voltages of READ LEVEL, 15, and is obtained by increasing the offset value on the basis of READ LEVEL or decreasing the offset value on the basis of READ LEVEL. The new threshold voltage is not necessarily the middle between the two basic threshold voltages, and can be adjusted according to the actual situation. Simply determining the new threshold voltage at the very middle of the two base voltages can maximize the reliability of each data.

Referring to fig. 19, fig. 19 is a flowchart of an eleventh embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application. Which comprises the following steps:

S111: the voltage information in the data storage unit is voltage-compared with 4 voltage intervals to read the second data information stored in the data storage unit.

After the data in the buffer area is stored in the data storage unit, the data is read according to the determined new critical voltage value when the data is read.

Based on the above embodiments, it is conceivable that, in the data storage unit of the QLC, writing of data in the first buffer area, the second buffer area, and the third buffer area is performed according to the original threshold voltage value, and then eight voltage state data are obtained through logic operation, so that the eight voltage state data are uniformly distributed in the whole voltage section. Further, according to the original voltage intervals and the threshold voltage values corresponding to the eight voltage state data, new eight voltage intervals and corresponding seven threshold voltage values are determined. The new seven threshold voltage values may be obtained on the basis of the threshold voltage values corresponding to the eight voltage state data. After the data information stored in the buffer memory is stored in the data storage unit, the data storage unit is read through the new seven critical voltage values. The method of such an embodiment is also within the scope of the present application.

Referring to fig. 20, fig. 20 is a flowchart illustrating a control flow of a memory control unit in a data flash memory chip according to a twelfth embodiment of the present application. Which comprises the following steps:

s121: and writing data in the first buffer area, the second buffer area and the third buffer area of the page buffer.

In a data storage unit of the QLC, data of the first buffer area, the second buffer area and the third buffer area are written according to the original storage writing flow, and the data of the first buffer area, the second buffer area and the third buffer area are determined by external input.

S122: and generating data in the fourth buffer area.

The data generated by the fourth buffer area is obtained by logic operation of any two of the data of the first buffer area, the data of the second buffer area and the data of the third buffer area by using the computing resources of the page buffer. The data of the first buffer area, the second buffer area, the third buffer area and the fourth buffer area determine third data information.

S123: and writing the third data information stored in the page buffer into the data storage unit.

After the data writing in the buffer is completed, the finally obtained data is written in the data storage unit to complete the data storage.

In the practical application process, the first buffer area, the second buffer area, the third buffer area and the fourth buffer area can be any one of all the set buffer areas. The first, second, third and fourth buffer areas are not limited in position, and only indicate that the positions of the buffer areas are different.

Referring to fig. 21, fig. 21 is a flowchart of a thirteenth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application. Which comprises the following steps:

S131: and determining a corresponding interval voltage signal according to the third data information cached by the page buffer.

After the data of the first buffer area, the second buffer area and the third buffer area are written, the data of the fourth buffer area is obtained through logic operation by using the computing resources of the page buffer, so that eight kinds of voltage state data can be finally obtained, and the eight kinds of voltage state data are data information which can be stored by the current buffer.

After eight kinds of voltage state data are determined, the original voltage interval and the critical voltage value of the voltage interval can be further determined. The determining step may refer to the above embodiment, and will not be described herein.

S132: and writing the third data information into the data storage unit according to the corresponding interval voltage signal.

And determining a voltage interval and a critical voltage value according to the determined cache data. Writing data into the data storage unit based on the section voltage. The voltage written into the data storage unit by the corresponding data information is in the corresponding voltage interval. Reference may be made to the above embodiments, and no further description is given here.

Referring to fig. 22, fig. 22 is a flowchart of a control flow of a memory control unit in a data flash memory chip according to a fourteenth embodiment of the present application. Which comprises the following steps:

s141: 16 voltage intervals corresponding to 4-bit data are determined.

In the storage mode of QLC, one data storage unit is capable of storing 4 bits corresponding to sixteen state data, each occupying a voltage section so as to be distinguished according to adjacent voltages of the voltage section when read. The 16 voltage intervals are determined by 15 threshold voltage values. 15 critical voltage values are READ LEVEL1-15.

S142: 8 voltage intervals determined by the first buffer, the second buffer, the third buffer and the fourth buffer are determined.

Sixteen state data will only remain eight of them after the logic operation. For example, it is assumed that the voltage sections corresponding to the eight kinds of voltage state data that remain after the logical operation are the first section, the third section, the fifth section, the seventh section, the ninth section, the eleventh section, the thirteenth section, and the sixteenth section. In order to increase the reliability of the data, a new read voltage needs to be determined for it, and a new voltage interval needs to be divided for it to distinguish the eight voltage states that remain. The 8 voltage intervals are determined by 7 threshold voltage values.

By employing one of the 15 threshold voltage values and the corresponding offset, 7 threshold voltage values are represented, respectively. After determining the voltage intervals corresponding to the eight reserved state data, the respective critical voltages of the eight reserved state data are determined accordingly. Assuming that the first interval, the third interval and the fifth interval exist in the reserved intervals, and the critical voltage corresponding to the third interval is READ LEVEL, 3, the first interval corresponds to READ LEVEL, the fifth interval corresponds to READ LEVEL, 5, the first new critical voltage is the middle voltage between the first interval and the third interval, which can be READ LEVEL, 2, and is obtained by increasing the difference between READ LEVEL1 and 2 by half on the basis of READ LEVEL1, or subtracting the difference between READ LEVEL1 and 2 by half on the basis of READ LEVEL. Other new threshold voltages are determined with reference to the above description. The new threshold voltage is not necessarily the middle between the two basic threshold voltages, and can be adjusted according to the actual situation. Simply determining the new threshold voltage at the very middle of the two base voltages can maximize the reliability of each data.

Referring to fig. 23, fig. 23 is a flowchart of a fifteenth embodiment of a control flow of a memory control unit in a data flash memory chip according to the present application. Which comprises the following steps:

s151: the voltage information in the data storage unit is compared with 8 voltage intervals to read the third data information stored in the data storage unit.

After the data in the buffer area is stored in the data storage unit, the data is read according to the determined 8 new critical voltage values when the data is read.

Further, on the basis of the above embodiment, for a memory chip capable of storing a plurality of bit information in one data storage unit, the bit information stored in one data storage unit is reduced by the above logic operation in the page buffer, but the technical solution of increasing the data reliability is in the protection scope of the present application.

The flash memory chip in the above embodiment may be a TLC/QLC NAND FLASH memory.

In summary, on the basis of determining the first and second buffer area data, the third buffer area data is not directly determined by input, but the data of the third buffer area is obtained by performing logic operation on the data of the first and second buffer areas, and because the buffer data has 0 or 1, each buffer area stores buffer data of one bit data information, eight data information can be obtained by determining the first, second and third buffer area data by using the critical voltage value in the prior art. Because the occurrence of data information is reduced, on the basis of the same maximum voltage interval, a larger threshold voltage interval can be divided for four data information, the fault tolerance degree of the data information on the threshold voltage offset of the memory cell is increased, and the reliability of the stored data is improved. The logic operation is realized by the logic operation function of the buffer area by means of the response of the storage control unit in the storage chip to the writing instruction, the calculation resource of an external CPU is not occupied, the calculation force of the system can be saved, and the operation of completing the storage mode conversion from the storage chip can be realized.

In the several embodiments provided in the present application, it should be understood that the disclosed method and apparatus may be implemented in other manners. For example, the above-described device embodiments are merely illustrative, e.g., the division of the modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted, or not performed.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units of the other embodiments described above may be stored in a computer readable storage medium if implemented in the form of software functional units and sold or used as stand alone products. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the method according to the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

The foregoing description is only illustrative of the present application and is not intended to limit the scope of the application, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present application.

Claims (17)

1. A flash memory chip, the flash memory chip comprising:

The storage module comprises a data storage unit and a page buffer;

The conversion module comprises a storage control unit and a data receiving unit, and is connected with the storage module to control data access of the storage module;

the data receiving unit is used for receiving an instruction and stored data information, and the storage control unit is used for writing data in a first cache area and a second cache area of the page buffer based on the instruction; generating data in a third buffer area of the page buffer; the data generated by the third buffer area is obtained by carrying out logic operation on the data of the first buffer area and the data of the second buffer area, and the data of the first buffer area, the data of the second buffer area and the data of the third buffer area determine first data information; and writing the first data information cached by the page buffer into the data storage unit.

2. The flash memory chip of claim 1, wherein,

The storage control unit performs first logic operation on the data of the first cache region and the data of the second cache region to obtain intermediate data;

Writing the intermediate data and the data of the first buffer area into the third buffer area by performing second logic operation to obtain data; or (b)

And writing the data obtained by performing a second logic operation on the intermediate data and the data of the second buffer area into the third buffer area.

3. The flash memory chip of claim 2, wherein,

The first logical operation is an exclusive-nor logical operation, and the second logical operation is an exclusive-nor logical operation.

4. The flash memory chip of claim 1, wherein,

And the storage control unit writes the data obtained by performing a third logic operation on the data of the first cache region and the data of the second cache region into the third cache region.

5. The flash memory chip of claim 4, wherein,

The third logical operation is an exclusive nor logical operation.

6. The flash memory chip of claim 1, wherein,

The storage control unit is used for determining a corresponding interval voltage signal according to the first data information cached by the page buffer;

And writing the first data information into the data storage unit according to the corresponding interval voltage signal.

7. The flash memory chip of claim 6, wherein the memory chip further comprises a memory chip,

The storage control unit determines 8 voltage intervals corresponding to the 3-bit data, wherein the 8 voltage intervals are determined by 7 critical voltage values; and

Determining 4 voltage intervals determined by the first buffer area, the second buffer area and the third buffer area, wherein the 4 voltage intervals are determined by 3 critical voltage values;

Wherein, one of the 7 critical voltage values and the corresponding offset are adopted to respectively represent the 3 critical voltage values.

8. The flash memory chip of claim 7, wherein,

The storage control unit compares the voltage information in the data storage unit with the 4 voltage sections to read the first data information stored in the data storage unit.

9. The flash memory chip of claim 1, wherein,

The storage control unit is used for generating data in a fourth buffer area of the page buffer; the data generated by the fourth buffer area is obtained by performing logic operation on any two of the data of the first buffer area, the data of the second buffer area and the data of the third buffer area, and the data of the first buffer area, the second buffer area, the third buffer area and the fourth buffer area determine second data information;

And writing the second data information cached by the page buffer into the data storage unit.

10. The flash memory chip of claim 9, wherein the memory chip further comprises a memory chip,

The storage control unit is used for determining a corresponding interval voltage signal according to the second data information cached by the page buffer;

And writing the second data information into the data storage unit according to the corresponding interval voltage signal.

11. The flash memory chip of claim 10, wherein the memory chip further comprises a memory chip,

The storage control unit is used for determining 16 voltage intervals corresponding to 4-bit data, and the 16 voltage intervals are determined by 15 critical voltage values; and

Determining 4 voltage intervals determined by the first buffer area, the second buffer area, the third buffer area and the fourth buffer area, wherein the 4 voltage intervals are determined by 3 critical voltage values;

Wherein, one of the 15 critical voltage values and the corresponding offset are adopted to respectively represent the 3 critical voltage values.

12. The flash memory chip of claim 11, wherein,

The storage control unit performs voltage comparison of the voltage information in the data storage unit with the 4 voltage sections to read the second data information stored in the data storage unit.

13. The flash memory chip of claim 1, wherein,

The storage control unit is used for writing data in the third buffer area of the page buffer;

Generating data in the fourth buffer area; the data generated by the fourth buffer area is obtained by performing logic operation on any two of the data of the first buffer area, the data of the second buffer area and the data of the third buffer area, and the data of the first buffer area, the second buffer area, the third buffer area and the fourth buffer area determine third data information;

and writing the third data information stored by the page buffer into the data storage unit.

14. The flash memory chip of claim 13, wherein the memory chip further comprises a memory chip,

The storage control unit determines a corresponding interval voltage signal according to the third data information cached by the page buffer;

and writing the third data information into the data storage unit according to the corresponding interval voltage signal.

15. The flash memory chip of claim 14, wherein the memory chip further comprises a memory chip,

The storage control unit determines 16 voltage intervals corresponding to 4-bit data, wherein the 16 voltage intervals are determined by 15 critical voltage values; and

Determining 8 voltage intervals determined by the first buffer area, the second buffer area, the third buffer area and the fourth buffer area, wherein the 8 voltage intervals are determined by 7 critical voltage values;

Wherein, one of the 15 critical voltage values and the corresponding offset are adopted to respectively represent the 8 critical voltage values.

16. The flash memory chip of claim 15, wherein,

The storage control unit performs voltage comparison of the voltage information in the data storage unit with the 8 voltage sections to read the third data information stored in the data storage unit.

17. The flash memory chip of claim 1, wherein,

The flash memory chip is TLC/QLC NAND FLASH memory.