CN118112400A

CN118112400A - Frequency test method, frequency test device and program product for differential clock signal

Info

Publication number: CN118112400A
Application number: CN202410537599.6A
Authority: CN
Inventors: 郭毅
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2024-04-30
Filing date: 2024-04-30
Publication date: 2024-05-31

Abstract

The embodiment of the application provides a frequency testing method, a frequency testing device and a program product of a differential clock signal, wherein the method comprises the following steps: receiving a differential clock signal generated by the clock source equipment through the connector, and adjusting the signal vibration amplitude of the differential clock signal according to the preset signal vibration amplitude to obtain a target differential clock signal; determining a matching result between the target differential clock signal and the preset differential clock signal by using the target preset frequency of the target differential clock signal, the signal frequency of the preset differential clock signal and the gating count of the target differential clock signal in a preset time period; and testing the frequency of the target differential clock signal according to the matching result to determine whether the frequency of the target differential clock signal is abnormal or not based on the testing result. The application solves the problem that the frequency of the differential clock signal cannot be tested in the related technology.

Description

Frequency test method, frequency test device and program product for differential clock signal

Technical Field

The embodiment of the application relates to the field of computers, in particular to a frequency testing method, a frequency testing device and a program product of a differential clock signal.

Background

The boundary scan test is a test based on the 1149 protocol. All kinds of connector interfaces supporting 1149 protocol can realize full-automatic plug in the test process, no manual participation is needed, and the test time is about 2 minutes.

However, in the boundary scan test, there is no method for detecting differential clock signals, and the differential clock signals are not tested in the boundary scan test, so that the coverage of the test on the signals is not achieved.

Disclosure of Invention

The embodiment of the application provides a frequency testing method, a frequency testing device and a program product for a differential clock signal, which at least solve the problem that the frequency of the differential clock signal cannot be tested in the related technology.

According to an aspect of an embodiment of the present invention, there is provided a frequency testing method of a differential clock signal, applied to a frequency testing apparatus, the frequency testing apparatus being connected to a clock source device through a connector, the method including: receiving a differential clock signal generated by the clock source equipment through the connector, and adjusting the signal vibration amplitude of the differential clock signal according to a preset signal vibration amplitude to obtain a target differential clock signal, wherein the differential clock signal is a signal for data transmission or time sequence control, and the signal vibration amplitude of the target differential clock signal is larger than that of the differential clock signal; determining a matching result between the target differential clock signal and the preset differential clock signal by using a target preset frequency of the target differential clock signal, a signal frequency of the preset differential clock signal and a gating count of the target differential clock signal in a preset time period, wherein the gating count is used for representing the pulse number or the period number of the target differential clock signal in the preset time period; and testing the frequency of the target differential clock signal according to the matching result to determine whether the frequency of the target differential clock signal is abnormal or not based on the testing result.

In an exemplary embodiment, receiving, by the connector, a differential clock signal generated by the clock source device, and adjusting a signal vibration amplitude of the differential clock signal according to a preset signal vibration amplitude, to obtain a target differential clock signal, including: receiving, by the connector, a plurality of pairs of the differential clock signals generated by the clock source device, wherein the differential clock signals are clock signals generated by a differential clock signal source after a computer system is started; and adjusting the signal vibration amplitude of the differential clock signals by an amplifier according to the preset signal vibration amplitude to obtain the target differential clock signal, wherein the amplifier is arranged in the frequency testing device.

In one exemplary embodiment, determining a matching result between the target differential clock signal and the preset differential clock signal using a target preset frequency of the target differential clock signal, a signal frequency of the preset differential clock signal, and a gating count of the target differential clock signal for a preset period of time includes: determining the gating count of the target differential clock signal in the preset time period through a counter; determining clock counts of the preset differential clock signals according to the cycle numbers of the preset differential clock signals in the preset time period; and matching the target preset frequency by utilizing the corresponding relation among the signal frequency of the preset differential clock signal, the gating count and the clock count to obtain the matching result.

In an exemplary embodiment, matching the target preset frequency with the corresponding relation among the signal frequency of the preset differential clock signal, the gating count and the clock count to obtain the matching result includes: the matching result is calculated by the following formula:，/> Wherein clk_fx is used to represent the target preset frequency, fx_cnt is used to represent the gating count, gateTime is used to represent the preset time period, clk_fs is used to represent the signal frequency of the preset differential clock signal, and fs_cnt is used to represent the clock count; will said/> Comparing with the target preset frequency, and calculating the/>, according to the comparison resultAnd obtaining the matching result by matching the target preset frequency with the matching degree.

In an exemplary embodiment, before determining the matching result between the target differential clock signal and the preset differential clock signal, using the target preset frequency of the target differential clock signal, the signal frequency of the preset differential clock signal, and the gate count of the target differential clock signal in the preset time period, the method further includes: acquiring a preset frequency of the target differential clock signal, wherein the preset frequency is preset according to the signal type of the target differential clock signal; and adjusting the preset frequency according to a preset frequency proportion to obtain the target preset frequency, wherein the target preset frequency is smaller than the preset frequency.

In one exemplary embodiment, testing the frequency of the target differential clock signal according to the matching result to determine whether the frequency of the target differential clock signal is abnormal based on the test result includes: determining that the frequency of the target differential clock signal is in an abnormal state under the condition that the matching degree between the target differential clock signal and the preset differential clock signal displayed in the matching result is smaller than the preset matching degree, wherein the abnormal state is used for indicating that a clock signal line of the target differential clock signal is short-circuited or open-circuited; and under the condition that the matching degree between the target differential clock signal and the preset differential clock signal is larger than the preset matching degree, determining that the frequency of the target differential clock signal is in a normal state.

In an exemplary embodiment, after testing the frequency of the target differential clock signal according to the matching result to determine whether the frequency of the target differential clock signal is abnormal based on the test result, the method further includes: converting the test result into a level signal, wherein when the level signal is a high level signal, the frequency of the target differential clock signal is in a normal state, and when the level signal is a low level signal, the frequency of the target differential clock signal is in an abnormal state; transmitting the level signal to a boundary scan test device, wherein the boundary scan test device is configured to identify the level signal and display an identification result, and a format of the identification result includes at least one of: text format, digital format, signal format supported by the transport protocol of the boundary scan test equipment.

In an exemplary embodiment, after converting the test result into a level signal, the method further comprises: sending a prompt instruction to prompt equipment according to the level signal so as to control the prompt equipment to send prompt information according to the prompt instruction, wherein the prompt instruction comprises the test result, the prompt information is used for prompting whether the frequency of the target differential clock signal is in an abnormal state or not, and the prompt information comprises at least one of the following components: voice prompt and color prompt.

According to another aspect of the embodiment of the present invention, there is also provided a frequency testing apparatus, including: the device comprises a connector, a processing chip and a transmission device, wherein the connector is used for connecting a clock source device, wherein the clock source device is used for generating a differential clock signal, and the differential clock signal is a signal used for data transmission or time sequence control; the processing chip is connected with the connector and is used for receiving the differential clock signal generated by the clock source equipment through the connector, and the processing chip is provided with the method in any one of the above steps; the transmission device is connected with the processing chip and used for transmitting the test result processed by the processing chip to external equipment, wherein the test result is used for determining whether the frequency of the target differential clock signal is abnormal or not.

In an exemplary embodiment, an amplifier, a processor and a counter are disposed in the processing chip, where the amplifier is connected to the connector and is configured to adjust a signal vibration amplitude of the differential clock signal according to a preset signal vibration amplitude, so as to obtain the target differential clock signal; the processor is connected with the amplifier and is used for receiving the target differential clock signal sent by the amplifier; the counter is connected with the processor, and is used for receiving the target differential clock signal sent by the processor and determining a gating count of the target differential clock signal in a preset time period, wherein the gating count is used for representing the pulse number or the period number of the target differential clock signal in the preset time period; the processor is further configured to determine a matching result between the target differential clock signal and the preset differential clock signal by using a target preset frequency of the target differential clock signal, a signal frequency of the preset differential clock signal, and a gating count of the target differential clock signal in a preset time period, and test the frequency of the target differential clock signal according to the matching result, so as to determine whether the frequency of the target differential clock signal is abnormal based on the test result.

In an exemplary embodiment, a field programmable gate array device is further disposed in the processing chip, where the field programmable gate array device is connected to the processor, and is configured to transmit the level signal to a boundary scan test device connected to the field programmable gate array device, where the boundary scan test device is configured to identify the level signal and display an identification result, and a format of the identification result includes at least one of: text format, digital format, signal format supported by the transport protocol of the boundary scan test equipment.

In an exemplary embodiment, the field programmable gate array device includes an input pin and an output pin, wherein the input pin is connected with the processor and is used for transmitting the level signal to the output pin; the output pin is connected with the boundary scan test equipment and used for transmitting the level signal to the boundary scan test equipment.

In one exemplary embodiment, a hint device is also disposed in the processing chip, wherein,

The prompting device is connected with the processor, and is used for receiving a prompting instruction sent by the processor and sending prompting information according to the prompting instruction, wherein the prompting instruction is generated by the processor according to the level signal, the prompting information is used for prompting whether the frequency of the target differential clock signal is in an abnormal state or not, and the prompting information comprises at least one of the following components: voice prompt and color prompt.

In an exemplary embodiment, the frequency testing apparatus further comprises a switching device, the switching device comprising a first switching interface and a second switching interface, wherein the first switching interface is connected with the connector for transmitting the differential clock signal to the connector; the second switching interface is connected with the field programmable gate array device and used for transmitting other signals to the field programmable gate array device, wherein the field programmable gate array device is connected with the field programmable gate array device and used for testing whether the frequencies of the other signals are abnormal or not.

According to a further embodiment of the application, there is also provided a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

According to a further embodiment of the application, there is also provided a computer readable storage medium having stored therein a computer program, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

According to a further embodiment of the application there is also provided an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

According to the application, as the received differential clock signal is subjected to signal vibration amplitude amplification, a target differential clock signal is obtained; and determining a matching result of the target differential clock signal and the standard preset differential clock signal, and testing whether the frequency of the target differential clock signal is abnormal or not based on the matching result. The method and the device realize the purpose of automatically testing the frequency of the differential clock signal, and can improve the accuracy of the test result, thereby solving the problem that the frequency of the differential clock signal cannot be tested in the related technology.

Drawings

Fig. 1 is a block diagram of a hardware structure of a mobile terminal according to a frequency test method of a differential clock signal according to an embodiment of the present application;

FIG. 2 is a flow chart of a method of frequency testing of a differential clock signal according to an embodiment of the application;

FIG. 3 is a schematic block diagram of acquiring a differential clock signal according to an embodiment of the application;

FIG. 4 is an enlarged schematic block diagram according to an embodiment of the application;

FIG. 5 is a schematic diagram of signal alignment according to an embodiment of the application;

FIG. 6 is a schematic diagram of frequency measurement logic according to an embodiment of the application;

fig. 7 is a block diagram of a frequency test apparatus according to an embodiment of the present application;

FIG. 8 is a block diagram of a frequency testing apparatus when the field programmable gate array device is an FPGA in accordance with an embodiment of the application;

Fig. 9 is a block diagram of a frequency test apparatus of a differential clock signal according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will be described in detail below with reference to the accompanying drawings in conjunction with the embodiments.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present application and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order.

The method embodiments provided in the embodiments of the present application may be performed in a mobile terminal, a computer terminal or similar computing device. Taking the mobile terminal as an example, fig. 1 is a block diagram of a hardware structure of the mobile terminal according to a frequency testing method of a differential clock signal according to an embodiment of the present application. As shown in fig. 1, a mobile terminal may include one or more (only one is shown in fig. 1) processors 102 (the processor 102 may include, but is not limited to, a microprocessor MCU or a processing device such as a programmable logic device FPGA) and a memory 104 for storing data, wherein the mobile terminal may also include a transmission device 106 for communication functions and an input-output device 108. It will be appreciated by those skilled in the art that the structure shown in fig. 1 is merely illustrative and not limiting of the structure of the mobile terminal described above. For example, the mobile terminal may also include more or fewer components than shown in fig. 1, or have a different configuration than shown in fig. 1.

The memory 104 may be used to store a computer program, for example, a software program of application software and a module, such as a computer program corresponding to a frequency test method of a differential clock signal in an embodiment of the present application, and the processor 102 executes the computer program stored in the memory 104, thereby performing various functional applications and data processing, that is, implementing the above-mentioned method. Memory 104 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some examples, the memory 104 may further include memory remotely located relative to the processor 102, which may be connected to the mobile terminal via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

The transmission device 106 is used to receive or transmit data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider of the mobile terminal. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, simply referred to as a NIC) that can connect to other network devices through a base station to communicate with the internet. In one example, the transmission device 106 may be a Radio Frequency (RF) module, which is configured to communicate with the internet wirelessly.

In this embodiment, a frequency testing method of a differential clock signal is provided and applied to a frequency testing device, where the frequency testing device is connected to a clock source device through a connector, and fig. 2 is a flowchart of the frequency testing method of the differential clock signal according to an embodiment of the present application, as shown in fig. 2, and the flowchart includes the following steps:

Step S202, receiving a differential clock signal generated by the clock source equipment through the connector, and adjusting the signal vibration amplitude of the differential clock signal according to a preset signal vibration amplitude to obtain a target differential clock signal, wherein the differential clock signal is a signal for data transmission or time sequence control, and the signal vibration amplitude of the target differential clock signal is larger than that of the differential clock signal;

Step S204, determining a matching result between the target differential clock signal and the preset differential clock signal by using a target preset frequency of the target differential clock signal, a signal frequency of the preset differential clock signal and a gating count of the target differential clock signal in a preset time period, wherein the gating count is used for indicating the pulse number or the period number of the target differential clock signal in the preset time period;

step S206, testing the frequency of the target differential clock signal according to the matching result to determine whether the frequency of the target differential clock signal is abnormal or not based on the testing result.

Through the steps, as the received differential clock signal is subjected to signal vibration amplitude amplification, a target differential clock signal is obtained; and determining a matching result of the target differential clock signal and the standard preset differential clock signal, and testing whether the frequency of the target differential clock signal is abnormal or not based on the matching result. The method and the device realize the purpose of automatically testing the frequency of the differential clock signal, and can improve the accuracy of the test result, thereby solving the problem that the frequency of the differential clock signal cannot be tested in the related technology.

Alternatively, the differential clock signal is a signal used in a digital circuit to synchronize the actions of the individual elements. It indicates when the elements in the circuit should operate to ensure that they are working in the correct order and time. Differential clock signals typically emanate at a fixed frequency and propagate throughout the circuit to ensure that the operation of the various elements are coordinated. Differential clock signals play an important role in digital systems and can be used to synchronize the operation of processors, memories and other electronic components to ensure that they operate in the correct order and timing.

In addition to the differential clock signal, the embodiment can be applied to a reset signal and also can be SLIMLINE clock signals in SLIMLINE signals, namely clock signals for synchronous data transmission, but the clock signals have different characteristics and application scenes. For example, a differential clock signal is a clock signal transmitted using a differential signal, and interference and noise in a transmission process are reduced by simultaneously transmitting the differential clock signal and an inverted signal thereof, thereby improving reliability and stability of data transmission. Differential clock signals are often used in high-speed data transmission scenarios, such as high-speed communication interfaces, high-speed memory interfaces, and the like. SLIMLINE clock signal is a low power consumption, high performance clock signal commonly used in mobile devices and embedded systems to meet the requirements for high performance and low power consumption. The SLIMLINE clock signal adopts a special clock circuit design and an optimized clock signal transmission mode, so that the power consumption can be reduced while the high performance is maintained, and the method is suitable for application scenes with high requirements on battery endurance time and heat dissipation. In general, the differential clock signal is suitable for high-speed data transmission scenarios, while the SLIMLINE clock signal is suitable for application scenarios where power consumption and performance requirements are balanced.

The reset signal is a signal used to restore a circuit or system to an initial state, typically to clear registers, initialize logic elements, and restore the system to a known state. The measured clock signal refers to a measured differential clock signal that is used to measure the frequency, phase, or other clock-related characteristics of the clock.

As another example, as shown in Table 1, SLIMLINE are power supply, GND, differential Serdes, differential clocks, and other signals, wherein the signals generated by the differential clocks in A11 and A12 are differential clock signals that cannot be boundary scan tested.

Table 1:

A differential clock is a clock used to measure time intervals. It calculates the time interval by comparing the time differences of two clocks, typically for measuring the time interval between events, e.g. in experiments. Differential clocks are generally of higher accuracy and stability and are therefore widely used in applications requiring accurate measurement of time intervals, such as in the fields of scientific experimentation, engineering measurements and computer network synchronization.

Alternatively, the predetermined differential clock signal is a reference differential clock signal, which refers to a signal generated by an accurate, stable clock device for measuring and calibrating other clocks or timing devices. Reference clocks typically use atomic clocks or other high precision clock devices to ensure their accuracy and stability.

In an exemplary embodiment, the connector is used for receiving the differential clock signal generated by the clock source device, and adjusting the signal vibration amplitude of the differential clock signal according to the preset signal vibration amplitude to obtain a target differential clock signal: receiving, by the connector, a plurality of pairs of the differential clock signals generated by the clock source device, wherein the differential clock signals are clock signals generated by a differential clock signal source after a computer system is started; and adjusting the signal vibration amplitude of the differential clock signals by an amplifier according to the preset signal vibration amplitude to obtain the target differential clock signal, wherein the amplifier is arranged in the frequency testing device.

Alternatively, a connector is a device for connecting two or more electronic devices or electronic components. They may be used to transmit data, power, signals, or other types of information. For example, as shown in fig. 3, the connector is SLIMLINE, after the computer system is normally started, SLIMLINE is connected to 2 pairs of 100MHz differential clock signals, and the clock source device is a differential clock.

Alternatively, the reasons for the occurrence of the differential clock after the normal start of the computer system (board) include, but are not limited to: 1. clock synchronization problem: the clock of the board may not be synchronized with the network or other device, resulting in the occurrence of a differential clock. 2. Power supply problem: the poor power stability of the board may cause clock instability, thereby generating a differential clock. 3. Hardware failure: the clock chip or other related hardware on the board malfunctions, resulting in inaccurate clocks. 4. Software configuration problem: an error may occur in the clock configuration of the board, resulting in the occurrence of a differential clock.

Optionally, the differential clock signal is amplified in amplitude and unchanged in frequency after passing through the signal amplifier. For example, as shown in FIG. 4, from 1, 3"IN" inputs and from 5"OUT" outputs.

In the embodiment, the signal vibration amplitude of the differential clock signal is increased by using the amplifier, and the period and the frequency of the differential clock signal are still unchanged, so that the stability and the accuracy of the differential clock signal can be ensured.

Alternatively, the present embodiment performs calculation using a precision frequency measurement method, which is a method for measuring a signal frequency, the precision of which depends on the precision of the measuring apparatus and technique.

Optionally, matching with the target preset frequency by using a corresponding relationship among the signal frequency of the preset differential clock signal, the gating count and the clock count to obtain the matching result, including: the matching result is calculated by the following formula:，/> Wherein clk_fx is used to represent the target preset frequency, fx_cnt is used to represent the gating count, gateTime is used to represent the preset time period, clk_fs is used to represent the signal frequency of the preset differential clock signal, and fs_cnt is used to represent the clock count; will said/> Comparing with the target preset frequency, and calculating the/>, according to the comparison resultAnd obtaining the matching result by matching the target preset frequency with the matching degree.

Optionally, before determining the matching result between the target differential clock signal and the preset differential clock signal, using the target preset frequency of the target differential clock signal, the signal frequency of the preset differential clock signal, and the gate count of the target differential clock signal in the preset time period, the method further includes: acquiring a preset frequency of the target differential clock signal, wherein the preset frequency is preset according to the signal type of the target differential clock signal; and adjusting the preset frequency according to a preset frequency proportion to obtain the target preset frequency, wherein the target preset frequency is smaller than the preset frequency.

For example, as shown in fig. 5, the target preset frequency of the target differential clock signal is clk_fx, the gate count is fx_cnt, the signal frequency of the preset differential clock signal detected in the same time GateTime is clk_fs, and the clock count is fs_cnt.

For another example, the signal frequency of the preset differential clock signal is 20MHz, and the target differential clock signal is tested after being divided into 1MHz (clk_fx). Since the gating count (fx_cnt) ×20MHz (clk_fs) =the system clock count (fs_cnt) ×1MHz (clk_fx), the gating count value fx_cnt is selected to be 100. If the FPGA with larger resource is selected, a higher gating count value can be selected, and the test precision is higher, but the embodiment is characterized by testing the frequency (detecting the short circuit and the open circuit of the differential clock signal by measuring the frequency).

When the gating count fx_cnt=50 is measured, it is calculated according to the formula: 50×20/1000=1, and clk_fx=1 MHz, it can be determined that the frequency of the target differential clock signal is a normal frequency. When the gating count fx_cnt=30 is measured, 30×20/1000=0.6 is calculated according to a formula, and is different from clk_fx=1 MHz, it can be determined that the frequency of the target differential clock signal is abnormal.

According to the embodiment, the signal frequency of the preset differential clock signal, the corresponding relation between the gate control count and the clock count and the target preset frequency are compared, so that a relatively accurate comparison result can be obtained.

Optionally, the short circuit of the target differential clock signal refers to a short circuit phenomenon occurring on the differential clock signal line, so that the differential clock signal cannot be normally transmitted, and may affect the working stability and performance of the whole system. The disconnection of the differential clock signal means that a disconnection phenomenon occurs on the differential clock signal line, so that the differential clock signal cannot be normally transmitted, and the system may not normally work or have a timing error. In integrated circuit designs, both short and open circuits of the differential clock signal are very serious problems that can cause the entire chip to fail to function properly. An open circuit of a target differential clock signal refers to a condition in which a disconnection or open circuit occurs on the differential clock signal line, resulting in that the differential clock signal cannot be normally transmitted to the target device or module. An open circuit of the differential clock signal may cause an error or loss of data transmission between the devices, which may affect the normal operation of the system. Differential clock signal lines refer to signal lines used in digital circuits to synchronize the operation of individual logic elements. The differential clock signal lines may pulse at a frequency to tell the logic element when to transfer, process or store data. The frequency of the differential clock signal lines depends on the design of the digital circuit, typically in hertz (Hz). In synchronous circuits, the stability and accuracy of the differential clock signal lines are important to the performance of the digital system.

According to the embodiment, whether the frequency of the target differential clock signal is abnormal or not can be accurately tested through the comparison result.

Alternatively, the boundary scan test device may be BSI (Boundary Scan Inspection), a device that performs testing based on the 1149 protocol. The boundary scan test equipment is used to test power supplies, GND, differential Serdes, and other signals. All kinds of connector interfaces supporting 1149 protocol can realize full-automatic plug in the test process, no manual participation is needed, and the test time is about 2 minutes.

Alternatively, as shown in fig. 6, the FPGA frequency measurement logic included in the frequency test apparatus feeds back the test result to pins (43, 44, 45, 46 pin) of the corresponding FPGA, and the boundary scan test device x1149 judges the frequency test result by reading the value of the corresponding pin. I.e., to convert the test results to signals supporting the 1149 protocol, it is first necessary to convert the test results to digital signals. The digital signal is then encoded and decoded according to the requirements of the 1149 protocol to conform to the signal transmission standard of the 1149 protocol. Special tools and equipment are required for signal conversion and processing. Finally, the converted signals are output to an interface conforming to the 1149 protocol for further testing and analysis. For example, if the frequency test result is Fail, the x1149 software will report that the particular pin frequency is not too high (e.g., A8 Fail); after the pins to be tested are tested by the frequency measurement module, pass and Fail can output different results to the specific pins of the FPGA, the states of the specific pins are read through boundary scanning, and the states are fed back to x1149 software for judgment, so that whether the frequency test is abnormal or not can be judged.

According to the embodiment, the level signal is transmitted to the boundary scan test equipment, the boundary scan test equipment identifies the level signal and displays the identification result, so that the identification result can be quickly obtained.

Alternatively, the alert device is a device for issuing an alert signal to inform whether or not an abnormality is present. The alert signal may be sent by sound, light, or other means. For example, whether or not abnormality is indicated by the color of the indicator lamp, green represents normal, and red represents abnormality. The prompting device in this embodiment may be a device disposed in the frequency testing apparatus, or may be an external device. According to the embodiment, the test result can be determined rapidly through the prompting device.

In this embodiment, there is also provided a frequency testing device, and fig. 7 is a block diagram of a frequency testing device according to an embodiment of the present application, as shown in fig. 7, where the device includes: a connector, a processing chip and a transmission device, wherein,

The connector is used for connecting clock source equipment, wherein the clock source equipment is used for generating differential clock signals, and the differential clock signals are signals used for data transmission or time sequence control;

The processing chip is connected with the connector and is used for receiving the differential clock signal generated by the clock source equipment through the connector, and the processing chip is provided with the method in any one of the above steps;

The transmission device is connected with the processing chip and used for transmitting the test result processed by the processing chip to external equipment, wherein the test result is used for determining whether the frequency of the target differential clock signal is abnormal or not.

By the device, the received differential clock signal is subjected to signal vibration amplitude amplification to obtain a target differential clock signal; and determining a matching result of the target differential clock signal and the standard preset differential clock signal, and testing whether the frequency of the target differential clock signal is abnormal or not based on the matching result. The method and the device realize the purpose of automatically testing the frequency of the differential clock signal, and can improve the accuracy of the test result, thereby solving the problem that the frequency of the differential clock signal cannot be tested in the related technology.

Table 1:

Optionally, a field programmable gate array device is further disposed in the processing chip, where the field programmable gate array device is connected to the processor and is configured to transmit the level signal to a boundary scan test device connected to the field programmable gate array device, where the boundary scan test device is configured to identify the level signal and display an identification result, and a format of the identification result includes at least one of: text format, digital format, signal format supported by the transport protocol of the boundary scan test equipment.

Optionally, the field programmable gate array device includes an input pin and an output pin, where the input pin is connected to the processor and is used to transmit the level signal to the output pin; the output pin is connected with the boundary scan test equipment and used for transmitting the level signal to the boundary scan test equipment.

Alternatively, when the field programmable gate array device is an FPGA and the boundary scan test device is x1149, a structural diagram of the frequency test apparatus is shown in fig. 8.

In an exemplary embodiment, a prompting device is further disposed in the processing chip, where the prompting device is connected to the processor, and is configured to receive a prompting instruction sent by the processor, and send prompting information according to the prompting instruction, where the prompting instruction is generated by the processor according to the level signal, and the prompting information is used to prompt whether the frequency of the target differential clock signal is in an abnormal state, and the prompting information includes at least one of: voice prompt and color prompt.

Alternatively, the alert device is a device for issuing an alert signal to inform whether or not an abnormality is present. An alarm signal may be sounded, light, or otherwise. For example, whether or not abnormality is indicated by the color of the indicator lamp, green represents normal, and red represents abnormality. The prompting device in this embodiment may be a device disposed in the frequency testing apparatus, or may be an external device. According to the embodiment, the test result can be determined rapidly through the prompting device.

Alternatively, the switching device may be used to connect different types or specifications of devices or interfaces to enable transmission or conversion of signals. Interface types for the switching device include, but are not limited to: USB interface, HDMI interface, VGA interface, thunder and lightning interface, network interface, etc. The first interface and the second interface may be used to connect different test devices or sensors, respectively, for frequency testing. The switching device may enable connection between different interfaces through adapters, converters or other types of connectors. Thus, the frequency test can be flexibly performed, and the device is suitable for different types or specifications of devices.

From the description of the above embodiments, it will be clear to a person skilled in the art that the method according to the above embodiments may be implemented by means of software plus the necessary general hardware platform, but of course also by means of hardware, but in many cases the former is a preferred embodiment. Based on such understanding, the technical solution of the present application may be embodied essentially or in a part contributing to the prior art in the form of a software product stored in a storage medium (e.g. ROM/RAM, magnetic disk, optical disk) comprising instructions for causing a terminal device (which may be a mobile phone, a computer, a server, or a network device, etc.) to perform the method according to the embodiments of the present application.

The embodiment also provides a device for testing the frequency of the differential clock signal, which is used for implementing the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

Fig. 9 is a block diagram of a frequency test apparatus of a differential clock signal according to an embodiment of the present application, as shown in fig. 9, the apparatus including:

A first adjusting module 902, configured to receive, through the connector, a differential clock signal generated by the clock source device, and adjust a signal vibration amplitude of the differential clock signal according to a preset signal vibration amplitude, so as to obtain a target differential clock signal, where the differential clock signal is a signal for data transmission or timing control, and the signal vibration amplitude of the target differential clock signal is greater than the signal vibration amplitude of the differential clock signal;

a first determining module 904, configured to determine a matching result between the target differential clock signal and the preset differential clock signal by using a target preset frequency of the target differential clock signal, a signal frequency of the preset differential clock signal, and a gating count of the target differential clock signal in a preset time period, where the gating count is used to represent a pulse number or a cycle number of the target differential clock signal in the preset time period;

A first test module 906, configured to test the frequency of the target differential clock signal according to the matching result, so as to determine whether the frequency of the target differential clock signal is abnormal based on the test result.

In an exemplary embodiment, the first adjusting module 902 includes: a first receiving unit, configured to receive, through the connector, a plurality of pairs of the differential clock signals generated by the clock source device, where the differential clock signals are clock signals generated by a differential clock signal source after the computer system is started; and the first adjusting unit is used for obtaining the target differential clock signal by adjusting the signal vibration amplitude of the differential clock signals according to the preset signal vibration amplitude through an amplifier, wherein the amplifier is arranged in the frequency testing device.

In an exemplary embodiment, the first determining module 904 includes: a first determining unit, configured to determine, by using a counter, the gating count of the target differential clock signal in the preset period;

A second determining unit, configured to determine a clock count of the preset differential clock signal according to a cycle number of the preset differential clock signal in the preset time period;

And the first matching unit is used for matching with the target preset frequency by utilizing the corresponding relation among the signal frequency of the preset differential clock signal, the gating count and the clock count to obtain the matching result.

In an exemplary embodiment, the first matching unit is configured to calculate the matching result by the following formula:，/> Wherein clk_fx is used to represent the target preset frequency, fx_cnt is used to represent the gating count, gateTime is used to represent the preset time period, clk_fs is used to represent the signal frequency of the preset differential clock signal, and fs_cnt is used to represent the clock count; will said/> Comparing the target preset frequency with the target preset frequency, and calculating the target preset frequency according to a comparison resultAnd obtaining the matching result by matching the target preset frequency with the matching degree.

In an exemplary embodiment, the above apparatus further includes: the first acquisition module is used for acquiring the preset frequency of the target differential clock signal before determining a matching result between the target differential clock signal and the preset differential clock signal by utilizing the target preset frequency of the target differential clock signal, the signal frequency of the preset differential clock signal and the gating count of the target differential clock signal in a preset time period, wherein the preset frequency is a frequency preset according to the signal type of the target differential clock signal; the second adjusting module is used for adjusting the preset frequency according to a preset frequency proportion to obtain the target preset frequency, wherein the target preset frequency is smaller than the preset frequency.

In one exemplary embodiment, the first test module 906 includes: the first test unit is used for determining that the frequency of the target differential clock signal is in an abnormal state when the matching degree between the target differential clock signal and the preset differential clock signal displayed in the matching result is smaller than the preset matching degree, wherein the abnormal state is used for indicating that a clock signal line of the target differential clock signal is short-circuited or open-circuited; and the third determining unit is used for determining that the frequency of the target differential clock signal is in a normal state under the condition that the matching degree between the target differential clock signal and the preset differential clock signal is larger than the preset matching degree in the matching result.

In an exemplary embodiment, the above apparatus further includes: a first conversion module, configured to test the frequency of the target differential clock signal according to the matching result, so as to determine whether the frequency of the target differential clock signal is abnormal based on the test result, and a second conversion module, configured to convert the test result into a level signal, where when the level signal is a high level signal, the frequency of the target differential clock signal is in a normal state, and when the level signal is a low level signal, the frequency of the target differential clock signal is in an abnormal state; the first transmission module is used for transmitting the level signal to boundary scan test equipment, wherein the boundary scan test equipment is used for identifying the level signal and displaying an identification result, and the format of the identification result comprises at least one of the following: text format, digital format, signal format supported by the transport protocol of the boundary scan test equipment.

In an exemplary embodiment, the above apparatus further includes: the first sending module is used for sending a prompt instruction to prompt equipment according to the level signal after the test result is converted into the level signal so as to control the prompt equipment to send prompt information according to the prompt instruction, wherein the prompt instruction comprises the test result, the prompt information is used for prompting whether the frequency of the target differential clock signal is in an abnormal state or not, and the prompt information comprises at least one of the following components: voice prompt and color prompt.

It should be noted that each of the above modules may be implemented by software or hardware, and for the latter, it may be implemented by, but not limited to: the modules are all located in the same processor; or the above modules may be located in different processors in any combination.

Embodiments of the application also provide a computer program product comprising a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

Embodiments of the present application also provide another computer program product comprising a non-volatile computer readable storage medium storing a computer program which, when executed by a processor, implements the steps of any of the method embodiments described above.

Embodiments of the present application also provide a computer program comprising computer instructions stored in a computer-readable storage medium; the processor of the computer device reads the computer instructions from the computer readable storage medium and the embedder executes the computer instructions to cause the computer device to perform the steps of any of the method embodiments described above.

Embodiments of the present application also provide a computer readable storage medium having a computer program stored therein, wherein the computer program is arranged to perform the steps of any of the method embodiments described above when run.

In one exemplary embodiment, the computer readable storage medium may include, but is not limited to: a usb disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory RAM), a removable hard disk, a magnetic disk, or an optical disk, or other various media capable of storing a computer program.

An embodiment of the application also provides an electronic device comprising a memory having stored therein a computer program and a processor arranged to run the computer program to perform the steps of any of the method embodiments described above.

In an exemplary embodiment, the electronic device may further include a transmission device connected to the processor, and an input/output device connected to the processor.

Specific examples in this embodiment may refer to the examples described in the foregoing embodiments and the exemplary implementation, and this embodiment is not described herein.

It will be appreciated by those skilled in the art that the modules or steps of the application described above may be implemented in a general purpose computing device, they may be concentrated on a single computing device, or distributed across a network of computing devices, they may be implemented in program code executable by computing devices, so that they may be stored in a storage device for execution by computing devices, and in some cases, the steps shown or described may be performed in a different order than that shown or described herein, or they may be separately fabricated into individual integrated circuit modules, or multiple modules or steps of them may be fabricated into a single integrated circuit module. Thus, the present application is not limited to any specific combination of hardware and software.

The above description is only of the preferred embodiments of the present application and is not intended to limit the present application, but various modifications and variations can be made to the present application by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the principle of the present application should be included in the protection scope of the present application.

Claims

1. A method for testing the frequency of a differential clock signal, applied to a frequency testing device, the frequency testing device being connected to a clock source device by a connector, the method comprising:

Receiving a differential clock signal generated by the clock source equipment through the connector, and adjusting the signal vibration amplitude of the differential clock signal according to a preset signal vibration amplitude to obtain a target differential clock signal, wherein the differential clock signal is a signal for data transmission or time sequence control, and the signal vibration amplitude of the target differential clock signal is larger than that of the differential clock signal;

Determining a matching result between the target differential clock signal and the preset differential clock signal by using a target preset frequency of the target differential clock signal, a signal frequency of the preset differential clock signal and a gating count of the target differential clock signal in a preset time period, wherein the gating count is used for representing the pulse number or the period number of the target differential clock signal in the preset time period;

And testing the frequency of the target differential clock signal according to the matching result to determine whether the frequency of the target differential clock signal is abnormal or not based on the testing result.

2. The method of claim 1, wherein receiving the differential clock signal generated by the clock source device through the connector and adjusting the signal vibration amplitude of the differential clock signal according to a preset signal vibration amplitude to obtain the target differential clock signal comprises:

Receiving, by the connector, a plurality of pairs of the differential clock signals generated by the clock source device, wherein the differential clock signals are clock signals generated by a differential clock signal source after a computer system is started;

And adjusting the signal vibration amplitude of the differential clock signals by an amplifier according to the preset signal vibration amplitude to obtain the target differential clock signal, wherein the amplifier is arranged in the frequency testing device.

3. The method of claim 1, wherein determining a match between the target differential clock signal and the preset differential clock signal using a target preset frequency of the target differential clock signal, a signal frequency of the preset differential clock signal, and a gating count of the target differential clock signal for a preset period of time comprises:

Determining the gating count of the target differential clock signal in the preset time period through a counter;

Determining clock counts of the preset differential clock signals according to the cycle numbers of the preset differential clock signals in the preset time period;

And matching the target preset frequency by utilizing the corresponding relation among the signal frequency of the preset differential clock signal, the gating count and the clock count to obtain the matching result.

4. A method according to claim 3, wherein matching the target preset frequency with the correspondence between the signal frequency of the preset differential clock signal, the gating count and the clock count to obtain the matching result comprises:

the matching result is calculated by the following formula:

，/> Wherein clk_fx is used to represent the target preset frequency, fx_cnt is used to represent the gating count, gateTime is used to represent the preset time period, clk_fs is used to represent the signal frequency of the preset differential clock signal, and fs_cnt is used to represent the clock count;

The said Comparing the target preset frequency with the target preset frequency, and calculating the target preset frequency according to a comparison resultAnd obtaining the matching result by matching the target preset frequency with the matching degree.

5. The method of claim 1, wherein prior to determining a match between the target differential clock signal and the preset differential clock signal using a target preset frequency of the target differential clock signal, a signal frequency of the preset differential clock signal, and a gating count of the target differential clock signal for a preset period of time, the method further comprises:

Acquiring a preset frequency of the target differential clock signal, wherein the preset frequency is preset according to the signal type of the target differential clock signal;

and adjusting the preset frequency according to a preset frequency proportion to obtain the target preset frequency, wherein the target preset frequency is smaller than the preset frequency.

6. The method of claim 1, wherein testing the frequency of the target differential clock signal based on the matching result to determine whether the frequency of the target differential clock signal is abnormal based on the test result comprises:

Determining that the frequency of the target differential clock signal is in an abnormal state under the condition that the matching degree between the target differential clock signal and the preset differential clock signal displayed in the matching result is smaller than the preset matching degree, wherein the abnormal state is used for indicating that a clock signal line of the target differential clock signal is short-circuited or open-circuited;

And under the condition that the matching degree between the target differential clock signal and the preset differential clock signal is larger than the preset matching degree, determining that the frequency of the target differential clock signal is in a normal state.

7. The method of claim 1, wherein after testing the frequency of the target differential clock signal according to the matching result to determine whether the frequency of the target differential clock signal is abnormal based on the test result, the method further comprises:

Converting the test result into a level signal, wherein when the level signal is a high level signal, the frequency of the target differential clock signal is in a normal state, and when the level signal is a low level signal, the frequency of the target differential clock signal is in an abnormal state;

transmitting the level signal to a boundary scan test device, wherein the boundary scan test device is configured to identify the level signal and display an identification result, and a format of the identification result includes at least one of: text format, digital format, signal format supported by the transport protocol of the boundary scan test equipment.

8. The method of claim 7, wherein after converting the test result to a level signal, the method further comprises:

Sending a prompt instruction to prompt equipment according to the level signal so as to control the prompt equipment to send prompt information according to the prompt instruction, wherein the prompt instruction comprises the test result, the prompt information is used for prompting whether the frequency of the target differential clock signal is in an abnormal state or not, and the prompt information comprises at least one of the following components: voice prompt and color prompt.

9. A frequency testing apparatus, comprising: a connector, a processing chip and a transmission device, wherein,

The processing chip is connected with the connector and is used for receiving the differential clock signal generated by the clock source equipment through the connector, and the method of any one of claims 1 to 8 is deployed on the processing chip;

10. The apparatus of claim 9, wherein the processing chip has an amplifier, a processor, and a counter disposed therein,

The amplifier is connected with the connector and is used for adjusting the signal vibration amplitude of the differential clock signal according to the preset signal vibration amplitude to obtain the target differential clock signal;

The processor is connected with the amplifier and is used for receiving the target differential clock signal sent by the amplifier;

The counter is connected with the processor, and is used for receiving the target differential clock signal sent by the processor and determining a gating count of the target differential clock signal in a preset time period, wherein the gating count is used for representing the pulse number or the period number of the target differential clock signal in the preset time period;

The processor is further configured to determine a matching result between the target differential clock signal and the preset differential clock signal by using a target preset frequency of the target differential clock signal, a signal frequency of the preset differential clock signal, and a gating count of the target differential clock signal in a preset time period, and test the frequency of the target differential clock signal according to the matching result, so as to determine whether the frequency of the target differential clock signal is abnormal based on the test result.

11. The apparatus of claim 10, wherein the processing chip further has a field programmable gate array device disposed therein, wherein,

The field programmable gate array device is connected with the processor and is used for transmitting the level signal to boundary scan test equipment connected with the field programmable gate array device, wherein the boundary scan test equipment is used for identifying the level signal and displaying an identification result, and the format of the identification result comprises at least one of the following components: text format, digital format, signal format supported by the transport protocol of the boundary scan test equipment.

12. The apparatus of claim 11, wherein the field programmable gate array device comprises an input pin and an output pin, wherein,

The input pin is connected with the processor and used for transmitting the level signal to the output pin;

The output pin is connected with the boundary scan test equipment and used for transmitting the level signal to the boundary scan test equipment.

13. The apparatus of claim 12, wherein the processing chip further has a hint device disposed therein, wherein,

14. The apparatus of claim 11, wherein the frequency testing apparatus further comprises a switching device comprising a first switching interface and a second switching interface, wherein,

The first switching interface is connected with the connector and used for transmitting the differential clock signal to the connector;

The second switching interface is connected with the field programmable gate array device and used for transmitting other signals to the field programmable gate array device, wherein the field programmable gate array device is connected with the field programmable gate array device and used for testing whether the frequencies of the other signals are abnormal or not.

15. A computer program product comprising a computer program, characterized in that the computer program, when being executed by a processor, implements the steps of the method as claimed in any one of claims 1 to 8.

16. A computer readable storage medium, characterized in that a computer program is stored in the computer readable storage medium, wherein the computer program, when being executed by a processor, implements the steps of the method according to any of the claims 1 to 8.

17. An electronic device comprising a memory, a processor and a computer program stored on the memory and executable on the processor, characterized in that the processor implements the steps of the method of any one of claims 1 to 8 when the computer program is executed.