CN118099205A

CN118099205A - Semiconductor device and method for manufacturing the same

Info

Publication number: CN118099205A
Application number: CN202410417676.4A
Authority: CN
Inventors: 张雪
Original assignee: Innoscience Zhuhai Technology Co Ltd
Current assignee: Innoscience Zhuhai Technology Co Ltd
Priority date: 2024-04-09
Filing date: 2024-04-09
Publication date: 2024-05-28

Abstract

The application provides a semiconductor device and a method for manufacturing the same. The semiconductor device comprises a substrate, and a channel layer, a barrier layer and a p-type cap layer which are sequentially laminated on the substrate. The p-type cap layer comprises a first p-type cap layer, a barrier layer and a second p-type cap layer which are sequentially stacked on the barrier layer, the barrier layer comprises a first barrier layer, a first potential well layer and a second barrier layer which are sequentially stacked on the first p-type cap layer, the forbidden band width of the first barrier layer is larger than that of the first potential well layer, and the forbidden band width of the second barrier layer is larger than that of the first potential well layer. It is possible to improve the voltage resistance and reliability of the gate electrode in the semiconductor device.

Description

Semiconductor device and method for manufacturing the same

Technical Field

The application relates to the technical field of semiconductor devices, in particular to a semiconductor device and a preparation method thereof.

Background

The semiconductor device may include a heterojunction bipolar transistor (heterojunction bipolar transistor, HBT), a heterojunction field effect transistor (heterojunction FIELD EFFECT transistor, HFET), a high electron mobility transistor (high electron mobility transistor, HEMT), a modulation doped FET (MODFET), and the like. The HEMT device may include an enhancement HEMT device and a depletion HEMT device, for example, the enhancement HEMT device may include a p-GaN (p-type gallium nitride) gate structure enhancement HEMT device, where the p-GaN gate structure has a relatively complex mechanism of action, and the voltage withstand capability and reliability of the p-GaN gate structure remain to be further improved.

Disclosure of Invention

The application aims at the defects of the related art, and provides a semiconductor device and a preparation method thereof, which are used for solving the problem that the voltage resistance and the reliability of a grid electrode of the semiconductor device in the related art are still to be improved.

The application provides a semiconductor device, which comprises a substrate, and a channel layer, a barrier layer and a p-type cap layer which are sequentially laminated on the substrate. The p-type cap layer comprises a first p-type cap layer, a blocking layer and a second p-type cap layer which are sequentially stacked on the barrier layer, the blocking layer comprises a first barrier layer, a first potential well layer and a second barrier layer which are sequentially stacked on the first p-type cap layer, the forbidden band width of the first barrier layer is larger than that of the first potential well layer, and the forbidden band width of the second barrier layer is larger than that of the first potential well layer.

The application also provides a preparation method of the semiconductor device, which comprises the following steps:

Sequentially forming a channel layer and a barrier layer on a substrate;

Forming a p-type cap layer on the barrier layer; the p-type cap layer comprises a first p-type cap layer, a barrier layer and a second p-type cap layer which are sequentially stacked on the barrier layer, the barrier layer comprises a first barrier layer, a first potential well layer and a second barrier layer which are sequentially stacked on the first p-type cap layer, the forbidden band width of the first barrier layer is larger than that of the first potential well layer, and the forbidden band width of the second barrier layer is larger than that of the first potential well layer.

The beneficial effects of the application include:

Compared with the prior art that two sides of the p-type cap layer are respectively and directly contacted with the grid electrode and the barrier layer, the barrier layer is additionally arranged in the p-type cap layer and comprises a barrier-well-barrier sandwich stacking structure formed by the first barrier layer, the first potential well layer and the second barrier layer, on one hand, when the grid electrode is arranged on one side of the p-type cap layer far away from the barrier layer, avalanche breakdown caused by a triangular barrier with super-strong interface between the second p-type cap layer and the grid electrode can be prevented, and injection of holes can be prevented; on the other hand, two-dimensional electron gas (2 DEG) generated at the interface of the channel layer and the barrier layer can be prevented from being injected into the first p-type cap layer, so that the risk of electric leakage of the grid electrode is reduced, and the voltage withstand capability of the grid electrode of the semiconductor device is improved.

Additional aspects and advantages of the application will be set forth in part in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.

Drawings

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.

Fig. 1 is a schematic view showing a structure of a semiconductor device in the related art;

Fig. 2 to fig. 7 are schematic structural diagrams of a semiconductor device according to an embodiment of the present application;

Fig. 8a to 8c are schematic structural diagrams of each step of a method for manufacturing a semiconductor device according to an embodiment of the present application;

Fig. 9a to fig. 9e are schematic structural diagrams illustrating steps of another method for manufacturing a semiconductor device according to an embodiment of the present application;

FIGS. 10a to 10g are schematic views illustrating the structure of each step of a method for manufacturing a semiconductor device according to another embodiment of the present application;

fig. 11 is a schematic diagram showing energy band distribution of a semiconductor device according to an embodiment of the present application.

In the figure: 1-a substrate; a 2-channel layer; a 3-barrier layer; 31-grooves; 41-grid electrode; 42-source; 43-drain electrode; a 5-p type cap layer; 51-a first p-type cap layer; 52-a barrier layer; 521-a first barrier layer; 522-a first potential well layer; 523-a second barrier layer; 53-a second p-type cap layer; 6-passivation layer; 7-a mask layer; 71-concave holes.

Detailed Description

Reference will now be made in detail to exemplary embodiments, examples of which are illustrated in the accompanying drawings. When the following description refers to the accompanying drawings, the same numbers in different drawings refer to the same or similar elements, unless otherwise indicated. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with the present application. Rather, they are merely examples of apparatus and methods consistent with aspects of the application as detailed in the accompanying claims.

The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. As used in this specification and the appended claims, the singular forms "a," "an," and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It should also be understood that the term "and/or" as used herein refers to and encompasses any or all possible combinations of one or more of the associated listed items.

It will be understood that when a layer, an area, or a structure is described as being "on" or "over" another layer, another area, it can be referred to as being directly on the other layer, another area, or another layer or area can be included between the layer and the other layer, another area. And if the component is turned over, that layer, one region, will be "under" or "beneath" the other layer, another region.

It has been found that the enhancement mode HEMT device may include a p-GaN (p-type gallium nitride) gate structure enhancement mode HEMT device, the structure of which is shown in fig. 1, including a substrate 1, a GaN channel layer 2, an AlGaN barrier layer 3, a p-GaN layer 5' and a gate 41, and a source 42 and a drain 43 on both sides of the gate, which are sequentially stacked. Compared with a depletion type HEMT device, the p-GaN gate structure enhancement type HEMT device is characterized in that a p-GaN layer 5 'is introduced between the lower part of a gate and an AlGaN barrier layer, the p-GaN layer 5' can improve the energy band at an AlGaN/GaN heterojunction interface, and when the gate bias voltage is 0V, the p-GaN gate structure enhancement type HEMT device is higher than the fermi level, so that two-dimensional electron gas (2-dimensional electron gas,2 DEG) in the area below the gate is exhausted, and the normally-off characteristic is realized. However, when schottky contact is formed between the p-GaN layer and the gate metal, an avalanche breakdown phenomenon occurs in the triangular barrier at the super-strong interface between the p-GaN layer and the gate metal, and thus the voltage resistance and reliability of the gate in the transistor may be affected. In addition, in order to obtain a p-type conductive GaN layer, magnesium (Mg) is often used as a dopant to dope the GaN material, but Mg dopant has low solubility in GaN and high ionization energy of Mg, so it is difficult to achieve a sufficiently high hole concentration, resulting in that 2DEG under the gate is hardly completely consumed, 2DEG will inevitably diffuse into the gate to cause gate leakage, and gate withstand voltage is reduced.

The application provides a semiconductor device and a preparation method thereof, which aim to solve the technical problems in the related art.

Hereinafter, a semiconductor device and a method for manufacturing the same in an embodiment of the present application will be described in detail with reference to the accompanying drawings. The features of the embodiments described below can be supplemented or combined with one another without conflict.

The embodiment of the application provides a semiconductor device, as shown in fig. 2, the semiconductor device comprises a channel layer 2, a potential barrier layer 3 and a p-type cap layer 5 which are sequentially stacked on a substrate 1, wherein the p-type cap layer 5 comprises a first p-type cap layer 51, a barrier layer 52 and a second p-type cap layer 53 which are sequentially stacked on the potential barrier layer 3, the barrier layer 52 comprises a first potential barrier layer 521, a first potential well layer 522 and a second potential barrier layer 523 which are sequentially stacked on the first p-type cap layer 51, the energy gap of the first potential barrier layer 521 is larger than the energy gap of the first potential well layer 522, and the energy gap of the second potential barrier layer 523 is larger than the energy gap of the first potential well layer 522.

Compared with the p-type cap layer 5 'in fig. 1, in which both sides of the p-type cap layer 5' are respectively in direct contact with the gate 41 and the barrier layer 3, the present embodiment adds the barrier layer 52 in the p-type cap layer 5, and the barrier layer 52 includes a barrier-well-barrier sandwich stack structure formed by the first barrier layer 521, the first potential well layer 522 and the second barrier layer 523, as shown in fig. 11, (i) acceleration of electrons and holes in the figure; (ii) defects generated by high-energy electrons. On the other hand, when the gate 41 is disposed on the side of the p-type cap layer 5 away from the barrier layer 3, avalanche breakdown due to a triangular barrier with a super-strong interface between the second p-type cap layer 53 and the gate 41 can be prevented, and injection of holes can be prevented. On the other hand, two-dimensional electron gas (2 DEG) generated at the interface between the channel layer 2 and the barrier layer 3 is prevented from being injected into the first p-type cap layer 51, so that the risk of leakage of the gate 41 is reduced, and the voltage-withstanding capability of the gate 41 of the semiconductor device is improved.

In some embodiments, the substrate 1 may comprise silicon (Si), doped Si, silicon carbide (SiC), germanium silicide (SiGe), gallium arsenide (GaAs) or other semiconductor material, as well as sapphire, silicon-on-insulator (SOI) or other suitable material.

In some embodiments, the channel layer 2 may comprise a nitride, such as gallium nitride (GaN), aluminum nitride (AlN), aluminum gallium nitride (AlxGa 1-xN, where 0 < x < 1), and the like. The channel layer 2 may be gallium nitride (GaN), and the forbidden band width of GaN is about 3.4eV. Furthermore, a buffer layer may be provided between the channel layer 2 and the substrate 1, the buffer layer being for reducing lattice mismatch between the substrate 1 and the channel layer 2.

In some embodiments, barrier layer 3 may comprise a group III-V compound, such as the compound InAlGaN (InaAlbGa-a-bN, where a+b.ltoreq.1). Further, the barrier layer 3 may include a compound of aluminum gallium nitride (AlxGa 1-xN, where x.ltoreq.1), and a compound of indium aluminum nitride (InxAl 1-xN, where x < 1). The forbidden bandwidth of the barrier layer 3 can be larger than that of the channel layer 2, the barrier layer 3 can be indium gallium nitride (AlxGa 1-xN, wherein x is less than or equal to 1), and the forbidden bandwidth of the AlxGa1-xN is about 3.4-6.2 eV.

It should be noted that, due to the energy band difference between the channel layer 2 and the barrier layer 3, the barrier layer 3 may form a potential well for electrons, so that the electrons may be limited to move in a direction perpendicular to the barrier layer 3, and may freely move in a plane of the barrier layer 3, thereby forming a two-dimensional electron gas (2 DEG) region.

The p-type cap layer 5 includes a first p-type cap layer 51, a barrier layer 52, and a second p-type cap layer 53 stacked in this order on the barrier layer 3. The side of the first p-type cap layer 51 remote from the barrier layer 52 is in contact with the barrier layer 3 and the side of the second p-type cap layer 53 remote from the barrier layer 52 is in contact with the gate 41. A p-type dopant may be included in the first p-type cap layer 51 and/or the second p-type cap layer 53. In some embodiments, the first p-type cap layer 51 may include a p-doped GaN layer, a p-doped AlGaN layer, a p-doped AlN layer, or other suitable III-V compound semiconductor material layer. The second p-type cap layer 53 may include a p-doped GaN layer, a p-doped AlGaN layer, a p-doped AlN layer, or other suitable III-V compound semiconductor material layer. The p-type dopant may include magnesium (Mg), beryllium (Be), zinc (Zn), and cadmium (Cd).

Note that the materials of the first p-type cap layer 51 and the second p-type cap layer 53 may be the same or different, and in one example, the first p-type cap layer 51 and the second p-type cap layer 53 are both p-doped GaN layers. In another example, the first p-type cap layer 51 is a p-doped GaN layer and the second p-type cap layer 53 is a p-doped AlGaN layer. The p-type dopants doped in each of the first and second p-type cap layers 51 and 53 may be the same or different. In one example, the p-type dopants doped in the first and second p-type cap layers 51, 53 are both magnesium (Mg). In another example, the p-type dopant of the first p-type cap layer 51 is magnesium (Mg) and the p-type dopant of the second p-type cap layer 53 is zinc (Zn).

The p-type cap layer 5 may be used to control the concentration of 2DEG in the channel layer 2, and in particular may be used to deplete the 2DEG under the p-type cap layer 5. However, when the p-type dopant is doped in the p-type cap layer 5, it is affected by the p-type dopant, for example, when the p-type dopant is magnesium (Mg), the solubility of Mg dopant in GaN is low, and the ionization energy of Mg is high, and thus, it is difficult to achieve a sufficiently high hole concentration, resulting in that the 2DEG under the p-type cap layer 5 is hardly completely consumed, the 2DEG will inevitably diffuse into the gate 41 to cause leakage of the gate 41, resulting in a decrease in the voltage withstand capability of the gate 41. Therefore, compared with the conventional semiconductor structure in which only a single p-type cap layer 5 is provided, in this embodiment, a barrier-well-barrier sandwich stack structure is added in the p-type cap layer 5, so that the 2DEG under the p-type cap layer 5 is prevented from being implanted into the p-type cap layer 5, thereby reducing the leakage current of the gate 41 and improving the voltage-withstanding capability of the gate 41.

In some embodiments, the forbidden bandwidth of the first potential well layer 522 is less than or equal to 3.4eV. The first potential well layer 522 may include gallium nitride (GaN), indium nitride (InN), and indium gallium nitride (inxga 1-xN, where 0 < x < 1). The first potential well layer 522 may include gallium nitride (GaN). Gallium nitride (GaN) has a forbidden bandwidth of about 3.4eV.

In some embodiments, the forbidden bandwidth of the first barrier layer 521 is greater than 3.4eV. The forbidden bandwidth of the second barrier layer 523 is greater than 3.4eV. The first barrier layer 521 may include Boron Nitride (BN), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN), aluminum nitride (AlN), gallium oxide (Ga ₂O₃), and aluminum gallium nitride (AlxGa 1-xN, where 0 < x < 1). The second barrier layer 523 may include Boron Nitride (BN), hexagonal boron nitride (h-BN), cubic boron nitride (c-BN), aluminum nitride (AlN), gallium oxide (Ga ₂O₃), and aluminum gallium nitride (AlxGa 1-xN, where 0 < x < 1). The first barrier layer 521 may include Boron Nitride (BN). The second barrier layer 523 may include Boron Nitride (BN). The forbidden bandwidth of Boron Nitride (BN) is about 6.4eV.

The materials of the first barrier layer 521 and the second barrier layer 523 may be the same or different. In one example, the first barrier layer 521 and the second barrier layer 523 are both made of Boron Nitride (BN). In the BN/GaN/BN stacked structure formed in this example, BN, which is a wide bandgap semiconductor material, has high thermal conductivity, high resistivity, high mobility, low dielectric constant, high breakdown field, can realize double doping, and has good stability, and is suitable for manufacturing electronic devices used under extreme conditions. In another example, the material of the first barrier layer 521 is Boron Nitride (BN), and the material of the second barrier layer 523 is aluminum nitride (AlN).

In some embodiments, as shown in fig. 3, a groove 31 is provided on a side of the barrier layer 3 away from the substrate 1, at least a portion of the first p-type cap layer 51 is located in the groove 31, and a distance d1 between a side of the first p-type cap layer 51 away from the substrate 1 and the substrate 1 is greater than a distance d2 between a side of the barrier layer 3 away from the substrate 1 and the substrate 1. In this embodiment, the recess 31 is added in the barrier layer 3, so that the height of the whole device can be reduced, and the integration level of the device can be improved.

In some embodiments, as shown in fig. 4, a groove 31 is disposed on a side of the barrier layer 3 away from the substrate 1, a first p-type cap layer 51 is disposed in the groove 31, and an orthographic projection of the barrier layer 52 on the substrate 1 is located within an orthographic projection of the first p-type cap layer 51 on the substrate 1, and a projected area of the orthographic projection of the first p-type cap layer 51 on the substrate 1 is larger than a projected area of the orthographic projection of the barrier layer 52 on the substrate 1. In this embodiment, the groove 31 is added in the barrier layer 3 and the first p-type cap layer 51 is completely filled in the groove 31, so that the height of the whole device can be reduced, the integration level of the device can be improved, and the preparation process can be more flexible. In addition, in this embodiment, the first p-type cap layer 51 is located in the groove 31, and the first p-type cap layer 51 may be formed by depositing a cap layer that is not doped p-type in the groove 31, and then doping a p-type dopant into the cap layer in the groove 31 by ion implantation.

In some embodiments, as shown in fig. 2-4, a gate 41 is disposed on a side of the p-type cap layer 5 away from the barrier layer 3, and schottky contact is formed between the gate 41 and the p-type cap layer 5. Further, a schottky contact is formed between the second p-type cap layer 53 and the gate 41. The material of the gate 41 may include titanium (Ti), tantalum (Ta), tungsten (W), aluminum (Al), cobalt (Co), copper (Cu), nickel (Ni), platinum (Pt), lead (Pb), molybdenum (Mo) and their compounds (such as but not limited to titanium nitride (TiN), tantalum nitride (TaN), other conductive nitrides or conductive oxides), metal alloys (such as aluminum copper alloys (A1-Cu)), or other suitable materials.

In some embodiments, the orthographic projection of gate 41 onto substrate 1 is located within the orthographic projection of p-type cap layer 5 onto substrate 1. In one example, as shown in fig. 2, the front projection of gate 41 onto substrate 1 is fully coincident with the front projection of p-type cap layer 5 onto substrate 1. In another example, as shown in fig. 5, the front projection of gate 41 onto substrate 1 is less than the front projection of p-type cap layer 5 onto substrate 1. In yet another example, as shown in fig. 6, at least part of the gate 41 covers a side surface and a side surface of the second p-type cap layer 53 away from the substrate 1, and a distance d3 between a side of the gate 41 close to the barrier layer 3 and the barrier layer 3 is greater than a distance d4 between a side of the second p-type cap layer 53 close to the barrier layer 3 and the barrier layer 3.

In some embodiments, as shown in fig. 2 to 6, a source 42 and a drain 43 are further disposed on the barrier layer 3, and the source 42 and the drain 43 are both in contact with the barrier layer 3. The source 42 may comprise a conductive material, which may comprise a metal, an alloy, a doped semiconductor material (e.g., doped crystalline silicon), or other suitable conductive material, such as Ti, A1, ni, cu, au, pt, pd, W, tiN, or other suitable material. Drain 43 may comprise a conductive material, which may comprise a metal, an alloy, a doped semiconductor material (e.g., doped crystalline silicon), or other suitable conductive material, such as Ti, A1, ni, cu, au, pt, pd, W, tiN, or other suitable material.

In some embodiments, as shown in fig. 2-6, the source 42 and the drain 43 may be disposed on opposite sides of the gate 41. In other embodiments, although not shown, a portion of the source electrode 42 may extend into the barrier layer 3 or penetrate the barrier layer 3 to extend into the channel layer 2, and a portion of the drain electrode 43 may extend into the barrier layer 3 or penetrate the barrier layer 3 to extend into the channel layer 2.

In some embodiments, as shown in fig. 7, the semiconductor device further comprises a passivation layer 6 overlying the barrier layer 3. The material of the passivation layer 6 (Passivation layer) in this embodiment may be phosphosilicate glass (Phosphorosilicate Glass, PSG), borophosphosilicate glass (Boron-phosphorosilicate Glass, BPSG), silicon nitride (Si 3N 4), silicon oxynitride (SiOxNy), aluminum oxide (Al 2O 3), or the like. In one example, the passivation layer 6 is in contact with the first p-type cap layer 51, and the passivation layer 6 is not in contact with the blocking layer 52, so that the blocking layer 52 is prevented from being affected by the passivation layer 6, and the blocking layer 52 can be ensured to successfully block hole injection.

The embodiment of the application also provides a preparation method of the semiconductor device, which is shown in combination with fig. 2, and comprises the following steps:

s100: forming a channel layer 2 and a barrier layer 3 in sequence on a substrate 1;

s200: forming a p-type cap layer 5 on the barrier layer 3; the p-type cap layer 5 includes a first p-type cap layer 51, a barrier layer 52, and a second p-type cap layer 53 sequentially stacked on the barrier layer 3, the barrier layer 52 includes a first barrier layer 521, a first potential well layer 522, and a second barrier layer 523 sequentially stacked on the first p-type cap layer 51, a band gap width of the first barrier layer 521 is larger than a band gap width of the first potential well layer 522, and a band gap width of the second barrier layer 523 is larger than a band gap width of the first potential well layer 522.

The semiconductor device manufactured by the manufacturing method of the semiconductor device provided in this embodiment also has the barrier layer 52 of the barrier-well-barrier stack structure, so that all the advantages of the semiconductor device mentioned in the above embodiment are provided, and the description thereof is omitted here.

Specifically, the embodiment of the application provides the preparation methods of the semiconductor device of the following three embodiments.

In a first embodiment, a method of manufacturing a semiconductor device includes the steps of:

S100: as shown in fig. 8a, a channel layer 2 and a barrier layer 3 are sequentially formed on a substrate 1;

S210: as shown in fig. 8b, a p-type cap layer 5 is epitaxially grown on the barrier layer 3;

s220: as shown in fig. 8c, the p-type cap layer 5 is patterned.

The p-type cap layer 5 may be formed by epitaxial growth in this embodiment. Epitaxial growth methods may include hydride epitaxial growth (HVPE), molecular Beam Epitaxy (MBE), and Metal Organic Chemical Vapor Deposition (MOCVD).

In a second embodiment, a method of manufacturing a semiconductor device includes the steps of:

s100': as shown in fig. 9a, a channel layer 2 and a barrier layer 3 are sequentially formed on a substrate 1;

S210': as shown in fig. 9b, a mask layer 7 is formed on the barrier layer 3, and a concave hole 71 is formed on the mask layer 7, wherein the concave hole 71 exposes the barrier layer 3;

S220': as shown in fig. 9c, a first p-type cap layer 51 and a barrier layer 52 are sequentially formed within the recess hole 71; the distance d5 between the barrier layer 3 and the side of the barrier layer 52 remote from the barrier layer 3 is smaller than the distance d6 between the barrier layer 3 and the side of the mask layer 7 remote from the barrier layer 3;

s230': a second p-type cap layer 53 is formed on the side of the barrier layer 52 remote from the first p-type cap layer 51.

In this embodiment, the recess 71 is formed on the mask layer 7, and the position of the p-type cap layer 5 is defined by the structure of the recess 71, so that the process of etching the p-type cap layer 5 can be omitted, the problem that the barrier layer 3 is uneven due to residual or excessive etching of the p-type cap layer material possibly generated during etching the p-type cap layer 5 in the related art is avoided, and the uniformity of the barrier layer 3 can be improved. In addition, after the step of growing the barrier layer 3 and the step of growing the p-type cap layer 5 are separated, more process flexibility can be brought, for example, after the barrier layer 3 is grown, the passivation layer 6 is grown on the surface of the barrier layer 3 without etching damage, and interface states and dangling bonds on the surface of the barrier layer 3 can be further reduced, so that the performance of the semiconductor device is further improved.

Considering that p-type conductivity is typically achieved by doping the p-type dopants in first and second p-type caps 51 and 53, in one embodiment, first and/or second p-type caps 51 and 53 may be formed by first forming undoped cap material within wells 71 and then subjecting the cap material located within wells 71 to a doping process. In one example, the doping process may include a sputtering and annealing process in combination.

Further considering that the concentration of the p-type dopant that is doped after growth may be unevenly distributed, it is necessary to remove the excess p-type dopant by an additional step. The present embodiment can also form the first p-type cap layer 51 by doping a p-type dopant in the first p-type cap layer material in advance as a target material, and then sputter-growing the first p-type cap layer material doped with the p-type dopant in the recess hole 71. The problem of uneven concentration distribution of the p-type dopant caused by doping after sputter growth can be avoided.

Further, S230' may include the steps of:

s231': as shown in fig. 9d, the mask layer 7 and the barrier layer 52 are covered by a second p-type cap layer 53, and at least part of the second p-type cap layer 53 is located in the concave hole 71;

s232': as shown in fig. 9e, the mask layer 7 and the second p-type cap layer 53 overlying the mask layer 7 are removed, leaving the second p-type cap layer 53 overlying the barrier layer 52.

In this embodiment, by directly laying the second p-type cap layer 53 on the mask layer 7, the second p-type cap layer 53 covering the mask layer 7 is removed at the same time as the mask layer 7 is removed, and the second p-type mask layer 7 covering the barrier layer 52 is left. Furthermore, the surface of the barrier layer 3 can be removed by adopting processes such as stripping and the like, so that the problems that the surface interface state and the dangling bond become the constraint center of electrons and further influence the performance of the device caused by etching damage caused by ion beam bombardment in the etching process can be avoided. In addition, the problem of uneven surface of the barrier layer 3 caused by excessive etching to the barrier layer 3 when etching the mask layer 7 can be avoided.

As with sputter growing the first p-type cap layer 51, in some embodiments S230' may also include: the second p-type cap layer 53 is sputter-grown in the recess 71 on the side of the barrier layer 52 remote from the first p-type cap layer 51, and the distance between the side of the second p-type cap layer 53 remote from the barrier layer 3 and the barrier layer 3 is smaller than the distance between the side of the mask layer 7 remote from the barrier layer 3 and the barrier layer 3 (not shown in the figure). The second p-type cap layer 53 can be grown in this embodiment by sputtering directly on the side of the barrier layer 52 remote from the first p-type cap layer 51 in the recess hole 71 without stripping the second p-type cap layer 53 on the mask layer 7 via the mask layer 7.

Further, S200 may include the following steps:

S300 (not shown in the figure, refer to fig. 2 to 6): a gate 41 is formed on the p-type cap layer 5, and a schottky contact is formed between the gate 41 and the p-type cap layer 5. In this embodiment, on the one hand, the blocking layer 52 can block avalanche breakdown between the second p-type cap layer 53 and the gate 41 due to the triangular barrier with super-strong interface, and can block hole injection; on the other hand, the blocking layer 52 can block two-dimensional electron gas (2 DEG) generated at the interface between the channel layer 2 and the barrier layer 3 from being injected into the first p-type cap layer 51, so as to reduce the risk of leakage of the gate 41 and improve the voltage-withstanding capability of the gate 41 of the semiconductor device.

In a third embodiment, a method of manufacturing a semiconductor device includes the steps of:

s100'': as shown in fig. 10a, a channel layer 2 and a barrier layer 3 are sequentially formed on a substrate 1;

S200'': forming a p-type cap layer 5 and a passivation layer 6 on the barrier layer 3; the p-type cap layer 5 includes a first p-type cap layer 51, a barrier layer 52, and a second p-type cap layer 53 sequentially stacked on the barrier layer 3, the barrier layer 52 includes a first barrier layer 521, a first potential well layer 522, and a second barrier layer 523 sequentially stacked on the first p-type cap layer 51, a band gap width of the first barrier layer 521 is larger than a band gap width of the first potential well layer 522, and a band gap width of the second barrier layer 523 is larger than a band gap width of the first potential well layer 522. The distance d7 between the side of the passivation layer 6 remote from the barrier layer 3 and the barrier layer 3 is smaller than the distance d8 between the side of the first p-type cap layer 51 remote from the barrier layer 3 and the barrier layer 3.

Further, S200 "may comprise the steps of:

S210'': as shown in fig. 10b, a passivation layer 6 is laid on the barrier layer 3;

S220'': as shown in fig. 10c, a mask layer 7 is formed on the passivation layer 6, and a concave hole 71 is formed on the mask layer 7, wherein the concave hole 71 exposes the passivation layer 6;

S230'': as shown in fig. 10d, the passivation layer 6 in the recess hole 71 is removed;

S240'': as shown in fig. 10e, a first p-type cap layer 51 and a barrier layer 52 are sequentially formed within the recess hole 71;

S250'': a second p-type cap layer 53 is formed on the side of the barrier layer 52 remote from the first p-type cap layer 51.

Since the passivation layer 6 needs to be in contact with the barrier layer 3, in the foregoing embodiment, in the epitaxial growth manner, after the barrier layer 3 and the p-type cap layer 5 are stacked and formed, the passivation layer 6 may be formed on the barrier layer 3 after a portion of the barrier layer 3 is exposed, which may cause the passivation layer 6 to cover the p-type cap layer 5, and increase the complexity of the subsequent process for removing the passivation layer 6 covering the p-type cap layer 5. The passivation layer 6 is formed on the barrier layer 3 before the mask layer 7 is formed in this embodiment, and the manufacturing process can be simplified.

Further, S250 "may include the steps of:

S251'': as shown in fig. 10f, the mask layer 7 and the barrier layer 52 are covered with a second p-type cap layer 53, and at least part of the second p-type cap layer 53 is located in the concave hole 71;

S252 ''. As shown in fig. 10g, the mask layer 7 and the second p-type cap layer 53 overlying the mask layer 7 are removed, leaving the second p-type cap layer 53 overlying the barrier layer 52.

It is noted that in the drawings, the size of layers and regions may be exaggerated for clarity of illustration. Moreover, it will be understood that when an element or layer is referred to as being "on" another element or layer, it can be directly on the other element or intervening layers may be present. In addition, it will be understood that when an element or layer is referred to as being "under" another element or layer, it can be directly under the other element or intervening layers or elements may be present. In addition, it will be understood that when a layer or element is referred to as being "between" two layers or elements, it can be the only layer between the two layers or elements, or more than one intervening layer or element may also be present. Like reference numerals refer to like elements throughout.

The terms "center," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," and the like are used for convenience in describing and simplifying the description based on the orientation or positional relationship shown in the drawings, and do not denote or imply that the devices or elements referred to must have a particular orientation, be constructed and operated in a particular orientation, and thus should not be construed as limiting the application.

The terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include one or more such feature. In the description of the present application, unless otherwise indicated, the meaning of "a plurality" is two or more.

Other embodiments of the application will be apparent to those skilled in the art from consideration of the specification and practice of the disclosure disclosed herein. This application is intended to cover any variations, uses, or adaptations of the application following, in general, the principles of the application and including such departures from the present disclosure as come within known or customary practice within the art to which the application pertains. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the application being indicated by the following claims.

It is to be understood that the application is not limited to the precise arrangements and instrumentalities shown in the drawings, which have been described above, and that various modifications and changes may be effected without departing from the scope thereof. The scope of the application is limited only by the appended claims.

Claims

1. A semiconductor device, comprising:

A substrate;

a channel layer on the substrate;

A barrier layer on the channel layer;

The p-type cap layer comprises a first p-type cap layer, a blocking layer and a second p-type cap layer which are sequentially stacked on the barrier layer, the blocking layer comprises a first barrier layer, a first potential well layer and a second barrier layer which are sequentially stacked on the first p-type cap layer, the forbidden band width of the first barrier layer is larger than that of the first potential well layer, and the forbidden band width of the second barrier layer is larger than that of the first potential well layer.

2. The semiconductor device of claim 1, wherein a side of the barrier layer remote from the substrate is provided with a recess, at least a portion of the first p-type cap layer being located within the recess, a distance between the side of the first p-type cap layer remote from the substrate and the substrate being greater than a distance between the side of the barrier layer remote from the substrate and the substrate.

3. The semiconductor device according to claim 1, wherein a groove is formed in a side of the barrier layer away from the substrate, the first p-type cap layer is disposed in the groove, an orthographic projection of the barrier layer on the substrate is located within an orthographic projection of the first p-type cap layer on the substrate, and a projected area of the orthographic projection of the first p-type cap layer on the substrate is larger than a projected area of the orthographic projection of the barrier layer on the substrate.

4. The semiconductor device of claim 1, wherein a side of the p-type cap layer remote from the barrier layer is provided with a gate, the gate and the p-type cap layer forming a schottky contact therebetween.

5. The semiconductor device of claim 4, wherein an orthographic projection of the gate electrode on the substrate is located within an orthographic projection of the p-type cap layer on the substrate.

6. The semiconductor device of claim 4, wherein at least a portion of the gate covers a side surface and a side surface of the second p-type cap layer away from the substrate, a distance between a side of the gate adjacent to the barrier layer and the barrier layer being greater than a distance between a side of the second p-type cap layer adjacent to the barrier layer and the barrier layer.

7. The semiconductor device of claim 1, further comprising a passivation layer overlying the barrier layer.

8. The semiconductor device according to claim 1, wherein a forbidden bandwidth of the first potential well layer is less than or equal to 3.4eV.

9. The semiconductor device according to claim 8, wherein the material of the first potential well layer includes any one or more of gallium nitride, indium nitride, and indium gallium nitride.

10. The semiconductor device according to claim 1, wherein a forbidden bandwidth of the first barrier layer is greater than 3.4eV and a forbidden bandwidth of the second barrier layer is greater than 3.4eV.

11. The semiconductor device according to claim 10, wherein a material of the first barrier layer includes any one or more of boron nitride, aluminum nitride, gallium oxide, and aluminum gallium nitride, and a material of the second barrier layer includes any one or more of boron nitride, aluminum nitride, gallium oxide, and aluminum gallium nitride.

12. A method of manufacturing a semiconductor device, comprising:

Sequentially forming a channel layer and a barrier layer on a substrate;

13. The method of manufacturing a semiconductor device according to claim 12, wherein the forming a p-type cap layer over the barrier layer comprises:

Epitaxially growing a p-type cap layer on the barrier layer;

And patterning the p-type cap layer.

14. The method of manufacturing a semiconductor device according to claim 12, wherein the forming a p-type cap layer over the barrier layer comprises:

forming a mask layer on the barrier layer, wherein a concave hole is formed in the mask layer, and the concave hole exposes the barrier layer;

sequentially forming a first p-type cap layer and a barrier layer in the concave hole; the distance between the side of the barrier layer away from the barrier layer and the barrier layer is smaller than the distance between the side of the mask layer away from the barrier layer and the barrier layer;

a second p-type cap layer is formed on a side of the barrier layer remote from the first p-type cap layer.

15. The method of manufacturing a semiconductor device according to claim 14, wherein sequentially forming a first p-type cap layer and a barrier layer in the recess hole comprises:

and sequentially sputtering and growing the first p-type cap layer and the barrier layer in the concave holes.

16. The method of claim 14, wherein forming a second p-type cap layer on a side of the barrier layer away from the first p-type cap layer comprises:

Covering a second p-type cap layer on the mask layer and the barrier layer, wherein at least part of the second p-type cap layer is positioned in the concave hole;

And removing the mask layer and the second p-type cap layer covered on the mask layer, and reserving the second p-type cap layer covered on the barrier layer.

17. The method of manufacturing a semiconductor device according to claim 12, wherein after forming a p-type cap layer over the barrier layer, further comprising:

And forming a grid electrode on the p-type cap layer, wherein a Schottky contact is formed between the grid electrode and the p-type cap layer.

18. A method of manufacturing a semiconductor device, comprising:

Sequentially forming a channel layer and a barrier layer on a substrate;

Forming a p-type cap layer and a passivation layer on the barrier layer; the p-type cap layer comprises a first p-type cap layer, a barrier layer and a second p-type cap layer which are sequentially stacked on the barrier layer, the barrier layer comprises a first barrier layer, a first potential well layer and a second barrier layer which are sequentially stacked on the first p-type cap layer, the forbidden band width of the first barrier layer is larger than that of the first potential well layer, and the forbidden band width of the second barrier layer is larger than that of the first potential well layer; the distance between the side of the passivation layer away from the barrier layer and the barrier layer is smaller than the distance between the side of the first p-type cap layer away from the barrier layer and the barrier layer.

19. The method of manufacturing a semiconductor device according to claim 18, wherein the forming a p-type cap layer and a passivation layer on the barrier layer comprises:

A passivation layer is paved on the barrier layer;

Forming a mask layer on the passivation layer, wherein a concave hole is formed in the mask layer, and the concave hole exposes the passivation layer;

Removing the passivation layer in the concave holes;

sequentially forming a first p-type cap layer and a barrier layer in the concave hole;